soc: silabs: Add support for xG29 device family
Add EFR32MG29 and EFR32BG29 device families. Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
This commit is contained in:
Aksel Skauge Mellbye
Benjamin Cabé
parent
5645adb251
commit
2d3539b19a
16 changed files with 2884 additions and 2 deletions
23
dts/arm/silabs/xg29/efr32bg29b140f1024im40.dtsi
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23
dts/arm/silabs/xg29/efr32bg29b140f1024im40.dtsi
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@ -0,0 +1,23 @@
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/*
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* Copyright (c) 2025 Silicon Laboratories Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <silabs/xg29/xg29.dtsi>
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/ {
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soc {
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compatible = "silabs,efr32bg29b140f1024im40", "silabs,efr32bg29", "silabs,xg29",
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"silabs,efr32", "simple-bus";
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};
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};
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&sram0 {
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reg = <0x20000000 DT_SIZE_K(256)>;
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};
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&flash0 {
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reg = <0x08000000 DT_SIZE_K(1024)>;
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};
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31
dts/arm/silabs/xg29/efr32bg29b220f1024cj45.dtsi
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31
dts/arm/silabs/xg29/efr32bg29b220f1024cj45.dtsi
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@ -0,0 +1,31 @@
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/*
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* Copyright (c) 2025 Silicon Laboratories Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <silabs/xg29/xg29.dtsi>
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#include <zephyr/dt-bindings/regulator/silabs_dcdc.h>
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/ {
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soc {
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compatible = "silabs,efr32bg29b220f1024cj45", "silabs,efr32bg29", "silabs,xg29",
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"silabs,efr32", "simple-bus";
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};
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};
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&sram0 {
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reg = <0x20000000 DT_SIZE_K(256)>;
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};
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&flash0 {
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reg = <0x08000000 DT_SIZE_K(1024)>;
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};
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&dcdc {
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regulator-boot-on;
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regulator-initial-mode = <SILABS_DCDC_MODE_BOOST>;
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regulator-init-microvolt = <1800000>;
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status = "okay";
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};
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31
dts/arm/silabs/xg29/efr32bg29b221f1024cj45.dtsi
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31
dts/arm/silabs/xg29/efr32bg29b221f1024cj45.dtsi
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@ -0,0 +1,31 @@
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/*
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* Copyright (c) 2025 Silicon Laboratories Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <silabs/xg29/xg29.dtsi>
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#include <zephyr/dt-bindings/regulator/silabs_dcdc.h>
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/ {
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soc {
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compatible = "silabs,efr32bg29b221f1024cj45", "silabs,efr32bg29", "silabs,xg29",
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"silabs,efr32", "simple-bus";
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};
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};
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&sram0 {
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reg = <0x20000000 DT_SIZE_K(192)>;
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};
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&flash0 {
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reg = <0x08000000 DT_SIZE_K(1024)>;
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};
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&dcdc {
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regulator-boot-on;
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regulator-initial-mode = <SILABS_DCDC_MODE_BOOST>;
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regulator-init-microvolt = <1800000>;
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status = "okay";
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};
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31
dts/arm/silabs/xg29/efr32bg29b230f1024cm40.dtsi
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31
dts/arm/silabs/xg29/efr32bg29b230f1024cm40.dtsi
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@ -0,0 +1,31 @@
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/*
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* Copyright (c) 2025 Silicon Laboratories Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <silabs/xg29/xg29.dtsi>
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#include <zephyr/dt-bindings/regulator/silabs_dcdc.h>
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/ {
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soc {
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compatible = "silabs,efr32bg29b230f1024cm40", "silabs,efr32bg29", "silabs,xg29",
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"silabs,efr32", "simple-bus";
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};
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};
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&sram0 {
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reg = <0x20000000 DT_SIZE_K(256)>;
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};
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&flash0 {
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reg = <0x08000000 DT_SIZE_K(1024)>;
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};
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&dcdc {
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regulator-boot-on;
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regulator-initial-mode = <SILABS_DCDC_MODE_BOOST>;
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regulator-init-microvolt = <1800000>;
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status = "okay";
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};
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23
dts/arm/silabs/xg29/efr32mg29b140f1024im40.dtsi
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23
dts/arm/silabs/xg29/efr32mg29b140f1024im40.dtsi
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@ -0,0 +1,23 @@
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/*
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* Copyright (c) 2025 Silicon Laboratories Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <silabs/xg29/xg29.dtsi>
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/ {
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soc {
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compatible = "silabs,efr32mg29b140f1024im40", "silabs,efr32mg29", "silabs,xg29",
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"silabs,efr32", "simple-bus";
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};
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};
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&sram0 {
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reg = <0x20000000 DT_SIZE_K(256)>;
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};
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&flash0 {
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reg = <0x08000000 DT_SIZE_K(1024)>;
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};
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31
dts/arm/silabs/xg29/efr32mg29b230f1024cm40.dtsi
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31
dts/arm/silabs/xg29/efr32mg29b230f1024cm40.dtsi
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/*
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* Copyright (c) 2025 Silicon Laboratories Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <silabs/xg29/xg29.dtsi>
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#include <zephyr/dt-bindings/regulator/silabs_dcdc.h>
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/ {
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soc {
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compatible = "silabs,efr32mg29b230f1024cm40", "silabs,efr32mg29", "silabs,xg29",
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"silabs,efr32", "simple-bus";
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};
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};
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&sram0 {
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reg = <0x20000000 DT_SIZE_K(256)>;
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};
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&flash0 {
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reg = <0x08000000 DT_SIZE_K(1024)>;
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};
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&dcdc {
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regulator-boot-on;
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regulator-initial-mode = <SILABS_DCDC_MODE_BOOST>;
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regulator-init-microvolt = <1800000>;
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status = "okay";
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};
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461
dts/arm/silabs/xg29/xg29.dtsi
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461
dts/arm/silabs/xg29/xg29.dtsi
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@ -0,0 +1,461 @@
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/*
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* Copyright (c) 2025 Silicon Laboratories Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv8-m.dtsi>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/i2c/i2c.h>
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#include <dt-bindings/adc/adc.h>
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#include <dt-bindings/clock/silabs/xg29-clock.h>
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#include <freq.h>
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/ {
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chosen {
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zephyr,flash-controller = &msc;
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zephyr,entropy = &se;
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};
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clocks {
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hfxort: hfxort {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&hfxo>;
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};
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hfrcodpllrt: hfrcodpllrt {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&hfrcodpll>;
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};
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sysclk: sysclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&hfrcodpll>;
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};
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hclk: hclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&sysclk>;
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/* Divisors 1, 2, 4, 8, 16 allowed */
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clock-div = <1>;
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};
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pclk: pclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&hclk>;
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/* Divisors 1, 2 allowed */
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clock-div = <2>;
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};
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lspclk: lspclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&pclk>;
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/* Fixed divisor of 2 */
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clock-div = <2>;
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};
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hclkdiv1024: hclkdiv1024 {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&hclk>;
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/* Fixed divisor of 1024 */
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clock-div = <1024>;
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};
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traceclk: traceclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&sysclk>;
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/* Divisors 1, 2, 3, 4 allowed */
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clock-div = <1>;
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};
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em01grpaclk: em01grpaclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&hfrcodpll>;
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};
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em01grpbclk: em01grpbclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&hfrcodpll>;
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};
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em01grpcclk: em01grpcclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&hfrcodpll>;
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};
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iadcclk: iadcclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&em01grpaclk>;
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};
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em23grpaclk: em23grpaclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&lfrco>;
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};
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em4grpaclk: em4grpaclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&lfrco>;
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};
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rtccclk: rtccclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&lfrco>;
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};
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wdog0clk: wdog0clk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&lfrco>;
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};
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systickclk: systickclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&hclk>;
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};
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eusart0clk: eusart0clk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&em01grpaclk>;
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m33";
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reg = <0>;
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cpu-power-states = <&pstate_em1 &pstate_em2>;
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};
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power-states {
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/*
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* EM1 is a basic "CPU WFI idle", all high-freq clocks remain
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* enabled.
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*/
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pstate_em1: em1 {
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compatible = "zephyr,power-state";
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power-state-name = "runtime-idle";
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min-residency-us = <4>;
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/* HFXO remains active */
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exit-latency-us = <2>;
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};
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/*
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* EM2 is a deepsleep with HF clocks disabled by HW, voltages
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* scaled down, etc.
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*/
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pstate_em2: em2 {
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compatible = "zephyr,power-state";
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power-state-name = "suspend-to-idle";
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min-residency-us = <260>;
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exit-latency-us = <250>;
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};
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};
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};
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sram0: memory@20000000 {
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device_type = "memory";
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compatible = "mmio-sram";
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};
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soc {
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cmu: clock@50008000 {
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compatible = "silabs,series-clock";
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reg = <0x50008000 0x4000>;
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interrupts = <52 0>;
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interrupt-names = "cmu";
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status = "okay";
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#clock-cells = <2>;
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};
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hfxo: hfxo@5000c000 {
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#clock-cells = <0>;
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compatible = "silabs,hfxo";
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reg = <0x5000c000 0x4000>;
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interrupts = <50 0>;
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interrupt-names = "hfxo0";
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clock-frequency = <DT_FREQ_K(38400)>;
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ctune = <140>;
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precision = <50>;
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status = "disabled";
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};
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hfrcodpll: hfrcodpll@50010000 {
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#clock-cells = <0>;
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compatible = "silabs,series2-hfrcodpll";
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reg = <0x50010000 0x4000>;
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interrupts = <51 0>, <56 0>;
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interrupt-names = "hfrco0", "dpll0";
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clock-frequency = <DT_FREQ_M(19)>;
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};
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fsrco: fsrco@50018000 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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reg = <0x50018000 0x4000>;
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clock-frequency = <DT_FREQ_M(20)>;
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};
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lfxo: lfxo@50020000 {
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#clock-cells = <0>;
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compatible = "silabs,series2-lfxo";
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reg = <0x50020000 0x4000>;
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interrupts = <27 0>;
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interrupt-names = "lfxo";
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clock-frequency = <32768>;
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ctune = <63>;
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precision = <50>;
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timeout = <4096>;
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status = "disabled";
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};
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lfrco: lfrco@50024000 {
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#clock-cells = <0>;
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compatible = "silabs,series2-lfrco";
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reg = <0x50024000 0x4000>;
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interrupts = <28 0>;
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interrupt-names = "lfrco";
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clock-frequency = <32768>;
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};
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ulfrco: ulfrco@50028000 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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reg = <0x50028000 0x4000>;
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interrupts = <29 0>;
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interrupt-names = "ulfrco";
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clock-frequency = <1000>;
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};
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clkin0: clkin0@5003c460 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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reg = <0x5003c460 0x4>;
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clock-frequency = <DT_FREQ_M(38)>;
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};
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msc: flash-controller@50030000 {
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compatible = "silabs,gecko-flash-controller";
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reg = <0x50030000 0x4000>;
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interrupts = <55 0>;
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interrupt-names = "msc";
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#address-cells = <1>;
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#size-cells = <1>;
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flash0: flash@8000000 {
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compatible = "soc-nv-flash";
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write-block-size = <4>;
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erase-block-size = <8192>;
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};
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};
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gpio: gpio@5003c000 {
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compatible = "silabs,gecko-gpio";
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reg = <0x5003C000 0x440>;
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interrupts = <31 0>, <30 0>;
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interrupt-names = "GPIO_EVEN", "GPIO_ODD";
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clocks = <&cmu CLOCK_GPIO CLOCK_BRANCH_PCLK>;
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ranges;
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#address-cells = <1>;
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#size-cells = <1>;
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gpioa: gpio@5003c000 {
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compatible = "silabs,gecko-gpio-port";
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reg = <0x5003C000 0x30>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpiob: gpio@5003c030 {
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compatible = "silabs,gecko-gpio-port";
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reg = <0x5003C030 0x30>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpioc: gpio@5003c060 {
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compatible = "silabs,gecko-gpio-port";
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reg = <0x5003C060 0x30>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpiod: gpio@5003c090 {
|
||||
compatible = "silabs,gecko-gpio-port";
|
||||
reg = <0x5003C090 0x30>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl: pin-controller@5003c440 {
|
||||
compatible = "silabs,dbus-pinctrl";
|
||||
reg = <0x5003c440 0xbc0>;
|
||||
};
|
||||
|
||||
dma0: dma@40040000{
|
||||
compatible = "silabs,ldma";
|
||||
reg = <0x40040000 0x4000>;
|
||||
interrupts = <26 0>;
|
||||
interrupt-names = "ldma";
|
||||
#dma-cells = <3>;
|
||||
dma_channels = <8>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart0: usart@5005c000 {
|
||||
compatible = "silabs,gecko-usart";
|
||||
reg = <0x5005C000 0x400>;
|
||||
interrupts = <16 0>, <17 0>;
|
||||
interrupt-names = "rx", "tx";
|
||||
clocks = <&cmu CLOCK_USART0 CLOCK_BRANCH_PCLK>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart1: usart@50060000 {
|
||||
compatible = "silabs,gecko-usart";
|
||||
reg = <0x50060000 0x400>;
|
||||
interrupts = <18 0>, <19 0>;
|
||||
interrupt-names = "rx", "tx";
|
||||
clocks = <&cmu CLOCK_USART1 CLOCK_BRANCH_PCLK>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
burtc0: burtc@50064000 {
|
||||
compatible = "silabs,gecko-burtc";
|
||||
reg = <0x50064000 0x4000>;
|
||||
interrupts = <23 0>;
|
||||
interrupt-names = "burtc";
|
||||
clocks = <&cmu CLOCK_BURTC CLOCK_BRANCH_EM4GRPACLK>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@5a010000 {
|
||||
compatible = "silabs,gecko-i2c";
|
||||
clock-frequency = <I2C_BITRATE_STANDARD>;
|
||||
reg = <0x5a010000 0x4000>;
|
||||
interrupts = <32 0>;
|
||||
interrupt-names = "i2c0";
|
||||
clocks = <&cmu CLOCK_I2C0 CLOCK_BRANCH_LSPCLK>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@50068000 {
|
||||
compatible = "silabs,gecko-i2c";
|
||||
clock-frequency = <I2C_BITRATE_STANDARD>;
|
||||
reg = <0x50068000 0x4000>;
|
||||
interrupts = <33 0>;
|
||||
interrupt-names = "i2c1";
|
||||
clocks = <&cmu CLOCK_I2C1 CLOCK_BRANCH_PCLK>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dcdc: dcdc@50094000 {
|
||||
compatible = "silabs,series2-dcdc";
|
||||
reg = <0x50094000 0x4000>;
|
||||
interrupts = <8 0>;
|
||||
interrupt-names = "dcdc";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
eusart0: eusart@5a040000 {
|
||||
compatible = "silabs,eusart-spi";
|
||||
reg = <0x5A040000 0x4000>;
|
||||
interrupts = <20 0>, <21 0>;
|
||||
interrupt-names = "rx", "tx";
|
||||
clocks = <&cmu CLOCK_EUSART0 CLOCK_BRANCH_EUSART0CLK>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
eusart1: eusart@500b4000 {
|
||||
compatible = "silabs,eusart-spi";
|
||||
reg = <0x500B4000 0x4000>;
|
||||
interrupts = <68 0>, <69 0>;
|
||||
interrupt-names = "rx", "tx";
|
||||
clocks = <&cmu CLOCK_EUSART1 CLOCK_BRANCH_EM01GRPCCLK>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rtcc0: rtcc@58000000 {
|
||||
compatible = "silabs,gecko-stimer";
|
||||
reg = <0x58000000 0x4000>;
|
||||
interrupts = <15 0>;
|
||||
interrupt-names = "rtcc";
|
||||
clocks = <&cmu CLOCK_RTCC CLOCK_BRANCH_RTCCCLK>;
|
||||
clock-frequency = <32768>;
|
||||
prescaler = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdog0: wdog@58018000 {
|
||||
compatible = "silabs,gecko-wdog";
|
||||
reg = <0x58018000 0x4000>;
|
||||
peripheral-id = <0>;
|
||||
interrupts = <49 0>;
|
||||
interrupt-names = "wdog0";
|
||||
clocks = <&cmu CLOCK_WDOG0 CLOCK_BRANCH_WDOG0CLK>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
adc0: adc@5a004000 {
|
||||
compatible = "silabs,gecko-iadc";
|
||||
reg = <0x5a004000 0x4000>;
|
||||
interrupts = <54 0>;
|
||||
interrupt-names = "iadc0";
|
||||
clocks = <&cmu CLOCK_IADC0 CLOCK_BRANCH_IADCCLK>;
|
||||
status = "disabled";
|
||||
#io-channel-cells = <1>;
|
||||
};
|
||||
|
||||
se: semailbox@4c000000 {
|
||||
compatible = "silabs,gecko-semailbox";
|
||||
reg = <0x4c000000 0x1000>;
|
||||
interrupts = <0 3>, <1 3>, <2 3>;
|
||||
interrupt-names = "SETAMPERHOST", "SEMBRX", "SEMBTX";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
bt_hci_silabs: bt_hci_silabs {
|
||||
compatible = "silabs,bt-hci-efr32";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hwinfo: hwinfo {
|
||||
compatible = "silabs,series2-hwinfo";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <4>;
|
||||
};
|
||||
|
|
@ -19,6 +19,8 @@
|
|||
#include <zephyr/dt-bindings/clock/silabs/xg24-clock.h>
|
||||
#elif defined(CONFIG_SOC_SERIES_EFR32BG27)
|
||||
#include <zephyr/dt-bindings/clock/silabs/xg27-clock.h>
|
||||
#elif defined(CONFIG_SOC_SERIES_EFR32BG29) || defined(CONFIG_SOC_SERIES_EFR32MG29)
|
||||
#include <zephyr/dt-bindings/clock/silabs/xg29-clock.h>
|
||||
#endif
|
||||
|
||||
struct silabs_clock_control_cmu_config {
|
||||
|
|
|
|||
80
include/zephyr/dt-bindings/clock/silabs/xg29-clock.h
Normal file
80
include/zephyr/dt-bindings/clock/silabs/xg29-clock.h
Normal file
|
|
@ -0,0 +1,80 @@
|
|||
/*
|
||||
* Copyright (c) 2024 Silicon Laboratories Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* This file was generated by the script gen_clock_control.py in the hal_silabs module.
|
||||
* Do not manually edit.
|
||||
*/
|
||||
|
||||
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG29_CLOCK_H_
|
||||
#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG29_CLOCK_H_
|
||||
|
||||
#include <zephyr/dt-bindings/dt-util.h>
|
||||
#include "common-clock.h"
|
||||
|
||||
/*
|
||||
* DT macros for clock tree nodes.
|
||||
* Defined as:
|
||||
* 0..5 - Bit within CLKEN register
|
||||
* 6..8 - CLKEN register number
|
||||
* Must stay in sync with equivalent SL_BUS_*_VALUE constants in the Silicon Labs HAL to be
|
||||
* interpreted correctly by the clock control driver.
|
||||
*/
|
||||
#define CLOCK_ACMP0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 19))
|
||||
#define CLOCK_AGC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 0))
|
||||
#define CLOCK_AMUXCP0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 11))
|
||||
#define CLOCK_BUFC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 11))
|
||||
#define CLOCK_BURAM (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 28))
|
||||
#define CLOCK_BURTC (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 29))
|
||||
#define CLOCK_SEMAILBOX (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 21))
|
||||
#define CLOCK_DMEM (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 22))
|
||||
#define CLOCK_DCDC (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 31))
|
||||
#define CLOCK_DPLL0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 17))
|
||||
#define CLOCK_ETAMPDET (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 28))
|
||||
#define CLOCK_EUSART0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 20))
|
||||
#define CLOCK_EUSART1 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 23))
|
||||
#define CLOCK_FRC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 3))
|
||||
#define CLOCK_FSRCO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 20))
|
||||
#define CLOCK_GPCRC0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 3))
|
||||
#define CLOCK_GPIO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 26))
|
||||
#define CLOCK_HFRCO0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 18))
|
||||
#define CLOCK_HFXO0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 19))
|
||||
#define CLOCK_I2C0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 14))
|
||||
#define CLOCK_I2C1 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 15))
|
||||
#define CLOCK_IADC0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 10))
|
||||
#define CLOCK_ICACHE0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 16))
|
||||
#define CLOCK_IFADCDEBUG (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 12))
|
||||
#define CLOCK_LDMA0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 0))
|
||||
#define CLOCK_LDMAXBAR0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 1))
|
||||
#define CLOCK_LETIMER0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 12))
|
||||
#define CLOCK_LFRCO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 21))
|
||||
#define CLOCK_LFXO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 22))
|
||||
#define CLOCK_MODEM (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 1))
|
||||
#define CLOCK_MSC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 17))
|
||||
#define CLOCK_PDM (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 25))
|
||||
#define CLOCK_PRORTC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 10))
|
||||
#define CLOCK_PROTIMER (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 4))
|
||||
#define CLOCK_PRS (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 27))
|
||||
#define CLOCK_RAC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 5))
|
||||
#define CLOCK_RADIOAES (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 2))
|
||||
#define CLOCK_RDMAILBOX0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 8))
|
||||
#define CLOCK_RDMAILBOX1 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 9))
|
||||
#define CLOCK_RDSCRATCHPAD (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 7))
|
||||
#define CLOCK_RFCRC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 2))
|
||||
#define CLOCK_RFSENSE (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 14))
|
||||
#define CLOCK_RTCC (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 30))
|
||||
#define CLOCK_SMU (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 15))
|
||||
#define CLOCK_SYNTH (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 6))
|
||||
#define CLOCK_SYSCFG (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 16))
|
||||
#define CLOCK_TIMER0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 4))
|
||||
#define CLOCK_TIMER1 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 5))
|
||||
#define CLOCK_TIMER2 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 6))
|
||||
#define CLOCK_TIMER3 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 7))
|
||||
#define CLOCK_TIMER4 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 18))
|
||||
#define CLOCK_ULFRCO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 23))
|
||||
#define CLOCK_USART0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 8))
|
||||
#define CLOCK_USART1 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 9))
|
||||
#define CLOCK_WDOG0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 13))
|
||||
|
||||
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG29_CLOCK_H_ */
|
||||
2039
include/zephyr/dt-bindings/pinctrl/silabs/xg29-pinctrl.h
Normal file
2039
include/zephyr/dt-bindings/pinctrl/silabs/xg29-pinctrl.h
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -129,7 +129,7 @@ config SOC_GECKO_TRNG
|
|||
config SOC_SILABS_SLEEPTIMER
|
||||
bool
|
||||
select SOC_GECKO_PRS
|
||||
select SOC_GECKO_RTCC if SOC_SERIES_EFR32BG22 || SOC_SERIES_EFR32BG27 || SOC_SERIES_EFR32MG21
|
||||
select SOC_GECKO_RTCC if SOC_FAMILY_SILABS_S2 && $(dt_nodelabel_enabled,rtcc0)
|
||||
help
|
||||
Set if the Sleeptimer HAL module is used.
|
||||
|
||||
|
|
|
|||
43
soc/silabs/silabs_s2/xg29/Kconfig
Normal file
43
soc/silabs/silabs_s2/xg29/Kconfig
Normal file
|
|
@ -0,0 +1,43 @@
|
|||
# Copyright (c) 2025 Silicon Laboratories Inc.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_EFR32BG29
|
||||
select ARM
|
||||
select CPU_CORTEX_M33
|
||||
select CPU_HAS_FPU
|
||||
select CPU_HAS_ARM_MPU
|
||||
select CPU_HAS_ARM_SAU
|
||||
select CPU_CORTEX_M_HAS_DWT
|
||||
select ARMV8_M_DSP
|
||||
select ARM_TRUSTZONE_M
|
||||
select SOC_GECKO_HAS_RADIO
|
||||
select HAS_SILABS_GECKO
|
||||
select HAS_SWO
|
||||
select SOC_GECKO_CMU
|
||||
select SOC_GECKO_EMU
|
||||
select SOC_GECKO_GPIO
|
||||
select SOC_GECKO_DEV_INIT
|
||||
select SOC_GECKO_SE
|
||||
select HAS_PM
|
||||
|
||||
config SOC_SERIES_EFR32MG29
|
||||
select ARM
|
||||
select CPU_CORTEX_M33
|
||||
select CPU_HAS_FPU
|
||||
select CPU_HAS_ARM_MPU
|
||||
select CPU_HAS_ARM_SAU
|
||||
select CPU_CORTEX_M_HAS_DWT
|
||||
select ARMV8_M_DSP
|
||||
select ARM_TRUSTZONE_M
|
||||
select SOC_GECKO_HAS_RADIO
|
||||
select HAS_SILABS_GECKO
|
||||
select HAS_SWO
|
||||
select SOC_GECKO_CMU
|
||||
select SOC_GECKO_EMU
|
||||
select SOC_GECKO_GPIO
|
||||
select SOC_GECKO_DEV_INIT
|
||||
select SOC_GECKO_SE
|
||||
select HAS_PM
|
||||
|
||||
config SOC_GECKO_SDID
|
||||
default 240 if SOC_SERIES_EFR32BG29 || SOC_SERIES_EFR32MG29
|
||||
19
soc/silabs/silabs_s2/xg29/Kconfig.defconfig
Normal file
19
soc/silabs/silabs_s2/xg29/Kconfig.defconfig
Normal file
|
|
@ -0,0 +1,19 @@
|
|||
# Copyright (c) 2025 Silicon Laboratories Inc.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_SERIES_EFR32BG29 || SOC_SERIES_EFR32MG29
|
||||
|
||||
config NUM_IRQS
|
||||
# must be >= the highest interrupt number used
|
||||
default 70
|
||||
|
||||
config PM
|
||||
default n
|
||||
select UART_INTERRUPT_DRIVEN if SERIAL_SUPPORT_INTERRUPT
|
||||
|
||||
choice PM_POLICY
|
||||
default PM_POLICY_DEFAULT
|
||||
depends on PM
|
||||
endchoice
|
||||
|
||||
endif
|
||||
58
soc/silabs/silabs_s2/xg29/Kconfig.soc
Normal file
58
soc/silabs/silabs_s2/xg29/Kconfig.soc
Normal file
|
|
@ -0,0 +1,58 @@
|
|||
# Copyright (c) 2025 Silicon Laboratories Inc.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_SERIES_EFR32BG29
|
||||
bool
|
||||
select SOC_FAMILY_SILABS_S2
|
||||
help
|
||||
Silicon Labs EFR32BG29 (Blue Gecko) Series MCU
|
||||
|
||||
config SOC_SERIES_EFR32MG29
|
||||
bool
|
||||
select SOC_FAMILY_SILABS_S2
|
||||
help
|
||||
Silicon Labs EFR32MG29 (Mighty Gecko) Series MCU
|
||||
|
||||
config SOC_PART_NUMBER_EFR32BG29B140F1024IM40
|
||||
bool
|
||||
select SOC_SERIES_EFR32BG29
|
||||
|
||||
config SOC_PART_NUMBER_EFR32BG29B220F1024CJ45
|
||||
bool
|
||||
select SOC_SERIES_EFR32BG29
|
||||
|
||||
config SOC_PART_NUMBER_EFR32BG29B221F1024CJ45
|
||||
bool
|
||||
select SOC_SERIES_EFR32BG29
|
||||
|
||||
config SOC_PART_NUMBER_EFR32BG29B230F1024CM40
|
||||
bool
|
||||
select SOC_SERIES_EFR32BG29
|
||||
|
||||
config SOC_PART_NUMBER_EFR32MG29B140F1024IM40
|
||||
bool
|
||||
select SOC_SERIES_EFR32MG29
|
||||
|
||||
config SOC_PART_NUMBER_EFR32MG29B230F1024CM40
|
||||
bool
|
||||
select SOC_SERIES_EFR32MG29
|
||||
|
||||
config SOC_SERIES
|
||||
default "efr32bg29" if SOC_SERIES_EFR32BG29
|
||||
default "efr32mg29" if SOC_SERIES_EFR32MG29
|
||||
|
||||
config SOC
|
||||
default "efr32bg29b140f1024im40" if SOC_PART_NUMBER_EFR32BG29B140F1024IM40
|
||||
default "efr32bg29b220f1024cj45" if SOC_PART_NUMBER_EFR32BG29B220F1024CJ45
|
||||
default "efr32bg29b221f1024cj45" if SOC_PART_NUMBER_EFR32BG29B221F1024CJ45
|
||||
default "efr32bg29b230f1024cm40" if SOC_PART_NUMBER_EFR32BG29B230F1024CM40
|
||||
default "efr32mg29b140f1024im40" if SOC_PART_NUMBER_EFR32MG29B140F1024IM40
|
||||
default "efr32mg29b230f1024cm40" if SOC_PART_NUMBER_EFR32MG29B230F1024CM40
|
||||
|
||||
config SOC_PART_NUMBER
|
||||
default "EFR32BG29B140F1024IM40" if SOC_PART_NUMBER_EFR32BG29B140F1024IM40
|
||||
default "EFR32BG29B220F1024CJ45" if SOC_PART_NUMBER_EFR32BG29B220F1024CJ45
|
||||
default "EFR32BG29B221F1024CJ45" if SOC_PART_NUMBER_EFR32BG29B221F1024CJ45
|
||||
default "EFR32BG29B230F1024CM40" if SOC_PART_NUMBER_EFR32BG29B230F1024CM40
|
||||
default "EFR32MG29B140F1024IM40" if SOC_PART_NUMBER_EFR32MG29B140F1024IM40
|
||||
default "EFR32MG29B230F1024CM40" if SOC_PART_NUMBER_EFR32MG29B230F1024CM40
|
||||
|
|
@ -59,6 +59,16 @@ family:
|
|||
- name: efr32zg23
|
||||
socs:
|
||||
- name: efr32zg23b020f512im48
|
||||
- name: efr32bg29
|
||||
socs:
|
||||
- name: efr32bg29b140f1024im40
|
||||
- name: efr32bg29b220f1024cj45
|
||||
- name: efr32bg29b221f1024cj45
|
||||
- name: efr32bg29b230f1024cm40
|
||||
- name: efr32mg29
|
||||
socs:
|
||||
- name: efr32mg29b140f1024im40
|
||||
- name: efr32mg29b230f1024cm40
|
||||
- name: silabs_sim3
|
||||
series:
|
||||
- name: sim3u
|
||||
|
|
|
|||
2
west.yml
2
west.yml
|
|
@ -228,7 +228,7 @@ manifest:
|
|||
groups:
|
||||
- hal
|
||||
- name: hal_silabs
|
||||
revision: 220aac68ab8abaf5b0cf157ddb590a326f656e50
|
||||
revision: 5719804e682e9e4ba1d1f60c824af92a58ce1c2b
|
||||
path: modules/hal/silabs
|
||||
groups:
|
||||
- hal
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue