Commit graph

5973 commits

Author SHA1 Message Date
Ioannis Glaropoulos
2a3852fc75 soc: nrf: add include of nrfx_config_nrf9160.h in nrf9160 soc.h
In soc.h of nRF9160 SoC we need to explicitly include
nrfx_config_nrf9160.h to have the standard peripheral
base address macro mappings in Zephyr builds for nRF9160
SoC. (We need to do this spefically for nRF9160, as those
macros are not present in the nRF9160 MDK header).

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2019-01-25 22:16:49 +01:00
Michael Scott
13c794bc1c serial: RV32M1: introduce lpuart driver / DT bindings
Add a UART driver.

Signed-off-by: Michael Scott <mike@foundries.io>
Signed-off-by: Marti Bolivar <marti@foundries.io>
2019-01-25 11:59:46 -05:00
Michael Scott
0f314ebdda gpio: RV32M1: introduce gpio driver / DT bindings
Add a GPIO driver.

Signed-off-by: Michael Scott <mike@foundries.io>
2019-01-25 11:59:46 -05:00
Michael Scott
cdb1714c6c pinmux: RV32M1: introduce pinmux driver / DT bindings
Add a pinmux driver.

Signed-off-by: Michael Scott <mike@foundries.io>
Signed-off-by: Marti Bolivar <marti@foundries.io>
2019-01-25 11:59:46 -05:00
Marti Bolivar
58d8afb476 interrupt_controller: RV32M1: add intmux driver / DT bindings
Add a level 2 interrupt controller for the RV32M1 SoC. This uses the
INTMUX peripheral.

As a first customer, convert the timer driver over to using this,
adding nodes for the LPTMR peripherals. This lets users select the
timer instance they want to use, and what intmux channel they want to
route its interrupt to, using DT overlays.

Signed-off-by: Marti Bolivar <marti@foundries.io>
Signed-off-by: Mike Scott <mike@foundries.io>
2019-01-25 11:59:46 -05:00
Michael Scott
521f4778a1 clock_control: RV32M1: introduce PCC driver / DT bindings
Add a Peripheral Clock Controller (PCC) driver. This gates and ungates
clocks to various peripherals on the SoC.

Signed-off-by: Michael Scott <mike@foundries.io>
Signed-off-by: Marti Bolivar <marti@foundries.io>
2019-01-25 11:59:46 -05:00
Marti Bolivar
502d306630 soc: riscv32: add RV32M1 SoC as openisa_rv32m1
The OpenISA RV32M1 SoC has four CPU cores. Two of these are RISC-V
32-bit cores, which are named "RI5CY" and "ZERO-RISCY". (The other two
cores are ARM Cortex-M0+ and -M4.) This patch adds basic SoC
enablement for the RISC-V cores:

- basic dtsi, to be extended as additional drivers are added
- SoC definition in soc/riscv32/openisa_rv32m1 for RI5CY / ZERO-RISCY
- system timer driver for RI5CY, based on LPTMR0 peripheral

The timer driver will be generalized a bit soon once proper
multi-level interrupt support is available.

Emphasis is on supporting the RI5CY core as the more capable of the
two; the ZERO-RISCY SoC definitions are a good starting point, but
additional work setting up a dtsi and initial drivers is needed to
support that core.

Signed-off-by: Marti Bolivar <marti@foundries.io>
Signed-off-by: Michael Scott <mike@foundries.io>
2019-01-25 11:59:46 -05:00
Kumar Gala
61cb8b6c4f drivers: wdog: cmsdk: Convert to new DT_<COMPAT>_<INSTANCE> defines
Convert cmsdk driver to use new defines so we can remove the
dts_fixup.h code for it.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-01-25 08:55:06 -06:00
Kumar Gala
4b6cec44ff drivers: uart: cmsdk_apb: Convert to new DT_<COMPAT>_<INSTANCE> defines
Convert cmsdk_apb driver to use new defines so we can remove the
dts_fixup.h code for it.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-01-25 08:55:06 -06:00
Ryan QIAN
fe9ea3b26c arch: arm: nxp: imxrt1064: add device support
- Add SoC information for RT1064

Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
2019-01-24 07:59:52 -06:00
Georgij Cernysiov
3b77737208 soc: st: add STM32L452XC
Adds STM32 L452 soc with L452xC variant. L452 has 160 KB SRAM;
therefore, mpu mem config has been extended; IRQ number is based on
'stm32l452xx.h'.

Signed-off-by: Georgij Cernysiov <g.cernysiov@elco-automation.de>
2019-01-23 03:19:15 -06:00
Aurelien Jarno
0e7a6ec9ab boards: mimxrt1020_evk: Enable mcux ethernet driver and pins
Enables the mcux ethernet driver and pin muxes on the mimxrt1020_evk
board, the same way it is done on the mimxrt1050_evk board. Updates the
board documentation and yaml supported list accordingly.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2019-01-22 08:37:39 -06:00
Aurelien Jarno
ba459d002c soc: nxp_imx: Fix enabling ENET PLL outputs
The ENET PLL should be enabled if the SoC is the MIMXRT1021 (it used by
the ARM core) or if the ENET device is enabled.

The 500MHz clock should be enabled if the SoC is the MIMXRT1021.

The ENET clock should be enabled if the ENET device is enabled.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2019-01-22 08:37:39 -06:00
Aurelien Jarno
17f4d6bec7 soc: nxp_imx: fix ENET_PLL selection for MIMXRT1021
Kconfig currently emits a warning when building for a MIMXRT1021 SoC:

  warning: INIT_ENET_PLL (defined at
  soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1052:66) has direct
  dependencies NET_L2_ETHERNET && SOC_MIMXRT1052 && SOC_SERIES_IMX_RT
  with value n, but is currently being y-selected by the following
  symbols:
   - SOC_MIMXRT1021 (defined at soc/arm/nxp_imx/rt/Kconfig.soc:12),
  with value y, direct dependencies <choice> (value: y), and select
  condition <choice> (value: y)

This is due to the fact the ENET PLL is the one used by the ARM core on
the MIMXRT1021 so it is always enabled, while it is declared protected
by NET_L2_ETHERNET and SOC_SERIES_IMX_RT.

Fix that by declaring the symbol in Kconfig.defconfig.series.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2019-01-22 08:37:39 -06:00
Ioannis Glaropoulos
704e4b446b soc: nrf: clean up inclusions and style fixes
Remove redundant inclusion of nrf.h (included by nrfx.h).
Group the logging/log.h inclusion together with the other
inclusions in this file (make inclusions' list look as in
nrf9160/soc.c).

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2019-01-18 18:27:12 -05:00
Ioannis Glaropoulos
bc5b8e24fe soc: nrf: remove unnecessary macros in mpu_regions.c
Remove the locally-defined macros which define the base
addresses for XICR, Peripheral space and PPB. The macros
are not used.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2019-01-18 18:27:12 -05:00
Kumar Gala
717b647c30 ieee802154: mcr20a: Convert to new DT_<COMPAT>_<INSTANCE> defines
Convert mcr20a driver to use new defines so we can remove the
dts_fixup.h code for it.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-01-18 09:06:10 -06:00
Anas Nashif
15a5fedca7 qmsi: remove handling of qmsi library
Use built-in by default. We do not use external library of QMSI anymore
and rely on integrated HAL. Remove this option and simplify HAL
configuration.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-01-18 06:50:04 -05:00
Maureen Helm
9cad30814d soc: nxp_imx: Enable mcux lpi2c driver and clocks
Enables the mcux lpi2c shim driver and clocks on all imx rt socs when
the i2c driver interface is enabled.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-01-18 06:49:35 -05:00
Rajavardhan Gundi
e584b05215 dts: intel_s1000: Exclude sram space dedicated for mcubootloader
The starting 192kB SRAM is reserved for the mcubootloader. Exclude
this region while building an application to be loaded by mcubootloader.

Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
2019-01-16 21:22:56 -05:00
Rajavardhan Gundi
b5dd8ac37c Kconfig: intel_s1000: Move FIFO_DEPTH to soc Kconfig
FIFO_DEPTH should be in the SoC's Kconfig as this is a
configuration of SPI master controller in SoC.

Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
2019-01-16 21:22:56 -05:00
Savinay Dharmappa
955781b896 boards: nios2: Add dts support for i2c
patch add dts suppoer for i2c.

Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
2019-01-16 12:35:30 -06:00
Maureen Helm
2484e301b1 soc: nxp_imx: Add missing dts fixups for lpuart instance 2
Adds dts fixups for lpuart instance 2, which will be used for the
arduino_serial connection on the mimxrt1020_evk board.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-01-16 12:32:16 -06:00
Erwan Gouriou
e25d6a65ac drivers/pinmux: stm32: Clean up after gpio driver factorization
Clean up a left over from GPIO driver factorization.
Definition of GPIO_REG_SIZE and GPIO_PORTS_BASE do not need anymore
to be spread accross SoCs.
Put these definitions directly in STM32 pinmux driver.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-01-16 08:36:09 -06:00
Ioannis Glaropoulos
1d033a9a26 soc: arm: introduce Kconfig option for Nordic IDAU
This commit introduces a new Kconfig symbol to signify
that a CPU implements the Nordic-specific security
attribution unit. The symbol is meant to be selected
by Nordic SoCs that implement the System Protection
Unit (SPU) peripheral.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2019-01-15 17:18:34 -05:00
Ioannis Glaropoulos
5108990079 soc: nordic: add nRF9160 soc and mpu init configuration
This commit adds the nRF9160 fixup and the source files
for SOC and MPU boot configuration.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2019-01-15 17:18:34 -05:00
Ioannis Glaropoulos
1fa958510f soc: nordic: add Kconfig structure for nRF9160 SOC definition
This commit introduces the Kconfig file structure for nrf9160
SoC in the Zephyr tree.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2019-01-15 17:18:34 -05:00
Karl Zhang
80a9fc3fa1 arm: v2m musca: Add support for v2m musca SoC and board
Support musca board as a variant, it is a Cortex-M33 based SoC.

Signed-off-by: Karl Zhang <karl.zhang@linaro.org>
Signed-off-by: Minos Galanakis <minos.galanakis@arm.com>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-01-15 15:40:37 -06:00
Miguel A. Borrego
aea3645817 soc: select CONFIG_CPU_CORTEX_M_HAS_VTOR for SAMD2x.
SAMD2x series have available the Optional Vector Table Offset Register
(VTOR). If this option is not selected, SCB->VTOR is not configured
properly and the application hangs if it's located in an offset
different than 0.

Removed select CPU_CORTEX_M from SAMD20, as it's already selected by
select CPU_CORTEX_M0PLUS

Signed-off-by: Miguel A. Borrego <jimjim17@gmail.com>
2019-01-15 14:37:19 -06:00
Ioannis Glaropoulos
302a746bd6 drivers: clock control: nrf: rename CLOCK_CONTROL_NRF5 Kconfig symbol
This commit renames the CLOCK_CONTROL_NRF5 Kconfig symbol to
CLOCK_CONTROL_NRF. The change is required to aleviates confusion
when selecting the symbol in nRF9160 SOC definition.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2019-01-15 18:03:24 +01:00
Ioannis Glaropoulos
1aace66c05 soc: nordic: Fix flash driver defines nomenclature in fixup.h
In the wake of 9cbe468a470fe6a103557d4352d37604a632b2fe we need
to update the nomenclature of DT_FLASH_DEV_NAME macros.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2019-01-15 08:17:26 -06:00
Sathish Kuttan
39570b5bae soc: intel_s1000: Add SoC routine for GNA power-up
Add an SoC level routine to turn power and clock on for
Intel GNA block in Intel S1000 SoC.

Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
2019-01-14 08:43:51 -05:00
Andy Ross
b69d0da82d arch/x86_64: New architecture added
This patch adds a x86_64 architecture and qemu_x86_64 board to Zephyr.
Only the basic architecture support needed to run 64 bit code is
added; no drivers are added, though a low-level console exists and is
wired to printk().

The support is built on top of a "X86 underkernel" layer, which can be
built in isolation as a unit test on a Linux host.

Limitations:

+ Right now the SDK lacks an x86_64 toolchain.  The build will fall
  back to a host toolchain if it finds no cross compiler defined,
  which is tested to work on gcc 8.2.1 right now.

+ No x87/SSE/AVX usage is allowed.  This is a stronger limitation than
  other architectures where the instructions work from one thread even
  if the context switch code doesn't support it.  We are passing
  -no-sse to prevent gcc from automatically generating SSE
  instructions for non-floating-point purposes, which has the side
  effect of changing the ABI.  Future work to handle the FPU registers
  will need to be combined with an "application" ABI distinct from the
  kernel one (or just to require USERSPACE).

+ Paging is enabled (it has to be in long mode), but is a 1:1 mapping
  of all memory.  No MMU/USERSPACE support yet.

+ We are building with -mno-red-zone for stack size reasons, but this
  is a valuable optimization.  Enabling it requires automatic stack
  switching, which requires a TSS, which means it has to happen after
  MMU support.

+ The OS runs in 64 bit mode, but for compatibility reasons is
  compiled to the 32 bit "X32" ABI.  So while the full 64 bit
  registers and instruction set are available, C pointers are 32 bits
  long and Zephyr is constrained to run in the bottom 4G of memory.

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2019-01-11 15:18:52 -05:00
Carles Cufi
cee87a1ca2 soc: nrf: Add missing nRF52832 variants
The CIAA and QFAB variants of the nRF52832 were missing in Kconfig,
although present in Device Tree. Add the relevant Kconfig entries in
order to be able to select them.

Fixes #12417

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2019-01-11 10:32:42 +01:00
Aurelien Jarno
074f8a0a26 soc: nxp_imx: Add support for TRNG
Add support for the TRNG device contained in the i.MX RT SoCs. It uses
the existing MCUX driver, and mostly consists in adding the Kconfig and
DTS entries.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2019-01-10 21:22:15 -06:00
Song Qiang
2fb616efbe soc: arm: st_stm32: Using LL library to implement gpio functions
The original implementation of gpio functions access registers
directly. Using LL library can add a set of unifying access
functions for all series of stm32 for avoiding accessing low level
code, and improve readability.

Signed-off-by: Song Qiang <songqiang1304521@gmail.com>
2019-01-10 13:09:19 -06:00
Song Qiang
9612f9d840 soc: arm: st_stm32: Cleanup gpio function code.
All series STM32 have mostly the same GPIO architecture
and can share the same code for GPIO manipulation.
Functions of the external interrupt line control are also the same.
This patch extracts common code from them and put them into the 'common'
folder.

Functions of control GPIO of these series scattered in
soc/arm/st_stm32/stm32xx/ folders contain these functions:
stm32_gpio_flags_to_conf(), stm32_gpio_configure(), stm32_gpio_set(),
stm32_gpio_get, stm32_gpio_enable_int().
This patch merges them into the gpio_stm32.c file.

Signed-off-by: Song Qiang <songqiang1304521@gmail.com>
2019-01-10 13:09:19 -06:00
Wayne Ren
6b5dea578e board: iotdk: bug fixes and remove unsupported drivers config
* i2c, spi, gpio are not tested, remove them now.
* fix the license issue in openocd.cfg
* fix the shell related setting

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2019-01-10 07:05:51 -05:00
Wayne Ren
163625cf78 board: iotdk: necessary clean up based on latest master branch
* clean up the DTS related definitions
* code cleanup
* do the tests/kernel sannity check

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2019-01-10 07:05:51 -05:00
Wayne Ren
022f061632 board: add the initial support of iotdk
The initial support of iotdk which is a board based on Synopsys
ARC IoT SoC.

In this commit, it includes

* processor support
* UART driver

Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2019-01-10 07:05:51 -05:00
Maureen Helm
a9389da038 soc: nxp_imx: Add support for device configuration data (DCD)
Adds support for the device configuration data (DCD), which provides a
sequence of commands to the imx rt boot ROM to initialize components
such as an SDRAM.

It is now possible to use the external SDRAM instead of the internal
DTCM on the mimxrt1020_evk, mimxrt1050_evk, and mimxrt1060_evk. Note,
however, that the default board configurations still link data into
internal DTCM, therefore you must use a device tree overlay to override
"zephyr,sram = &sdram0"

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-01-09 16:01:25 -06:00
Maureen Helm
b5551d0690 soc: boards: Reserve space for the imx boot header at the soc level
Moves the default TEXT_SECTION_OFFSET from the board level to the soc
level for the imx rt series. This offset is used to reserve space for
the imx boot header for external xip flash images.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-01-09 16:01:25 -06:00
Maureen Helm
8e3004953d soc: nxp_imx: Add support for external xip flash boot header
Adds support for the boot data, image vector table, and FlexSPI NOR
config structures used by the imx rt boot ROM to boot an application
from an external xip flash device.

It is now possible to build and flash a bootable zephyr image to the
external xip flash on the mimxrt1020_evk, mimxrt1050_evk, and
mimxrt1060_evk boards via the 'ninja flash' build target and jlink
runner. Note, however, that the default board configurations still link
code into internal ITCM, therefore you must set CONFIG_CODE_HYPERFLASH=y
or CONFIG_CODE_QSPI=y explicitly to override the default. You must also
set CONFIG_NXP_IMX_RT_BOOT_HEADER=y to build the boot header into the
image.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-01-09 16:01:25 -06:00
Ryan QIAN
b416758e9f arch: arm: nxp: imxrt1021: add device support
- Add Soc information for RT1020

Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
2019-01-09 11:39:31 -06:00
Ryan QIAN
e66e6b054c soc: nxp_imx: rt: fix enet pll initialization config macro name
- Update config macro name for enet pll
- Update impacted defconfig of RT1052

Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
2019-01-09 11:39:31 -06:00
Piotr Mienkowski
9f84889779 soc: same70: Add SWO logger support
This commit configures ETM/TPIU clock upon startup in case SWO logger
backend is enabled on Atmel SAM E70 SoC.

Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
2019-01-09 15:30:59 +01:00
Christian Taedcke
e6d5c4e3da soc: silabs_exx32: Add SWO logger support to EFM32PG12B
By default, after reset SWO signal is not connected to GPIO pin.

Signed-off-by: Christian Taedcke <hacking@taedcke.com>
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
2019-01-09 15:30:59 +01:00
Piotr Mienkowski
8bed2d5e27 soc: silabs_exx32: Add SWO logger support
By default, after reset SWO signal is not connected to GPIO pin. This
commit adds required initialization code to enable support for SWO
logger. Not all SoC series support the feature.

Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
2019-01-09 15:30:59 +01:00
Piotr Mienkowski
03eaafddfd logger: add a SWO backend
This commit adds Serial Wire Output (SWO) logger backend. SWO is an
extension of Serial Wire Debug (SWD) port developed by ARM.

Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
2019-01-09 15:30:59 +01:00
Erwan Gouriou
f5d48240e9 drivers/gpio: stm32l4: PortG[15:2] requires dedicated VDDio2
On STM32L4, 14 pins (Port G[15:2]), require external power supply.
Activate this at port G init when PWR_CR2_IOSV is defined.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-01-09 08:05:24 -06:00