board: iotdk: necessary clean up based on latest master branch
* clean up the DTS related definitions * code cleanup * do the tests/kernel sannity check Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
This commit is contained in:
Wayne Ren
Anas Nashif
parent
f0db0b8815
commit
163625cf78
6 changed files with 43 additions and 54 deletions
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@ -7,43 +7,43 @@
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/* SoC level DTS fixup file */
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/* CCM configuration */
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#define CONFIG_DCCM_BASE_ADDRESS ARC_DCCM_80000000_BASE_ADDRESS
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#define CONFIG_DCCM_SIZE (ARC_DCCM_80000000_SIZE >> 10)
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#define DT_DCCM_BASE_ADDRESS DT_ARC_DCCM_80000000_BASE_ADDRESS
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#define DT_DCCM_SIZE (DT_ARC_DCCM_80000000_SIZE >> 10)
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#define CONFIG_ICCM_BASE_ADDRESS ARC_ICCM_20000000_BASE_ADDRESS
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#define CONFIG_ICCM_SIZE (ARC_ICCM_20000000_SIZE >> 10)
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#define DT_ICCM_BASE_ADDRESS DT_ARC_ICCM_20000000_BASE_ADDRESS
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#define DT_ICCM_SIZE (DT_ARC_ICCM_20000000_SIZE >> 10)
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/*
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* UART configuration
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*/
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#define CONFIG_UART_NS16550_PORT_0_BASE_ADDR NS16550_80014000_BASE_ADDRESS
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#define CONFIG_UART_NS16550_PORT_0_IRQ NS16550_80014000_IRQ_0
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#define CONFIG_UART_NS16550_PORT_0_CLK_FREQ NS16550_80014000_CLOCK_FREQUENCY
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#define CONFIG_UART_NS16550_PORT_0_BAUD_RATE NS16550_80014000_CURRENT_SPEED
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#define CONFIG_UART_NS16550_PORT_0_NAME NS16550_80014000_LABEL
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#define CONFIG_UART_NS16550_PORT_0_IRQ_PRI NS16550_80014000_IRQ_0_PRIORITY
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#define DT_UART_NS16550_PORT_0_BASE_ADDR DT_NS16550_80014000_BASE_ADDRESS
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#define DT_UART_NS16550_PORT_0_IRQ DT_NS16550_80014000_IRQ_0
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#define DT_UART_NS16550_PORT_0_CLK_FREQ DT_NS16550_80014000_CLOCK_FREQUENCY
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#define CONFIG_UART_NS16550_PORT_0_BAUD_RATE DT_NS16550_80014000_CURRENT_SPEED
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#define CONFIG_UART_NS16550_PORT_0_NAME DT_NS16550_80014000_LABEL
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#define CONFIG_UART_NS16550_PORT_0_IRQ_PRI DT_NS16550_80014000_IRQ_0_PRIORITY
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#define CONFIG_UART_NS16550_PORT_1_BASE_ADDR NS16550_80014100_BASE_ADDRESS
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#define CONFIG_UART_NS16550_PORT_1_IRQ NS16550_80014100_IRQ_0
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#define CONFIG_UART_NS16550_PORT_1_CLK_FREQ NS16550_80014100_CLOCK_FREQUENCY
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#define CONFIG_UART_NS16550_PORT_1_BAUD_RATE NS16550_80014100_CURRENT_SPEED
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#define CONFIG_UART_NS16550_PORT_1_NAME NS16550_80014100_LABEL
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#define CONFIG_UART_NS16550_PORT_1_IRQ_PRI NS16550_80014100_IRQ_0_PRIORITY
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#define DT_UART_NS16550_PORT_1_BASE_ADDR DT_NS16550_80014100_BASE_ADDRESS
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#define DT_UART_NS16550_PORT_1_IRQ DT_NS16550_80014100_IRQ_0
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#define DT_UART_NS16550_PORT_1_CLK_FREQ DT_NS16550_80014100_CLOCK_FREQUENCY
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#define CONFIG_UART_NS16550_PORT_1_BAUD_RATE DT_NS16550_80014100_CURRENT_SPEED
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#define CONFIG_UART_NS16550_PORT_1_NAME DT_NS16550_80014100_LABEL
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#define CONFIG_UART_NS16550_PORT_1_IRQ_PRI DT_NS16550_80014100_IRQ_0_PRIORITY
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#define CONFIG_UART_NS16550_PORT_2_BASE_ADDR NS16550_80014200_BASE_ADDRESS
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#define CONFIG_UART_NS16550_PORT_2_IRQ NS16550_80014200_IRQ_0
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#define CONFIG_UART_NS16550_PORT_2_CLK_FREQ NS16550_80014200_CLOCK_FREQUENCY
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#define CONFIG_UART_NS16550_PORT_2_BAUD_RATE NS16550_80014200_CURRENT_SPEED
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#define CONFIG_UART_NS16550_PORT_2_NAME NS16550_80014200_LABEL
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#define CONFIG_UART_NS16550_PORT_2_IRQ_PRI NS16550_80014200_IRQ_0_PRIORITY
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#define DT_UART_NS16550_PORT_2_BASE_ADDR DT_NS16550_80014200_BASE_ADDRESS
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#define DT_UART_NS16550_PORT_2_IRQ DT_NS16550_80014200_IRQ_0
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#define DT_UART_NS16550_PORT_2_CLK_FREQ DT_NS16550_80014200_CLOCK_FREQUENCY
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#define CONFIG_UART_NS16550_PORT_2_BAUD_RATE DT_NS16550_80014200_CURRENT_SPEED
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#define CONFIG_UART_NS16550_PORT_2_NAME DT_NS16550_80014200_LABEL
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#define CONFIG_UART_NS16550_PORT_2_IRQ_PRI DT_NS16550_80014200_IRQ_0_PRIORITY
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#define CONFIG_UART_NS16550_PORT_3_BASE_ADDR NS16550_80014300_BASE_ADDRESS
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#define CONFIG_UART_NS16550_PORT_3_IRQ NS16550_80014300_IRQ_0
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#define CONFIG_UART_NS16550_PORT_3_CLK_FREQ NS16550_80014300_CLOCK_FREQUENCY
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#define CONFIG_UART_NS16550_PORT_3_BAUD_RATE NS16550_80014300_CURRENT_SPEED
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#define CONFIG_UART_NS16550_PORT_3_NAME NS16550_80014300_LABEL
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#define CONFIG_UART_NS16550_PORT_3_IRQ_PRI NS16550_80014300_IRQ_0_PRIORITY
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#define DT_UART_NS16550_PORT_3_BASE_ADDR DT_NS16550_80014300_BASE_ADDRESS
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#define DT_UART_NS16550_PORT_3_IRQ DT_NS16550_80014300_IRQ_0
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#define DT_UART_NS16550_PORT_3_CLK_FREQ DT_NS16550_80014300_CLOCK_FREQUENCY
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#define CONFIG_UART_NS16550_PORT_3_BAUD_RATE DT_NS16550_80014300_CURRENT_SPEED
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#define CONFIG_UART_NS16550_PORT_3_NAME DT_NS16550_80014300_LABEL
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#define CONFIG_UART_NS16550_PORT_3_IRQ_PRI DT_NS16550_80014300_IRQ_0_PRIORITY
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/* End of SoC Level DTS fixup file */
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@ -26,18 +26,18 @@
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/* Instruction Closely Coupled Memory (ICCM) base address and size */
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#if defined(CONFIG_ICCM_BASE_ADDRESS) && (CONFIG_ICCM_SIZE > 0)
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#define ICCM_START CONFIG_ICCM_BASE_ADDRESS
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#define ICCM_SIZE CONFIG_ICCM_SIZE
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#if defined(DT_ICCM_BASE_ADDRESS) && (DT_ICCM_SIZE > 0)
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#define ICCM_START DT_ICCM_BASE_ADDRESS
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#define ICCM_SIZE DT_ICCM_SIZE
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#endif
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/*
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* DCCM base address and size. DCCM is the data memory.
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*/
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/* Data Closely Coupled Memory (DCCM) base address and size */
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#if defined(CONFIG_DCCM_BASE_ADDRESS) && (CONFIG_DCCM_SIZE > 0)
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#define DCCM_START CONFIG_DCCM_BASE_ADDRESS
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#define DCCM_SIZE CONFIG_DCCM_SIZE
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#if defined(DT_DCCM_BASE_ADDRESS) && (DT_DCCM_SIZE > 0)
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#define DCCM_START DT_DCCM_BASE_ADDRESS
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#define DCCM_SIZE DT_DCCM_SIZE
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#endif
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#include <arch/arc/v2/linker.ld>
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@ -6,7 +6,7 @@
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*/
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/**
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* This module provides routines to initialize and support board-level hardware
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* This module provides routines to initialize and support soc-level hardware
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* for the IoT Development Kit board.
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*
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*/
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@ -19,7 +19,7 @@ static int arc_iot_init(struct device *dev)
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ARG_UNUSED(dev);
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if (arc_iot_pll_fout_config(
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC/1000000) < 0) {
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / 1000000) < 0) {
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return -1;
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}
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@ -20,7 +20,7 @@
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#define SYSCLK_DEFAULT_IOSC_HZ MHZ(16)
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/*
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* UART
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* UART: use lr and sr to access subsystem uart IP
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*/
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#define UART_NS16550_ACCESS_IOPORT
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@ -38,21 +38,12 @@
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#include <misc/util.h>
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#include <random/rand32.h>
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#define ARCV2_TIMER0_INT_LVL IRQ_TIMER0
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#define ARCV2_TIMER0_INT_PRI 0
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#define ARCV2_TIMER1_INT_LVL IRQ_TIMER1
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#define ARCV2_TIMER1_INT_PRI 1
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#define INT_ENABLE_ARC ~(0x00000001 << 8)
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#define INT_ENABLE_ARC_BIT_POS (8)
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/*
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* UARTs: UART0 & UART1 & UART2
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*/
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#define CONFIG_UART_NS16550_PORT_0_IRQ_FLAGS 0 /* Default */
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#define CONFIG_UART_NS16550_PORT_1_IRQ_FLAGS 0 /* Default */
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#define CONFIG_UART_NS16550_PORT_2_IRQ_FLAGS 0 /* Default */
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#define DT_UART_NS16550_PORT_0_IRQ_FLAGS 0 /* Default */
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#define DT_UART_NS16550_PORT_1_IRQ_FLAGS 0 /* Default */
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#define DT_UART_NS16550_PORT_2_IRQ_FLAGS 0 /* Default */
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#endif /* !_ASMLANGUAGE */
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@ -27,9 +27,9 @@ typedef struct pll_conf {
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/* the following configuration is based on Fin = 16 Mhz */
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static const pll_conf_t pll_configuration[] = {
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{100, PLL_CONF_VAL(1, 25, 2)}, /* 100 Mhz */
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{100, PLL_CONF_VAL(1, 25, 2)}, /* 100 Mhz */
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{50, PLL_CONF_VAL(1, 25, 3)}, /* 50 Mhz */
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{150, PLL_CONF_VAL(4, 75, 1)}, /* 150 Mhz */
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{150, PLL_CONF_VAL(4, 75, 1)}, /* 150 Mhz */
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{75, PLL_CONF_VAL(4, 75, 2)}, /* 75 Mhz */
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{25, PLL_CONF_VAL(2, 25, 3)}, /* 25 Mhz */
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{72, PLL_CONF_VAL(8, 144, 2)}, /* 72 Mhz */
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@ -151,7 +151,6 @@ void arc_iot_dio_clk_divisor(uint8_t div)
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sysconf_reg_ptr->SDIO_REFCLK_DIV;
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}
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void arc_iot_spi_master_clk_divisor(uint8_t id, uint8_t div)
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{
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if (id == SPI_MASTER_0) {
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@ -55,7 +55,7 @@ typedef struct sysconf_reg {
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/* CLKSEL_CONST is not described in spec. */
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#define CLKSEL_CONST (0x5A690000)
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#define CLKSEL_EXT_16M (0 | CLKSEL_CONST)
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#define CLKSEL_PLL (1 | CLKSEL_CONST)
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#define CLKSEL_PLL (1 | CLKSEL_CONST)
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#define CLKSEL_EXT_32K (2 | CLKSEL_CONST)
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#define PLLCON_BIT_OFFSET_N 0
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@ -140,7 +140,6 @@ typedef struct sysconf_reg {
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extern void arc_iot_pll_conf_reg(uint32_t val);
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extern int32_t arc_iot_pll_fout_config(uint32_t freq);
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extern void arc_iot_ahb_clk_divisor(uint8_t div);
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extern void arc_iot_ahb_clk_enable(uint8_t dev);
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extern void arc_iot_ahb_clk_disable(uint8_t dev);
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