This adds power management support for the STM32WL series.
Suspend-to-idle is mapped to the three stop states (wake up from any
EXTI, including LPTIM), and soft-off can trigger either standby or
shutdown (wake up in reset).
Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
The PS/2 module in npcx provides a hardware accelerator mechanism
including an 8-bit shift register, a state machine, and control logic
that handle both the incoming and outgoing data. The hardware
accelerator mechanism is shared by 4 PS/2 channels. To support it,
this CL separates the PS/2 driver into channel and controller drivers.
The controller driver is in charge of the PS/2 transaction. The channel
driver is in charge of the connection between the Zehpyr PS/2 API
interface and controller driver.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
This commit adds the asserts symbol in Kconfig to enable/disable
asserts functionality for stm32 series. These would be used in
stm32cube hal & ll drivers.
Signed-off-by: Krishna Mohan Dani <krishnamohan.d@hcl.com>
rv32m1_vega don't boot due to device init ordering and changes with the
device model. The soc code is looking for a device pointer for the
intmux. Change to using DEVICE_DT_GET here as that will ensure we get
a valid pointer and by the time we need to utilize the pointer the
intmux driver will have been initialized and thus the device pointer
will be ready.
Also set BUILD_OUTPUT_HEX since we utilize openocd to flash and west
flash is looking for a hex file for openocd targets.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This is a work in progress initial submission for the
Microchip MEC172x family SoC. This submission does
not contain all header files or power management.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
1. Added RT10xx and RT11xx configs
2. Added a new soc file for rt117x. There are clock differences
between the RT10xx and RT11xx series, hence the soc files
have been separated.
Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
Enable Instruction Cache
Warning: no flash driver yet available for STM32l5
But cache coherency management (cache invalidate)
will be rerquired when implementing flash driver.
ICAHE must be disabled for any flash write opeartion.
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Enable Instruction cache accelerator for Cortex M4
first 1MB of Flash.
As per Reference Manual: no need for cache coherency management
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Convert the various device_get_binding() calls used to get the device
clock node to use DEVICE_DT_GET. The latter is processed at link time,
so it should be a bit more efficient.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Add power management support to STM32L0 series.
The SoC have a single stop state that can be used with LPTIM as a system
timer, as well as a standby mode where the system resets on exit.
Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
NPCX WIMU CR_SIN is used to wake up soc from NPCX sleep power state.
The wake-up IRQ enabled when UART init. It causes the wake-up IRQ to
generate many extra interrupt events, which causes the system too busy
to handle other events. This PR moves the UART wake-up IRQ enabling
from UART init to npcx_power_enter_system_sleep() to avoid the
interrupt storm.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
Set the defalut value of SYS_CLOCK_HW_CYCLES_PER_SEC Kconfig option
from the Device Tree. The `clock-frequency` property of the DT cpu@0
node is a single source of truth defining the CPU frequency. This is
the value used e.g. by all Atmel drivers.
For Atmel SAM family CPU clock is currently the only supported system
clock source. Ensure that kernel understanding of the hardware clock
frequency is the correct one.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Add flash driver for it8xxx2. The driver can implement
flash read, write and erase that will be mapped to the
ram section for executing.
TEST="flash write 0x80000 0x10 0x20 0x30 0x40 ..."
"flash read 0x80000 0x100"
"flash erase 0x80000 0x1000"
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
MPS2 AN521 is a dual (Cortex-M33) core where the two cores
have different capabilities. E.g CPU0 implements TrustZone-M,
while CPU1 implements the FPU. Therefore we introcude separate
Kconfig symbols for the two SoC variants, and use these to
select the different Cortex-M capabilities. We also update
the definitions of __MPU/FPU/SAU/DSP variant in soc.h to make
them get the value from the Kconfig settings, directly.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Adding support for beagleV Starlight board based on Starfive JH7100
SoC. It's a base support, no drivers other than uart has been tested.
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com>
This CL introduces six properties, clock-frequency, core-prescaler,
apb1/2/3/4-prescaler in pcc (Power and Clock Controller) node to
configure clock settings. It also removed the original Kconfig options
used for the same purpose.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Rename OSC_CLK as OFMCLK to meet npcx datasheet. The Oscillator
Frequency Multiplier Clock (OFMCLK), which is derived from
High-Frequency Clock Generator (HFCG), is the source clock of cortex-m4
core and most of NPCX hardware modules.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
We should gurantee that we do not use SRAM during Zephyr early
boot, until SystemInit has returned. This commit aims to ensure
that SystemInit will be branched to, without first pushing args
to stack, even when no optimizations are selected. We chose to
define z_platform_init in assembly directly (instead of using
inline assembly) as it appears to be a cleaner design.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Use a common implementation for z_platform_init
in nRF SoC family. The implementations are
identical, so no need to maintain separate
identical versions of them. The commit does not
introduce behavioral changes.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
The was a missing comma in the DEVICE_DT_INST_DEFINE macro and the
SAME71 HAL tweaks the name of a struct so we have to work around that.
Fixes#36095
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This is a follow-up to commit 60d9988401.
Add a third option for the HFXO capacitance that keeps the default
value of the XOSC32MCAPS register untouched. The message in the above
commit incorrectly claimed that external load capacitors for HFXO
(the reset value of the XOSC32MCAPS register) was the configuration
in effect before. In fact, the register value was modified during
the device trimming in the SystemInit() function to use the internal
capacitors, and that is the configuration required for proper RADIO
operation on nRF5340 DK, for instance.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Align cavs25 with cavs15/18 and add memory segment for uncached mapping
of the SRAM to linker script. Assign sections to uncached and cached
segments as done in cavs15/18.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
The macros are used to get the pin(s) of a given driver instance. Add
_INST prefix to match convention used by the devicetree.h. The original
macros can now be used to obtain pin(s) of an arbitrary device instance
identified by the nodelabel.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Configures flexcomm2 to operate in USART mode and enables the associated
peripheral clock and pinmuxes. This instance is attached to the Arduino
serial header pins and can be used for Bluetooth serial HCI with a
frdm_kw41z or other BLE controller shield.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Configures flexcomm4 to operate in USART mode and enables the associated
peripheral clock and pinmuxes. This instance is attached to the Arduino
serial header pins and can be used for Bluetooth serial HCI with a
frdm_kw41z or other BLE controller shield.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Switch from using internal 6pf to internal 7pf load capacitor for LFXO.
Use a default clock accuracy of 50PPM as this matches lab results.
50PPM should be sufficient for common operating temperatures of
25degC +- 15.
Signed-off-by: Johan Stridkvist <johan.stridkvist@nordicsemi.no>
Always source the Zephyr base soc and shield (board root) Kconfigs
directly from Kconfig instead of generated Kconfig files.
This has the benefit that it is no longer necessary to generate Kconfig
files to source SoC root and shield (board root) when no custom roots
are provided.
Also this cleans up the doc/CMakeLists.txt and ensures that the
doc/CMakeLists.txt is not getting out of sync with the Kconfig.cmake.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
To support west OpenOCD path image flashing, this generates an npcx hex
image from the npcx BIN image. Moreover, this also changes the name of
npcx output image by CONFIG_KERNEL_BIN_NAME.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
Create the pinmux phandle to the ADC driver node in the
devicetree. When the pinmux_pin_set function in
adc_it8xxx2_channel_setup can refer to the setting of
this phandle. It is more flexible to use.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
NPCX7 variants allocate code RAM either at 0x10070000 or 0x10090000.
The MPU requires addresses and region sizes to be aligned, so the
generic cortex_m/arm_mpu_regions.c results in an ineffective setup with
the addresses above.
This adds a custom mpu_regions setup for the npcx7, which covers both
available sizes, resulting in these two possible setups:
- 192kB devices
Code ram: 0x10090000 to 0x100bffff
MPU region: 0x10080000 to 0x100bffff (256k)
- 320kB devices
Code ram: 0x10070000 to 0x100bffff
MPU region 0: 0x10040000 to 0x1007ffff (256k)
MPU region 1: 0x10080000 to 0x100bffff (256k)
In both cases MPU data RAM setting is from 0x200c0000 to 0x200cffff,
matching the generic Cortex-m setup.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Add Kconfig options that allow configuration of optional internal
load capacitors for the high-frequency (HFXO) and low-frequency
(LFXO) crystal oscillators in nRF5340.
Default settings used for the new options are those that have been
in effect so far, i.e. external load capacitors for HFXO and 6 pF
internal capacitance for LFXO.
This commit also adds missing SOC_ENABLE_LFXO option dependency on
!TRUSTED_EXECUTION_NONSECURE.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This CL adds the support for npcx9m3f and npcx9m6f chips in ecst.py
script which generates the NPCX firmware header.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL replaces macros for miwu multi-registers' offset with internal
inline functions. This CL also uses soc series definitions to
distinguish the layout of miwu multi-registers between different npcx
series.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL adds the soc drivers for npcx9 series. There are two soc part
numbers, npcx9m3f and npcx9m6f, are introduced. We also move soc family
configurations from /nuvoton_npcx/npcx7/Kconfig.soc to
nuvoton_npcx/Kconfig.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
