soc/arm: Provide basic support for STM32H7 series
Enable basic support to STM32H7, in single core configuration (M7). Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
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9 changed files with 182 additions and 0 deletions
5
soc/arm/st_stm32/stm32h7/CMakeLists.txt
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soc/arm/st_stm32/stm32h7/CMakeLists.txt
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# SPDX-License-Identifier: Apache-2.0
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zephyr_include_directories(${ZEPHYR_BASE}/drivers)
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zephyr_sources_ifdef(CONFIG_CPU_CORTEX_M7 soc_m7.c)
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soc/arm/st_stm32/stm32h7/Kconfig.defconfig.series
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soc/arm/st_stm32/stm32h7/Kconfig.defconfig.series
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# Kconfig.defconfig.series - ST Microelectronics STM32H7 MCU line
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#
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# Copyright (c) 2019 Linaro Limited
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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# Kconfig symbols common to STM32H7 series
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if SOC_SERIES_STM32H7X
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source "soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h7*"
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config SOC_SERIES
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default "stm32h7"
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if GPIO_STM32
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# GPIO ports A, B and C are set in ../common/Kconfig.defconfig.series
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# empty for now
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endif # GPIO_STM32
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endif # SOC_SERIES_STM32H7X
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soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h747xx
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soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h747xx
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# Kconfig - ST STM32H747X MCU configuration options
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#
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# Copyright (c) 2019 Linaro Limited
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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if SOC_STM32H747XX
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config SOC
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string
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default "stm32h747xx"
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config NUM_IRQS
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int
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default 150
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endif # SOC_STM32H747XX
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soc/arm/st_stm32/stm32h7/Kconfig.series
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soc/arm/st_stm32/stm32h7/Kconfig.series
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# Kconfig - ST Microelectronics STM32H7 MCU series
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#
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# Copyright (c) 2019 Linaro Limited
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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config SOC_SERIES_STM32H7X
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bool "STM32H7x Series MCU"
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select CPU_HAS_FPU
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select SOC_FAMILY_STM32
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select HAS_STM32CUBE
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select CPU_HAS_ARM_MPU
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select CLOCK_CONTROL_STM32_CUBE if CLOCK_CONTROL
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select NEWLIB_LIBC
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help
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Enable support for STM32H7 MCU series
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soc/arm/st_stm32/stm32h7/Kconfig.soc
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soc/arm/st_stm32/stm32h7/Kconfig.soc
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# Kconfig.soc - ST Microelectronics STM32H7 MCU line
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#
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# Copyright (c) 2019 Linaro Limited
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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choice
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prompt "STM32H7x MCU Selection"
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depends on SOC_SERIES_STM32H7X
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config SOC_STM32H747XX
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bool "STM32H747XX"
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select CPU_HAS_FPU_DOUBLE_PRECISION if CPU_CORTEX_M7
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endchoice
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soc/arm/st_stm32/stm32h7/dts_fixup.h
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soc/arm/st_stm32/stm32h7/dts_fixup.h
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/*
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* Copyright (c) 2019 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* SoC level DTS fixup file */
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#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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#define DT_NUM_MPU_REGIONS DT_ARM_ARMV7M_MPU_E000ED90_ARM_NUM_MPU_REGIONS
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/* End of SoC Level DTS fixup file */
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soc/arm/st_stm32/stm32h7/linker.ld
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soc/arm/st_stm32/stm32h7/linker.ld
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/* linker.ld - Linker command/script file */
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/*
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* Copyright (c) 2019 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arch/arm/cortex_m/scripts/linker.ld>
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soc/arm/st_stm32/stm32h7/soc.h
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soc/arm/st_stm32/stm32h7/soc.h
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/*
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* Copyright (c) 2019 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _STM32F7_SOC_H_
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#define _STM32F7_SOC_H_
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#ifndef _ASMLANGUAGE
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#include <stm32h7xx.h>
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/* ARM CMSIS definitions must be included before kernel_includes.h.
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* Therefore, it is essential to include kernel_includes.h after including
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* core SOC-specific headers.
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*/
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#include <kernel_includes.h>
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#endif /* !_ASMLANGUAGE */
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#endif /* _STM32F7_SOC_H7_ */
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soc/arm/st_stm32/stm32h7/soc_m7.c
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soc/arm/st_stm32/stm32h7/soc_m7.c
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/*
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* Copyright (c) 2019 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief System/hardware module for STM32H7 CM7 processor
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*/
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#include <kernel.h>
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#include <device.h>
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#include <init.h>
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#include <soc.h>
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#include <arch/cpu.h>
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#include <cortex_m/exc.h>
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/**
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* @brief Perform basic hardware initialization at boot.
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*
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* This needs to be run from the very beginning.
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* So the init priority has to be 0 (zero).
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*
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* @return 0
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*/
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static int stm32h7_init(struct device *arg)
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{
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u32_t key;
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ARG_UNUSED(arg);
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key = irq_lock();
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SCB_EnableICache();
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if (!(SCB->CCR & SCB_CCR_DC_Msk)) {
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SCB_EnableDCache();
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}
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/* Install default handler that simply resets the CPU
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* if configured in the kernel, NOP otherwise
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*/
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NMI_INIT();
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irq_unlock(key);
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/* Update CMSIS SystemCoreClock variable (HCLK) */
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/* At reset, system core clock is set to 64 MHz from HSI */
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SystemCoreClock = 64000000;
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return 0;
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}
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SYS_INIT(stm32h7_init, PRE_KERNEL_1, 0);
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