soc: stm32h7: Add support for Cortex-M4 core
Add support for C-M4 core on STM32H7 series. It is enabled in Dual core context with 2 alternatives boot methods: * Boot CM4 CM7: Both core boot at reset, then CM4 enters Stop mode. CM7 performs system configuration then finally wakes up CM4 * Boot CM7, CM4 Gated: Only CM7 boots at reset. Once done with system configuration it triggers (requires option byte update) Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
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@ -3,3 +3,4 @@
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zephyr_include_directories(${ZEPHYR_BASE}/drivers)
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zephyr_sources_ifdef(CONFIG_CPU_CORTEX_M7 soc_m7.c)
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zephyr_sources_ifdef(CONFIG_CPU_CORTEX_M4 soc_m4.c)
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@ -13,5 +13,33 @@ config SOC_SERIES_STM32H7X
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select CPU_HAS_ARM_MPU
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select CLOCK_CONTROL_STM32_CUBE if CLOCK_CONTROL
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select NEWLIB_LIBC
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select USE_STM32_HAL_RCC_EX if CPU_CORTEX_M4
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help
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Enable support for STM32H7 MCU series
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config STM32H7_DUAL_CORE
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bool "Enable Dual Core"
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depends on SOC_SERIES_STM32H7X
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choice STM32H7_DUAL_CORE_BOOT
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prompt "STM32H7x Boot type selection"
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depends on STM32H7_DUAL_CORE
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config STM32H7_BOOT_CM4_CM7
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bool "Boot both CM4 and CM7"
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help
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Cortex-M7 and Cortex-M4 running from the flash (each from a bank)
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System configuration performed by the Cortex-M7
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Cortex-M4 goes to STOP after boot, then woken-up by Cortex-M7 using
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a HW semaphore
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config STM32H7_BOOT_CM7_CM4GATED
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bool "Boot CM7. CM4 boot gated"
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help
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Cortex-M4 boot is gated using Flash option bytes
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Cortex-M7 and Cortex-M4 running from the flash (each from a bank)
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Cortex-M7 boots , performs the System configuration then enable the
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Cortex-M4 boot using RCC.
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This mode requires option byte setting update (BCM4 uncheked)
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endchoice
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@ -17,6 +17,23 @@
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*/
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#include <kernel_includes.h>
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#ifdef CONFIG_STM32H7_DUAL_CORE
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#define LL_HSEM_ID_0 (0U) /* HW semaphore 0 */
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#define LL_HSEM_MASK_0 (1 << LL_HSEM_ID_0)
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#include <stm32h7xx_ll_hsem.h>
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#ifdef CONFIG_CPU_CORTEX_M4
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#include <stm32h7xx_ll_bus.h>
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#include <stm32h7xx_ll_pwr.h>
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#include <stm32h7xx_ll_cortex.h>
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#endif /* CONFIG_CPU_CORTEX_M4 */
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#endif /* CONFIG_STM32H7_DUAL_CORE */
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#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE
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#include <stm32h7xx_ll_bus.h>
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#include <stm32h7xx_ll_rcc.h>
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92
soc/arm/st_stm32/stm32h7/soc_m4.c
Normal file
92
soc/arm/st_stm32/stm32h7/soc_m4.c
Normal file
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@ -0,0 +1,92 @@
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/*
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* Copyright (c) 2019 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief System/hardware module for STM32H7 CM4 processor
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*/
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#include <kernel.h>
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#include <device.h>
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#include <init.h>
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#include <soc.h>
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#include <arch/cpu.h>
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#include <cortex_m/exc.h>
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#if defined(CONFIG_STM32H7_BOOT_CM4_CM7)
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void stm32h7_m4_boot_stop(void)
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{
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/*
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* Domain D2 goes to STOP mode (Cortex-M4 in deep-sleep) waiting for
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* Cortex-M7 to perform system initialization (system clock config,
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* external memory configuration.. )
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*/
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/* Clear pending events if any */
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__SEV();
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__WFE();
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/* Select the domain Power Down DeepSleep */
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LL_PWR_SetRegulModeDS(LL_PWR_REGU_DSMODE_MAIN);
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/* Keep DSTOP mode when D2 domain enters Deepsleep */
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LL_PWR_CPU_SetD2PowerMode(LL_PWR_CPU_MODE_D2STOP);
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LL_PWR_CPU2_SetD2PowerMode(LL_PWR_CPU2_MODE_D2STOP);
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/* Set SLEEPDEEP bit of Cortex System Control Register */
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LL_LPM_EnableDeepSleep();
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/* Ensure that all instructions done before entering STOP mode */
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__DSB();
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__ISB();
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/* Request Wait For Event */
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__WFE();
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/* Reset SLEEPDEEP bit of Cortex System Control Register,
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* the following LL API Clear SLEEPDEEP bit of Cortex
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* System Control Register
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*/
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LL_LPM_EnableSleep();
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}
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#endif /* CONFIG_STM32H7_BOOT_CM4_CM7 */
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/**
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* @brief Perform basic hardware initialization at boot.
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*
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* This needs to be run from the very beginning.
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* So the init priority has to be 0 (zero).
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*
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* @return 0
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*/
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static int stm32h7_m4_init(struct device *arg)
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{
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u32_t key;
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key = irq_lock();
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/* Install default handler that simply resets the CPU
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* if configured in the kernel, NOP otherwise
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*/
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NMI_INIT();
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irq_unlock(key);
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/*HW semaphore Clock enable*/
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LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_HSEM);
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#if defined(CONFIG_STM32H7_BOOT_CM4_CM7)
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/* Activate HSEM notification for Cortex-M4*/
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LL_HSEM_EnableIT_C2IER(HSEM, LL_HSEM_MASK_0);
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/* Boot and enter stop mode */
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stm32h7_m4_boot_stop();
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/* Clear HSEM flag */
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LL_HSEM_ClearFlag_C2ICR(HSEM, LL_HSEM_MASK_0);
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#endif /* CONFIG_STM32H7_BOOT_CM4_CM7 */
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return 0;
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}
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SYS_INIT(stm32h7_m4_init, PRE_KERNEL_1, 0);
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@ -16,6 +16,41 @@
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#include <arch/cpu.h>
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#include <cortex_m/exc.h>
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#if defined(CONFIG_STM32H7_DUAL_CORE)
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static int stm32h7_m4_wakeup(struct device *arg)
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{
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/*HW semaphore Clock enable*/
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LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_HSEM);
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if (IS_ENABLED(CONFIG_STM32H7_BOOT_CM4_CM7)) {
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u32_t timeout;
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/*
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* When system initialization is finished, Cortex-M7 will
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* release Cortex-M4 by means of HSEM notification
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*/
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/*Take HSEM */
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LL_HSEM_1StepLock(HSEM, LL_HSEM_ID_0);
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/*Release HSEM in order to notify the CPU2(CM4)*/
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LL_HSEM_ReleaseLock(HSEM, LL_HSEM_ID_0, 0);
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/* wait until CPU2 wakes up from stop mode */
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timeout = 0xFFFF;
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while ((LL_RCC_D2CK_IsReady() == 0) && ((timeout--) > 0)) {
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}
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if (timeout < 0) {
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return -EIO;
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}
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} else if (IS_ENABLED(CONFIG_STM32H7_BOOT_CM7_CM4GATED)) {
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/* Start CM4 */
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LL_RCC_ForceCM4Boot();
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}
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return 0;
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}
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#endif /* CONFIG_STM32H7_DUAL_CORE */
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/**
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* @brief Perform basic hardware initialization at boot.
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@ -55,3 +90,8 @@ static int stm32h7_init(struct device *arg)
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SYS_INIT(stm32h7_init, PRE_KERNEL_1, 0);
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#if defined(CONFIG_STM32H7_DUAL_CORE)
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/* Unlock M4 once system configuration has been done */
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SYS_INIT(stm32h7_m4_wakeup, POST_KERNEL, CONFIG_APPLICATION_INIT_PRIORITY);
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#endif /* CONFIG_STM32H7_DUAL_CORE */
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