Add Microchip MEC172x header set 5 chip specific
peripheral headers. Update with recent merged code.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Consensus was reached to locate Microchip MEC172x header files
in the zephyr MEC172x SoC folders. These are the first set of
headers specific to MEC172x and common to the MEC family. Hardware
register structures will be located in peripheral specific headers.
Update based on latest merge of MEC172x related files.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Adding support for the stm32l051 devices.
Signed-off-by: Even Falch-Larsen <even.falch.larsen@nomono.co>
Co-authored-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Added minimal device tree and board files to build Microchip
MEC172x. SOC layer stripped down to allow build for checking
compilation only.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Pin PB5 is part of ARM Cortex-M debug interface and by default
configured to output TDO/TRACESWO signal. Disable TDO/TRACESWO
function on PB5 pin when LOG_BACKEND_SWO is not enabled. This
ultimately frees the pin to be used by standard SoC peripherals.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
This commit includes the following:
1. Add symbol for choice option. So we can override the default value
by an earlier definition.
2. NPCX9 doesn't support 33MHz SPI clock in the header. So disable the
option for NPCX9.
3. NPCX9 support 512K flash. Change default to 512k for NPCX9.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
To be able to get a tokenize DT string without the quotes. Deprecate
also DT_ENUM_TOKEN and DT_ENUM_UPPER_TOKEN.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Default Voltage scaling range selection (range2)
doesn't allow to configure Max frequency
switch to range1 to match any frequency
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Default Voltage scaling range selection (range2)
doesn't allow to configure Max frequency
switch to range1 to match any frequency
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Add power management support (runtime-idle and suspend-to-idle)
support for the NXP Kinetis KE1xf SoC series.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Enable the NXP Kinetis Low Power Timer (LPTMR) OS timer driver when
power management is enabled as the Arm SysTick timer cannot wake up the
KE1xF from deep sleep.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Keep the Slow Internal Reference Clock (SIRC) running in low-power
mode.
This allows peripherals that needs to remain operative in low-power
mode to use the SIRC as clock source.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Determine the default CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC from devicetree
when using the Arm SysTick hardware timer.
When the NXP KE1xF SoC series is using the Arm SysTick as hardware
timer, the cycles/second will always be equal to the CPU core clock
frequency.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Adds a devicetree chosen node to the mimxrt1170_evk_cm7 board to link
Segger RTT and SystemView sections in DTCM by default. Enables the AHB
clock while the CM7 is sleeping to allow debug access to the TCM.
Note that automatic RTT control block detection may not search the DTCM
address region, therefore you may need to manually set the RTT control
block address or search range in the Segger host tools (SystemView or
RTT Viewer). For example,
$ JLinkRTTViewer -ra 0x20000000
Tested with:
- samples/subsys/shell/shell_module/
- samples/subsys/tracing/
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
The SoC driver name is 'USB High-Speed Interface (USBHS)'. This rename
from usb_dc_sam to usb_dc_sam_usbhs allowing add others SoC drivers
like 'USB Device Port (UDP)' that is found at SAM4S/E variations.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This commit adds support for stm32wle4xx, stm32wle5xx single core socs,
as well as stm32wl54 dual core soc.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
The bootloader itself contains the i.MX RT6xx boot header, so we don't
need to duplicate it when building chainloaded applications.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Refactors the i.MX RT600 SoC series to be more consistent with the i.MX
RT10xx SoC series by choosing a child node (external flash device) of
the FlexSPI bus for zephyr,flash.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
With this patch, zephyr can enable SMP directly. Otherwise
zephyr needs TB-R to provide psci function.
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
Add strong definition z_arm64_el2_plat_init() and it is controlled
by CONFIG_SOC_FVP_AEMV8R_EL2_INIT.
VMPIDR_EL2 must be set manually on EL2. The purpose of VMPIDR_EL2 is
that holds the value of the Virtualization Multiprocessor ID and This
is the value returned by EL1 reads of MPIDR_EL1
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
This commit adds a new Kconfig option CLOCK_CONTROL_NPCX_EXTERNAL_SRC.
With this option enabled, the internal 32.768 KHz clock (LFCLK) is
generated by the on-chip Crystal Oscillator (XTOSC). Otherwise, the
LFCLK is generated by the Low-Frequency Clock Generator (LFCG).
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
NPCX power.c use LOG_MODULE_DECLARE(soc), but NPCX chip doesn't
register soc log module. This CL register soc log in soc.c to fix NPCX
build error for power management & log system.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
Save ra to caller saved register is wrong because it might get
overwritten after another function is called, so we fix this.
Remove clear mip register operation. (it8xxx2 supports machine-mode
only, and MEIP bit of mip is read-only).
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
For esp32c3 related ROM located functions instead
of esp32c3_rom.
Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
The _PrepC() function is the standard risc-v way
of zephyr entry point, so let it call the z_cstart instead
of calling this function directly.
Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
replaces the plain memcpy to zero the bss with
the standard zephyr function that does this task.
Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
Plus added implementation for esp32c3 SoC.
Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
by adding the soc specific files such: soc initialization code,
linker scripts and support for esp32c3 devkitm
Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
hal_espressif repository was updated from esp-idf v4.2
to esp-idf v4.3 to allow latest Espressif chips integration.
As a consequence, it added a few changes in drivers
and peripherals. To maintain bisectability, changes in this
PR cannot be split. Here are some details:
wifi: update linker script by adding libphy and new attributes.
spi: update some APIs and fixed missing wait_idle check
west.yml: esp32: update hal to new version
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Configures Segger RTT and SystemView data linker sections to DTCM by
default on i.MX RT SoCs if there is a zephyr,dtcm chosen node in
devicetree. This fixes a build warning in
samples/subsys/shell/shell_module for the mimxrt1170_evk_cm7 and
mimxrt1170_evk_cm4 platforms, which don't currently have a zephyr,dtcm
chosen node.
Note that there are runtime issues with Segger RTT and SystemView on
this board that need further debug, but submitting this patch now to
address nightly CI failures.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
This fixes missing PPP iterable and adds all
common-rom.ld iterables.
ESP32 and esptool does not support more then 16 segments, which
blocks including common iterables section as is.
This partially reverts commit ad0bf94f77
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
