drivers: flash: Add STM32G0XX flash support
Add flash support for STM32G0X SoC series. Signed-off-by: Philippe Retornaz <philippe@shapescale.com Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit is contained in:
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8 changed files with 267 additions and 6 deletions
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@ -26,6 +26,7 @@ if(CONFIG_CLOCK_CONTROL_STM32_CUBE)
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zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F7X flash_stm32f7x.c)
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zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32L4X flash_stm32l4x.c)
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zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32WBX flash_stm32wbx.c)
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zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32G0X flash_stm32g0x.c)
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endif()
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zephyr_include_directories_ifdef(
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@ -10,23 +10,24 @@ if SOC_FAMILY_STM32
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menuconfig SOC_FLASH_STM32
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bool "STM32 flash driver"
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depends on (SOC_SERIES_STM32F0X || SOC_SERIES_STM32F3X || SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X || SOC_SERIES_STM32L4X || SOC_SERIES_STM32WBX)
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depends on (SOC_SERIES_STM32F0X || SOC_SERIES_STM32F3X || SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X || SOC_SERIES_STM32L4X || SOC_SERIES_STM32WBX || SOC_SERIES_STM32G0X)
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select FLASH_HAS_DRIVER_ENABLED
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default y
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select FLASH_PAGE_LAYOUT if SOC_SERIES_STM32F0X
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select FLASH_PAGE_LAYOUT if SOC_SERIES_STM32F3X
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select FLASH_PAGE_LAYOUT if SOC_SERIES_STM32G0X
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select FLASH_PAGE_LAYOUT if SOC_SERIES_STM32F4X
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select FLASH_PAGE_LAYOUT if SOC_SERIES_STM32F7X
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select FLASH_PAGE_LAYOUT if SOC_SERIES_STM32L4X
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select FLASH_PAGE_LAYOUT if SOC_SERIES_STM32WBX
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select FLASH_HAS_PAGE_LAYOUT if SOC_SERIES_STM32F0X
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select FLASH_HAS_PAGE_LAYOUT if SOC_SERIES_STM32F3X
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select FLASH_HAS_PAGE_LAYOUT if SOC_SERIES_STM32G0X
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select FLASH_HAS_PAGE_LAYOUT if SOC_SERIES_STM32F4X
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select FLASH_HAS_PAGE_LAYOUT if SOC_SERIES_STM32F7X
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select FLASH_HAS_PAGE_LAYOUT if SOC_SERIES_STM32L4X
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select FLASH_HAS_PAGE_LAYOUT if SOC_SERIES_STM32WBX
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help
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Enable STM32F0x, STM32F3x, STM32F4x, STM32F7x, STM32L4x or
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STM32WBx series flash driver.
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Enable STM32F0x, STM32F3x, STM32F4x, STM32F7x, STM32L4x, STM32WBx or STM32G0x series flash driver.
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endif
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@ -33,6 +33,9 @@
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/* STM32WB: maximum erase time of 24.5ms for a 4K sector */
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#elif defined(CONFIG_SOC_SERIES_STM32WBX)
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#define STM32_FLASH_MAX_ERASE_TIME (K_MSEC(25))
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#elif defined(CONFIG_SOC_SERIES_STM32G0X)
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/* STM32G0: maximum erase time of 40ms for a 2K sector */
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#define STM32_FLASH_MAX_ERASE_TIME (K_MSEC(40))
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#endif
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/* Let's wait for double the max erase time to be sure that the operation is
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@ -123,7 +126,8 @@ int flash_stm32_wait_flash_idle(struct device *dev)
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static void flash_stm32_flush_caches(struct device *dev,
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off_t offset, size_t len)
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{
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#if defined(CONFIG_SOC_SERIES_STM32F0X) || defined(CONFIG_SOC_SERIES_STM32F3X)
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#if defined(CONFIG_SOC_SERIES_STM32F0X) || defined(CONFIG_SOC_SERIES_STM32F3X) || \
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defined(CONFIG_SOC_SERIES_STM32G0X)
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ARG_UNUSED(dev);
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ARG_UNUSED(offset);
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ARG_UNUSED(len);
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@ -226,6 +230,8 @@ static int flash_stm32_write_protection(struct device *dev, bool enable)
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struct stm32l4x_flash *regs = FLASH_STM32_REGS(dev);
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#elif defined(CONFIG_SOC_SERIES_STM32WBX)
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struct stm32wbx_flash *regs = FLASH_STM32_REGS(dev);
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#elif defined(CONFIG_SOC_SERIES_STM32G0X)
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struct stm32g0x_flash *regs = FLASH_STM32_REGS(dev);
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#endif
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int rc = 0;
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@ -269,6 +275,10 @@ static struct flash_stm32_priv flash_data = {
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.enr = LL_AHB1_GRP1_PERIPH_FLASH },
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#elif defined(CONFIG_SOC_SERIES_STM32WBX)
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.regs = (struct stm32wbx_flash *) DT_FLASH_DEV_BASE_ADDRESS,
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#elif defined(CONFIG_SOC_SERIES_STM32G0X)
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.regs = (struct stm32g0x_flash *) DT_FLASH_DEV_BASE_ADDRESS,
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.pclken = { .bus = STM32_CLOCK_BUS_AHB1,
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.enr = LL_AHB1_GRP1_PERIPH_FLASH },
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#endif
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};
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@ -294,7 +304,8 @@ static int stm32_flash_init(struct device *dev)
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struct flash_stm32_priv *p = FLASH_STM32_PRIV(dev);
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#if defined(CONFIG_SOC_SERIES_STM32L4X) || \
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defined(CONFIG_SOC_SERIES_STM32F0X) || \
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defined(CONFIG_SOC_SERIES_STM32F3X)
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defined(CONFIG_SOC_SERIES_STM32F3X) || \
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defined(CONFIG_SOC_SERIES_STM32G0X)
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struct device *clk = device_get_binding(STM32_CLOCK_CONTROL_NAME);
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/*
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@ -12,7 +12,8 @@
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#if defined(CONFIG_SOC_SERIES_STM32L4X) || \
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defined(CONFIG_SOC_SERIES_STM32F0X) || \
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defined(CONFIG_SOC_SERIES_STM32F3X)
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defined(CONFIG_SOC_SERIES_STM32F3X) || \
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defined(CONFIG_SOC_SERIES_STM32G0X)
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#include <drivers/clock_control.h>
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#include <clock_control/stm32_clock_control.h>
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#endif
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@ -36,6 +37,10 @@ struct flash_stm32_priv {
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struct stm32_pclken pclken;
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#elif defined(CONFIG_SOC_SERIES_STM32WBX)
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struct stm32wbx_flash *regs;
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#elif defined(CONFIG_SOC_SERIES_STM32G0X)
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struct stm32g0x_flash *regs;
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/* clock subsystem driving this peripheral */
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struct stm32_pclken pclken;
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#endif
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struct k_sem sem;
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};
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174
drivers/flash/flash_stm32g0x.c
Normal file
174
drivers/flash/flash_stm32g0x.c
Normal file
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@ -0,0 +1,174 @@
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/*
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* Copyright (c) 2019 Philippe Retornaz <philippe@shapescale.com>
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* Copyright (c) 2017 Linaro Limited
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* Copyright (c) 2017 BayLibre, SAS
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define LOG_DOMAIN flash_stm32g0
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#define LOG_LEVEL CONFIG_FLASH_LOG_LEVEL
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#include <logging/log.h>
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LOG_MODULE_REGISTER(LOG_DOMAIN);
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#include <kernel.h>
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#include <device.h>
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#include <string.h>
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#include <flash.h>
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#include <init.h>
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#include <soc.h>
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#include "flash_stm32.h"
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#define STM32G0X_PAGE_SHIFT 11
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/*
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* offset and len must be aligned on 8 for write,
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* positive and not beyond end of flash
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*/
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bool flash_stm32_valid_range(struct device *dev, off_t offset, u32_t len,
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bool write)
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{
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return (!write || (offset % 8 == 0 && len % 8 == 0)) &&
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flash_stm32_range_exists(dev, offset, len);
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}
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/*
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* STM32G0xx devices can have up to 64 2K pages
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*/
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static unsigned int get_page(off_t offset)
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{
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return offset >> STM32G0X_PAGE_SHIFT;
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}
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static int write_dword(struct device *dev, off_t offset, u64_t val)
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{
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volatile u32_t *flash = (u32_t *)(offset + CONFIG_FLASH_BASE_ADDRESS);
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struct stm32g0x_flash *regs = FLASH_STM32_REGS(dev);
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u32_t tmp;
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int rc;
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/* if the control register is locked, do not fail silently */
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if (regs->cr & FLASH_CR_LOCK) {
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return -EIO;
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}
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/* Check that no Flash main memory operation is ongoing */
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rc = flash_stm32_wait_flash_idle(dev);
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if (rc < 0) {
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return rc;
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}
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/* Check if this double word is erased */
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if (flash[0] != 0xFFFFFFFFUL ||
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flash[1] != 0xFFFFFFFFUL) {
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return -EIO;
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}
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/* Set the PG bit */
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regs->cr |= FLASH_CR_PG;
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/* Flush the register write */
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tmp = regs->cr;
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/* Perform the data write operation at the desired memory address */
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flash[0] = (u32_t)val;
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flash[1] = (u32_t)(val >> 32);
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/* Wait until the BSY bit is cleared */
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rc = flash_stm32_wait_flash_idle(dev);
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/* Clear the PG bit */
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regs->cr &= (~FLASH_CR_PG);
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return rc;
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}
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static int erase_page(struct device *dev, unsigned int page)
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{
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struct stm32g0x_flash *regs = FLASH_STM32_REGS(dev);
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u32_t tmp;
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int rc;
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/* if the control register is locked, do not fail silently */
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if (regs->cr & FLASH_CR_LOCK) {
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return -EIO;
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}
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/* Check that no Flash memory operation is ongoing */
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rc = flash_stm32_wait_flash_idle(dev);
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if (rc < 0) {
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return rc;
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}
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/* Set the PER bit and select the page you wish to erase */
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regs->cr |= FLASH_CR_PER;
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regs->cr &= ~FLASH_CR_PNB_Msk;
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regs->cr |= ((page % 256) << 3);
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/* Set the STRT bit */
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regs->cr |= FLASH_CR_STRT;
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/* flush the register write */
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tmp = regs->cr;
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/* Wait for the BSY bit */
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rc = flash_stm32_wait_flash_idle(dev);
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regs->cr &= ~FLASH_CR_PER;
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return rc;
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}
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int flash_stm32_block_erase_loop(struct device *dev, unsigned int offset,
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unsigned int len)
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{
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int i, rc = 0;
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i = get_page(offset);
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for (; i <= get_page(offset + len - 1) ; ++i) {
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rc = erase_page(dev, i);
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if (rc < 0) {
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break;
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}
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}
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return rc;
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}
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int flash_stm32_write_range(struct device *dev, unsigned int offset,
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const void *data, unsigned int len)
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{
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int i, rc = 0;
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for (i = 0; i < len; i += 8, offset += 8) {
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rc = write_dword(dev, offset, ((const u64_t *) data)[i>>3]);
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if (rc < 0) {
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return rc;
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}
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}
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return rc;
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}
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void flash_stm32_page_layout(struct device *dev,
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const struct flash_pages_layout **layout,
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size_t *layout_size)
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{
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static struct flash_pages_layout stm32g0_flash_layout = {
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.pages_count = 0,
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.pages_size = 0,
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};
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ARG_UNUSED(dev);
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if (stm32g0_flash_layout.pages_count == 0) {
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stm32g0_flash_layout.pages_count = FLASH_SIZE / FLASH_PAGE_SIZE;
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stm32g0_flash_layout.pages_size = FLASH_PAGE_SIZE;
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}
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*layout = &stm32g0_flash_layout;
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*layout_size = 1;
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}
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@ -0,0 +1,13 @@
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title: STM32 G0 Flash Controller
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version: 0.1
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description: >
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This binding gives a base representation of the STM32 G0 Flash Controller
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inherits:
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!include flash-controller.yaml
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properties:
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compatible:
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constraint: "st,stm32g0-flash-controller"
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@ -8,4 +8,7 @@
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#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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#define DT_FLASH_DEV_BASE_ADDRESS DT_ST_STM32G0_FLASH_CONTROLLER_40022000_BASE_ADDRESS
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#define DT_FLASH_DEV_NAME DT_ST_STM32G0_FLASH_CONTROLLER_40022000_LABEL
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/* End of SoC Level DTS fixup file */
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53
soc/arm/st_stm32/stm32g0/flash_registers.h
Normal file
53
soc/arm/st_stm32/stm32g0/flash_registers.h
Normal file
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@ -0,0 +1,53 @@
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/*
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* Copyright (c) 2019 Philippe Retornaz <philippe@shapescale.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _STM32G0X_FLASH_REGISTERS_H_
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#define _STM32G0X_FLASH_REGISTERS_H_
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#define FLASH_SR_BSY FLASH_SR_BSY1
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enum {
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STM32_FLASH_LATENCY_0 = 0x0,
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STM32_FLASH_LATENCY_1 = 0x1,
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STM32_FLASH_LATENCY_2 = 0x2,
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};
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/* 3.7.1 FLASH_ACR */
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union __ef_acr {
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u32_t val;
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struct {
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u32_t latency :3 __packed;
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u32_t rsvd__3_7 :5 __packed;
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u32_t prften :1 __packed;
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u32_t icen :1 __packed;
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u32_t rsvd__10 :1 __packed;
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u32_t icrst :1 __packed;
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u32_t rsvd__12_15 :4 __packed;
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u32_t empty :1 __packed;
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u32_t rsvd__17 :1 __packed;
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u32_t dbg_swend :1 __packed;
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u32_t rsvd__19_31 :13 __packed;
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} bit;
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};
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/* FLASH register map */
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struct stm32g0x_flash {
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volatile union __ef_acr acr;
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volatile u32_t rsvd__4;
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volatile u32_t keyr;
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volatile u32_t optkeyr;
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volatile u32_t sr;
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volatile u32_t cr;
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volatile u32_t eccr;
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volatile u32_t rsvd_0;
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volatile u32_t optr;
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volatile u32_t pcrop1sr;
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volatile u32_t pcrop1er;
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volatile u32_t wrp1ar;
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volatile u32_t wrp1br;
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};
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#endif /* _STM32G0X_FLASH_REGISTERS_H_ */
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