Musca B1: MHU: IPM MHU dual core on V2M Musca B1

Add support for ipm_mhu_dual_core sample on Musca B1.

Signed-off-by: Karl Zhang <karl.zhang@linaro.org>

samples/subsys/ipc/ipm_mhu_dual_core/README.rst

@@ -18,6 +18,9 @@ steps are:
 Building and Running
 ********************
 
+On Musca A1
+-----------
+
 This project outputs 'IPM MHU sample on musca_a' to the console.
 It can be built and executed on Musca A1 CPU 0 as follows:
 
@@ -36,6 +39,40 @@ It can be built and executed on Musca A1 CPU 1 as follows:
    :goals: run
    :compact:
 
+On Musca B1
+-----------
+
+This project outputs 'IPM MHU sample on musca_b1' to the console.
+It can be built and executed on Musca B1 CPU 0 as follows:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/subsys/ipc/ipm_mhu_dual_core
+   :board: v2m_musca_b1
+   :goals: run
+   :compact:
+
+This project outputs 'IPM MHU sample on v2m_musca_b1_nonsecure' to the console.
+It can be built and executed on Musca B1 CPU 1 as follows:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/subsys/ipc/ipm_mhu_dual_core
+   :board: v2m_musca_b1_nonsecure
+   :goals: run
+   :compact:
+
+Combine images for Musca
+========================
+
+A third-party tool (srecord) is used to generate the Intel formatted hex image.
+For more information refer to the `Srecord Manual`_.
+
+.. code-block:: bash
+
+   srec_cat zephyr.bin -Binary -offset $IMAGE_OFFSET zephyr_nonsecure.bin -Binary -offset $IMAGE_NS_OFFSET -o dual_core_zephyr.hex -Intel
+
+   # This command is an example for Musca B1
+   srec_cat zephyr.bin -Binary -offset 0xA000000 zephyr_nonsecure.bin -Binary -offset 0xA060400 -o dual_core_zephyr.hex -Intel
+
 Open a serial terminal (minicom, putty, etc.) and connect the board with the
 following settings:
 
@@ -61,3 +98,7 @@ Sample Output
    MHU ISR on CPU 0
    MHU ISR on CPU 1
    MHU Test Done.
+
+
+.. _Srecord Manual:
+   http://srecord.sourceforge.net/man/man1/srec_cat.html

samples/subsys/ipc/ipm_mhu_dual_core/sample.yaml

@@ -5,4 +5,4 @@ sample:
 tests:
   test:
     tags: ipm
-    platform_whitelist: v2m_musca v2m_musca_nonsecure
+    platform_whitelist: v2m_musca v2m_musca_nonsecure v2m_musca_b1 v2m_musca_b1_nonsecure

soc/arm/arm/musca_b1/soc.c

@@ -8,6 +8,45 @@
 #include <init.h>
 #include <soc.h>
 
+/* (Secure System Control) Base Address */
+#define SSE_200_SYSTEM_CTRL_S_BASE	(0x50021000UL)
+#define SSE_200_SYSTEM_CTRL_INITSVTOR1	(SSE_200_SYSTEM_CTRL_S_BASE + 0x114)
+#define SSE_200_SYSTEM_CTRL_CPU_WAIT	(SSE_200_SYSTEM_CTRL_S_BASE + 0x118)
+#define SSE_200_CPU_ID_UNIT_BASE	(0x5001F000UL)
+
+#define NON_SECURE_FLASH_ADDRESS	(0x60000)
+#define NON_SECURE_FLASH_OFFSET	(0x10000000)
+#define BL2_HEADER_SIZE		(0x400)
+
+/**
+ * @brief Wake up CPU 1 from another CPU, this is plaform specific.
+ *
+ */
+void wakeup_cpu1(void)
+{
+	/* Set the Initial Secure Reset Vector Register for CPU 1 */
+	*(u32_t *)(SSE_200_SYSTEM_CTRL_INITSVTOR1) =
+					CONFIG_FLASH_BASE_ADDRESS +
+					BL2_HEADER_SIZE +
+					NON_SECURE_FLASH_ADDRESS -
+					NON_SECURE_FLASH_OFFSET;
+
+	/* Set the CPU Boot wait control after reset */
+	*(u32_t *)(SSE_200_SYSTEM_CTRL_CPU_WAIT) = 0;
+}
+
+/**
+ * @brief Get the current CPU ID, this is plaform specific.
+ *
+ * @return Current CPU ID
+ */
+u32_t sse_200_platform_get_cpu_id(void)
+{
+	volatile u32_t *p_cpu_id = (volatile u32_t *)SSE_200_CPU_ID_UNIT_BASE;
+
+	return (u32_t)*p_cpu_id;
+}
+
 /**
  * @brief Perform basic hardware initialization at boot.
  *

soc/arm/arm/musca_b1/soc.h

@@ -13,4 +13,8 @@
 #include <sys/util.h>
 #endif
 
+extern void wakeup_cpu1(void);
+
+extern u32_t sse_200_platform_get_cpu_id(void);
+
 #endif /* _SOC_H_ */