boards: hsdk: add initial support of ARC HS Development Kit
This commit includes the initial support of ARC HS Development Kit: * hsdk soc support * hsdk board support * no mmu support, so no userspace * smp support Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
This commit is contained in:
Wayne Ren
Ioannis Glaropoulos
parent
4fb8bf61c0
commit
dbc29fe77e
18 changed files with 828 additions and 0 deletions
14
boards/arc/hsdk/Kconfig.board
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14
boards/arc/hsdk/Kconfig.board
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# Kconfig - DesignWare ARC HS Development Kit board configuration
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#
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# Copyright (c) 2019 Synopsys, Inc. All rights reserved.
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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config BOARD_HSDK
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bool "ARC HS Development Kit"
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depends on SOC_ARC_HSDK
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help
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The DesignWare ARC HS Development Kit is a ready-to-use platform for
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rapid software development on the ARC HS3x family of processors. It
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supports single- and multi-core ARC HS34, HS36 and HS38 processors
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and offers a wide range of interfaces
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11
boards/arc/hsdk/Kconfig.defconfig
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11
boards/arc/hsdk/Kconfig.defconfig
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#
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# Copyright (c) 2019 Synopsys, Inc. All rights reserved.
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#
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# SPDX-License-Identifier: Apache-2.0
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if BOARD_HSDK
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config BOARD
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default "hsdk"
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endif # BOARD_HSDK
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6
boards/arc/hsdk/board.cmake
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6
boards/arc/hsdk/board.cmake
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# SPDX-License-Identifier: Apache-2.0
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# TODO: can this board just use the usual openocd runner?
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set(BOARD_FLASH_RUNNER em-starterkit)
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set(BOARD_DEBUG_RUNNER em-starterkit)
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board_finalize_runner_args(em-starterkit)
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BIN
boards/arc/hsdk/doc/hsdk.jpg
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BIN
boards/arc/hsdk/doc/hsdk.jpg
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Binary file not shown.
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208
boards/arc/hsdk/doc/index.rst
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208
boards/arc/hsdk/doc/index.rst
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.. _hsdk:
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DesignWare(R) ARC(R) HS Development Kit
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########################################
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Overview
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********
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The DesignWare(R) ARC(R) HS Development Kit is a ready-to-use platform for
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rapid software development on the ARC HS3x family of processors. It supports
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single- and multi-core ARC HS34, HS36 and HS38 processors and offers a wide
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range of interfaces including Ethernet, WiFi, Bluetooth, USB, SDIO, I2C, SPI,
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UART, I2S, ADC, PWM and GPIO. A Vivante GPU is also contained in the ARC
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Development System SoC. This allows developers to build and debug complex
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software on a comprehensive hardware platform
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.. image:: ./hsdk.jpg
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:width: 442px
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:align: center
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:alt: DesignWare(R) ARC(R) HS Development Kit (synopsys.com)
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For details about the board, see: `ARC HS Development Kit
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(IoTDK) <https://www.synopsys.com/dw/ipdir.php?ds=arc-hs-development-kit>`__
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Hardware
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********
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For hardware feature details, refer to :
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`Designware HS Development Kit website`_.
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Programming and Debugging
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*************************
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Required Hardware and Software
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==============================
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To use Zephyr RTOS applications on the HS Development Kit board, a few
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additional pieces of hardware are required.
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* A micro USB cable provides USB-JTAG debug and USB-UART communication
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to the board
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* A universal switching power adaptor (110-240V
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AC to 12V DC), provided in the package, provides power to the board.
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* :ref:`The Zephyr SDK <zephyr_sdk>`
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* Terminal emulator software for use with the USB-UART. Suggestion:
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`Putty Website`_.
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* (optional) A collection of Pmods, Arduino modules, or Mikro modules.
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See `Digilent Pmod Modules`_ or develop your custom interfaces to attach
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to the Pmod connector.
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Set up the ARC HS Development Kit
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==================================
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To run Zephyr application on IoT Development Kit, you need to
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set up the board correctly.
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* Connect the digilent USB cable from your host to the board.
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* Connect the 12V DC power supply to your board
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Set up Zephyr Software
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======================
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Building Sample Applications
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==============================
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You can try many of the :ref:`sample applications and demos
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<samples-and-demos>`. We'll use :ref:`hello_world`, found in
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:zephyr_file:`samples/hello_world` as an example.
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Configuring
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-----------
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You may need to write a prj_arc.conf file if the sample doesn't have one.
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Next, you can use the menuconfig rule to configure the target. By specifying
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``hsdk`` as the board configuration, you can select the ARC HS Development
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Kit board support for Zephyr.
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.. zephyr-app-commands::
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:board: hsdk
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:zephyr-app: samples/hello_world
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:goals: menuconfig
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Building
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--------
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You can build an application in the usual way. Refer to
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:ref:`build_an_application` for more details. Here is an example for
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:ref:`hello_world`.
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.. zephyr-app-commands::
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:board: hsdk
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:zephyr-app: samples/hello_world
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:maybe-skip-config:
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:goals: build
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Connecting Serial Output
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=========================
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In the default configuration, Zephyr's HS Development Kit images support
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serial output via the USB-UART on the board. To enable serial output:
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* Open a serial port emulator (i.e. on Linux minicom, putty, screen, etc)
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* Specify the tty driver name, for example, on Linux this may be
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:file:`/dev/ttyUSB0`
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* Set the communication settings to:
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========= =====
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Parameter Value
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========= =====
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Baud: 115200
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Data: 8 bits
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Parity: None
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Stopbits: 1
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========= =====
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Debugging
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==========
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Using the latest version of Zephyr SDK(>=0.10), you can debug and
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flash (run) HS Development Kit directly.
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One option is to build and debug the application using the usual
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Zephyr build system commands.
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.. zephyr-app-commands::
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:board: hsdk
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:app: <my app>
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:goals: debug
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At this point you can do your normal debug session. Set breakpoints and then
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:kbd:`c` to continue into the program.
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The other option is to launch a debug server, as follows.
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.. zephyr-app-commands::
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:board: hsdk
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:app: <my app>
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:goals: debugserver
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Then connect to the debug server at the HS Development Kit from a second
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console, from the build directory containing the output :file:`zephyr.elf`.
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.. code-block:: console
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$ cd <my app>
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$ $ZEPHYR_SDK_INSTALL_DIR/arc-zephyr-elf/arc-zephyr-elf-gdb zephyr.elf
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(gdb) target remote localhost:3333
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(gdb) load
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(gdb) b main
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(gdb) c
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Flashing
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========
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If you just want to download the application to the HS Development Kit's DDR
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and run, you can do so in the usual way.
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.. zephyr-app-commands::
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:board: hsdk
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:app: <my app>
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:goals: flash
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This command still uses openocd and gdb to load the application elf file to
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HS Development Kit, but it will load the application and immediately run. If
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power is removed, the application will be lost since it wasn't written to flash.
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Most of the time you will not be flashing your program but will instead debug
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it using openocd and gdb. The program can be download via the USB cable into
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the code and data memories.
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The HS Development Kit also supports flashing the Zephyr application
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with the U-Boot bootloader, a powerful and flexible tool for loading
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an executable from different sources and running it on the target platform.
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The U-Boot implementation for the HS Development Kit was further extended with
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additional functionality that allows users to better manage the broad
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configurability of the HS Development Kit
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When you are ready to deploy the program so that it boots up automatically on
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reset or power-up, you can follow the steps to place the program on SD card.
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For details, see: `Uboot-HSDK-Command-Reference
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<https://github.com/foss-for-synopsys-dwc-arc-processors/linux/wiki/Uboot-HSDK-Command-Reference#launching-baremetal-application-on-hsdk>`__
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Release Notes
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*************
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References
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**********
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.. _embARC website: https://www.embarc.org
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.. _Designware HS Development Kit website: <https://www.synopsys.com/dw/ipdir.php?ds=arc_hs_development_kit>`_
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.. _Digilent Pmod Modules: http://store.digilentinc.com/pmod-modules
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.. _Putty website: http://www.putty.org
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29
boards/arc/hsdk/hsdk.dts
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29
boards/arc/hsdk/hsdk.dts
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/*
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* Copyright (c) 2019, Synopsys, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <arc_hsdk.dtsi>
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/ {
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model = "hsdk";
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compatible = "snps,hsdk";
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aliases {
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uart-0 = &uart0;
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};
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chosen {
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zephyr,sram = &ddr0;
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zephyr,console = &uart0;
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zephyr,shell-uart = &uart0;
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};
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};
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&uart0 {
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status = "okay";
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current-speed = <115200>;
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};
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11
boards/arc/hsdk/hsdk.yaml
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11
boards/arc/hsdk/hsdk.yaml
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identifier: hsdk
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name: HS Development Kit
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type: mcu
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arch: arc
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toolchain:
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- zephyr
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- xtools
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testing:
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ignore_tags:
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- net
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- bluetooth
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15
boards/arc/hsdk/hsdk_defconfig
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15
boards/arc/hsdk/hsdk_defconfig
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_ARC=y
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CONFIG_CPU_ARCHS=y
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CONFIG_SOC_ARC_HSDK=y
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CONFIG_BOARD_HSDK=y
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CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
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CONFIG_XIP=y
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CONFIG_BUILD_OUTPUT_BIN=n
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CONFIG_PRINTK=y
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CONFIG_ARCV2_INTERRUPT_UNIT=y
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CONFIG_ARCV2_TIMER=y
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CONFIG_CONSOLE=y
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CONFIG_UART_CONSOLE=y
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CONFIG_SERIAL=y
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111
boards/arc/hsdk/support/openocd.cfg
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111
boards/arc/hsdk/support/openocd.cfg
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# Copyright (C) 2019 Synopsys, Inc.
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# SPDX-License-Identifier: Apache-2.0
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#
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# Configure JTAG cable
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# SDP has built-in FT2232 chip, which is similar to Digilent HS-1, except that
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# it uses channgel B for JTAG, instead of channel A.
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interface ftdi
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ftdi_vid_pid 0x0403 0x6010
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ftdi_layout_init 0x0088 0x008b
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ftdi_channel 1
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adapter_khz 10000
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# ARCs supports only JTAG.
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transport select jtag
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#
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# HS Development Kit SoC.
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#
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# Contains quad-core ARC HS38.
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#
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source [find cpu/arc/hs.tcl]
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set _coreid 0
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set _dbgbase [expr 0x00000000 | ($_coreid << 13)]
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# CHIPNAME will be used to choose core family (600, 700 or EM). As far as
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# OpenOCD is concerned EM and HS are identical.
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set _CHIPNAME arc-em
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# OpenOCD discovers JTAG TAPs in reverse order.
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set _TARGETNAME4 $_CHIPNAME.cpu4
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jtag newtap $_CHIPNAME cpu4 -irlen 4 -ircapture 0x1 -expected-id 0x200c24b1
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set _TARGETNAME3 $_CHIPNAME.cpu3
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jtag newtap $_CHIPNAME cpu3 -irlen 4 -ircapture 0x1 -expected-id 0x200824b1
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set _TARGETNAME2 $_CHIPNAME.cpu2
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jtag newtap $_CHIPNAME cpu2 -irlen 4 -ircapture 0x1 -expected-id 0x200424b1
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set _TARGETNAME1 $_CHIPNAME.cpu1
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jtag newtap $_CHIPNAME cpu1 -irlen 4 -ircapture 0x1 -expected-id 0x200024b1
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################################
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# ARC HS38 core 1
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################################
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target create $_TARGETNAME1 arcv2 -chain-position $_TARGETNAME1
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$_TARGETNAME1 configure -coreid $_coreid
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$_TARGETNAME1 configure -dbgbase $_dbgbase
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$_TARGETNAME1 configure -event reset-assert "arc_common_reset $_TARGETNAME1"
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set _coreid [expr $_coreid + 1]
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set _dbgbase [expr 0x00000000 | ($_coreid << 13)]
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arc_hs_init_regs
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# Enable L2 cache support for core 1.
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$_TARGETNAME1 arc has-l2cache true
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################################
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# ARC HS38 core 2
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################################
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target create $_TARGETNAME2 arcv2 -chain-position $_TARGETNAME2
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$_TARGETNAME2 configure -coreid $_coreid
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$_TARGETNAME2 configure -dbgbase $_dbgbase
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$_TARGETNAME2 configure -event reset-assert "arc_common_reset $_TARGETNAME2"
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set _coreid [expr $_coreid + 1]
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set _dbgbase [expr 0x00000000 | ($_coreid << 13)]
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arc_hs_init_regs
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# Enable L2 cache support for core 2.
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$_TARGETNAME2 arc has-l2cache true
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################################
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# ARC HS38 core 3
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################################
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target create $_TARGETNAME3 arcv2 -chain-position $_TARGETNAME3
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$_TARGETNAME3 configure -coreid $_coreid
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$_TARGETNAME3 configure -dbgbase $_dbgbase
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$_TARGETNAME3 configure -event reset-assert "arc_common_reset $_TARGETNAME3"
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set _coreid [expr $_coreid + 1]
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set _dbgbase [expr 0x00000000 | ($_coreid << 13)]
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arc_hs_init_regs
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# Enable L2 cache support for core 3.
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$_TARGETNAME3 arc has-l2cache true
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################################
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# ARC HS38 core 4
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################################
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target create $_TARGETNAME4 arcv2 -chain-position $_TARGETNAME4
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$_TARGETNAME4 configure -coreid $_coreid
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$_TARGETNAME4 configure -dbgbase $_dbgbase
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# Flush L2$.
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$_TARGETNAME4 configure -event reset-assert "arc_hs_reset $_TARGETNAME4"
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set _coreid [expr $_coreid + 1]
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set _dbgbase [expr 0x00000000 | ($_coreid << 13)]
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arc_hs_init_regs
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# Enable L2 cache support for core 4.
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$_TARGETNAME4 arc has-l2cache true
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# vi:ft=tcl
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189
dts/arc/arc_hsdk.dtsi
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189
dts/arc/arc_hsdk.dtsi
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/*
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* Copyright (c) 2019, Synopsys, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "skeleton.dtsi"
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#include <dt-bindings/i2c/i2c.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "snps,archs38";
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reg = <0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "snps,archs38";
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reg = <1>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "snps,archs38";
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reg = <2>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "snps,archs38";
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reg = <3>;
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};
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};
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intc: arcv2-intc {
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compatible = "snps,arcv2-intc";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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idu_intc: idu-interrupt-controller {
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compatible = "snps,archs-idu-intc";
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&idu_intc>;
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ranges;
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ddr0: memory@0 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0x0 0x80000000>;
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};
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|
||||
uart0: uart@f0005000 {
|
||||
compatible = "ns16550";
|
||||
clock-frequency = <33333333>;
|
||||
reg = <0xf0005000 0x1000>;
|
||||
label = "UART_0";
|
||||
interrupts = <30 1>;
|
||||
};
|
||||
|
||||
uart1: uart@f0026000{
|
||||
compatible = "ns16550";
|
||||
clock-frequency = <33333333>;
|
||||
reg = <0xf0026000 0x1000>;
|
||||
label = "UART_1";
|
||||
interrupts = <46 1>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: uart@f0027000 {
|
||||
compatible = "ns16550";
|
||||
clock-frequency = <33333333>;
|
||||
reg = <0xf0027000 0x1000>;
|
||||
label = "UART_2";
|
||||
interrupts = <47 1>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: uart@f0028000 {
|
||||
compatible = "ns16550";
|
||||
clock-frequency = <33333333>;
|
||||
reg = <0xf0028000 0x1000>;
|
||||
label = "UART_3";
|
||||
interrupts = <48 1>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio0: gpio@f0003000 {
|
||||
compatible = "snps,designware-gpio";
|
||||
reg = <0xf0003000 0x1000>;
|
||||
bits = <32>;
|
||||
label = "GPIO_0";
|
||||
interrupt-parent = <&idu_intc>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@f0023000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
clock-frequency = <I2C_BITRATE_STANDARD>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xf0023000 0x1000>;
|
||||
interrupts = <43 1>;
|
||||
label = "I2C_0";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@f0024000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
clock-frequency = <I2C_BITRATE_STANDARD>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xf0024000 0x1000>;
|
||||
interrupts = <44 1>;
|
||||
label = "I2C_1";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@f0025000 {
|
||||
compatible = "snps,designware-i2c";
|
||||
clock-frequency = <I2C_BITRATE_STANDARD>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xf0025000 0x1000>;
|
||||
interrupts = <45 1>;
|
||||
label = "I2C_2";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi0: spi@f0020000 {
|
||||
compatible = "snps,designware-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xf0020000 0x1000>;
|
||||
interrupts = <40 1>;
|
||||
label = "SPI_0";
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi1: spi@f0021000 {
|
||||
compatible = "snps,designware-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xf0021000 0x1000>;
|
||||
interrupts = <41 1>;
|
||||
label = "SPI_1";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi2: spi@f0022000 {
|
||||
compatible = "snps,designware-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xf0022000 0x1000>;
|
||||
interrupts = <42 1>;
|
||||
label = "SPI_1";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
23
dts/bindings/interrupt-controller/snps,archs-idu-intc.yaml
Normal file
23
dts/bindings/interrupt-controller/snps,archs-idu-intc.yaml
Normal file
|
|
@ -0,0 +1,23 @@
|
|||
#
|
||||
# Copyright (c) 2019, synopsys
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
|
||||
title: ARC-HS Interrupt Distribution Unit
|
||||
|
||||
description: >
|
||||
This binding describes the 2nd level interrupt controller can be used in
|
||||
SMP configurations for dynamic IRQ routing, load balancing of
|
||||
common/external IRQs towards core intc
|
||||
|
||||
inherits:
|
||||
!include [interrupt-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
constraint: "snps,archs-idu-intc"
|
||||
|
||||
"#cells":
|
||||
- irq
|
||||
- priority
|
||||
13
soc/arc/snps_arc_hsdk/CMakeLists.txt
Normal file
13
soc/arc/snps_arc_hsdk/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
zephyr_library_include_directories(${ZEPHYR_BASE}/drivers)
|
||||
|
||||
# -mcpu=hs38_linux includes -matomic -mcode-density -mdiv-rem
|
||||
# -mswap -mnorm -mll64 -mmpy-option=9 -mfpu=fpud_all
|
||||
zephyr_cc_option(-mcpu=${GCC_M_CPU})
|
||||
zephyr_cc_option(-mno-sdata)
|
||||
zephyr_cc_option_ifdef(CONFIG_FLOAT -mfpu=fpud_all)
|
||||
|
||||
zephyr_sources(
|
||||
soc.c
|
||||
)
|
||||
63
soc/arc/snps_arc_hsdk/Kconfig.defconfig
Normal file
63
soc/arc/snps_arc_hsdk/Kconfig.defconfig
Normal file
|
|
@ -0,0 +1,63 @@
|
|||
#
|
||||
# Copyright (c) 2019 Synopsys, Inc. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
|
||||
if SOC_ARC_HSDK
|
||||
|
||||
config SOC
|
||||
string
|
||||
default "snps_arc_hsdk"
|
||||
|
||||
config CPU_HS38_LINUX
|
||||
def_bool y
|
||||
|
||||
config NUM_IRQ_PRIO_LEVELS
|
||||
# This processor supports 2 priority levels:
|
||||
# 0 for Fast Interrupts (FIRQs) and 1 for Regular Interrupts (IRQs).
|
||||
default 2
|
||||
|
||||
config NUM_IRQS
|
||||
# must be > the highest interrupt number used
|
||||
default 88
|
||||
|
||||
config RGF_NUM_BANKS
|
||||
default 2
|
||||
|
||||
config SYS_CLOCK_HW_CYCLES_PER_SEC
|
||||
default 500000000
|
||||
|
||||
config ARC_FIRQ
|
||||
default y
|
||||
|
||||
config CODE_DENSITY
|
||||
default y
|
||||
|
||||
config ARCV2_TIMER_IRQ_PRIORITY
|
||||
default 1
|
||||
|
||||
config ARC_CONNECT
|
||||
default y
|
||||
|
||||
config MP_NUM_CPUS
|
||||
default 4
|
||||
|
||||
if SERIAL
|
||||
|
||||
config UART_NS16550
|
||||
default y
|
||||
|
||||
endif # SERIAL
|
||||
|
||||
if UART_CONSOLE
|
||||
|
||||
config UART_NS16550_PORT_0
|
||||
default y
|
||||
|
||||
config UART_NS16550_ACCESS_WORD_ONLY
|
||||
default y
|
||||
|
||||
endif # UART_CONSOLE
|
||||
|
||||
endif # ARC_HSDK
|
||||
9
soc/arc/snps_arc_hsdk/Kconfig.soc
Normal file
9
soc/arc/snps_arc_hsdk/Kconfig.soc
Normal file
|
|
@ -0,0 +1,9 @@
|
|||
#
|
||||
# Copyright (c) 2019 Synopsys, Inc. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
|
||||
config SOC_ARC_HSDK
|
||||
bool "Synopsys ARC HSDK SoC"
|
||||
select CPU_HAS_FPU
|
||||
19
soc/arc/snps_arc_hsdk/dts_fixup.h
Normal file
19
soc/arc/snps_arc_hsdk/dts_fixup.h
Normal file
|
|
@ -0,0 +1,19 @@
|
|||
/*
|
||||
* Copyright (c) 2019 Synopsys, Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/* SoC level DTS fixup file */
|
||||
|
||||
/*
|
||||
* UART configuration
|
||||
*/
|
||||
#define DT_UART_NS16550_PORT_0_BASE_ADDR DT_NS16550_F0005000_BASE_ADDRESS
|
||||
#define DT_UART_NS16550_PORT_0_IRQ DT_NS16550_F0005000_IRQ_0
|
||||
#define DT_UART_NS16550_PORT_0_CLK_FREQ DT_NS16550_F0005000_CLOCK_FREQUENCY
|
||||
#define DT_UART_NS16550_PORT_0_BAUD_RATE DT_NS16550_F0005000_CURRENT_SPEED
|
||||
#define DT_UART_NS16550_PORT_0_NAME DT_NS16550_F0005000_LABEL
|
||||
#define DT_UART_NS16550_PORT_0_IRQ_PRI DT_NS16550_F0005000_IRQ_0_PRIORITY
|
||||
|
||||
/* End of SoC Level DTS fixup file */
|
||||
23
soc/arc/snps_arc_hsdk/linker.ld
Normal file
23
soc/arc/snps_arc_hsdk/linker.ld
Normal file
|
|
@ -0,0 +1,23 @@
|
|||
/*
|
||||
* Copyright (c) 2019 Synopsys, Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Linker script for the HS Development Kit
|
||||
*/
|
||||
|
||||
#include <generated_dts_board.h>
|
||||
#include <autoconf.h>
|
||||
|
||||
/*
|
||||
* SRAM base address and size
|
||||
*/
|
||||
#if defined(CONFIG_SRAM_BASE_ADDRESS) && (CONFIG_SRAM_SIZE > 0)
|
||||
#define SRAM_START CONFIG_SRAM_BASE_ADDRESS
|
||||
#define SRAM_SIZE CONFIG_SRAM_SIZE
|
||||
#endif
|
||||
|
||||
|
||||
#include <arch/arc/v2/linker.ld>
|
||||
41
soc/arc/snps_arc_hsdk/soc.c
Normal file
41
soc/arc/snps_arc_hsdk/soc.c
Normal file
|
|
@ -0,0 +1,41 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2019 Synopsys, Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* This module provides routines to initialize and support soc-level hardware
|
||||
* for the HS Development Kit
|
||||
*/
|
||||
#include <device.h>
|
||||
#include <init.h>
|
||||
#include "soc.h"
|
||||
|
||||
static int arc_hsdk_init(struct device *dev)
|
||||
{
|
||||
ARG_UNUSED(dev);
|
||||
|
||||
u32_t core;
|
||||
u32_t i;
|
||||
|
||||
/* allocate all IDU interrupts to master core */
|
||||
core = z_arc_v2_core_id();
|
||||
|
||||
z_arc_connect_idu_disable();
|
||||
|
||||
for (i = 0; i < (CONFIG_NUM_IRQS - ARC_CONNECT_IDU_IRQ_START); i++) {
|
||||
z_arc_connect_idu_set_mode(i, ARC_CONNECT_INTRPT_TRIGGER_LEVEL,
|
||||
ARC_CONNECT_DISTRI_MODE_ROUND_ROBIN);
|
||||
z_arc_connect_idu_set_dest(i, 1 << core);
|
||||
z_arc_connect_idu_set_mask(i, 0x0);
|
||||
}
|
||||
|
||||
z_arc_connect_idu_enable();
|
||||
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
SYS_INIT(arc_hsdk_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
|
||||
43
soc/arc/snps_arc_hsdk/soc.h
Normal file
43
soc/arc/snps_arc_hsdk/soc.h
Normal file
|
|
@ -0,0 +1,43 @@
|
|||
/*
|
||||
* Copyright (c) 2019 Synopsys, Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Board configuration macros for HS Development Kit
|
||||
*
|
||||
* This header file is used to specify and describe board-level
|
||||
* aspects for the target.
|
||||
*/
|
||||
|
||||
#ifndef _SOC_H_
|
||||
#define _SOC_H_
|
||||
|
||||
#include <misc/util.h>
|
||||
|
||||
|
||||
/* ARC HS Core IRQs */
|
||||
#define IRQ_TIMER0 16
|
||||
#define IRQ_TIMER1 17
|
||||
#define IRQ_ICI 19
|
||||
|
||||
#define BASE_ADDR_SYSCONFIG 0xF000A000
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
|
||||
|
||||
#include <misc/util.h>
|
||||
#include <random/rand32.h>
|
||||
|
||||
/*
|
||||
* UARTs: UART0 & UART1 & UART2
|
||||
*/
|
||||
#define DT_UART_NS16550_PORT_0_IRQ_FLAGS 0 /* Default */
|
||||
#define DT_UART_NS16550_PORT_1_IRQ_FLAGS 0 /* Default */
|
||||
#define DT_UART_NS16550_PORT_2_IRQ_FLAGS 0 /* Default */
|
||||
|
||||
|
||||
#endif /* !_ASMLANGUAGE */
|
||||
|
||||
#endif /* _SOC_H_ */
|
||||
Loading…
Add table
Add a link
Reference in a new issue