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boards: remove galileo board

Browse source 
This board and SoC was discontinued some time ago and is currently not
maintained in the zephyr tree.
Remove all associated configurations and variants from the tree.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Anas Nashif 2019-07-06 09:09:47 -04:00 • committed by Andrew Boie
commit a597c86c30
25 changed files with 0 additions and 2191 deletions
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1
CODEOWNERS
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@ -49,7 +49,6 @@
/arch/x86/core/multiboot.c @gnuless
/soc/x86/ @andrewboie @gnuless
/soc/x86/intel_quark/quark_se/ @nashif
/soc/x86/intel_quark/quark_x1000/ @nashif
/arch/xtensa/ @andrewboie @dcpleung @andyross
/soc/xtensa/ @andrewboie @dcpleung @andyross
/boards/arc/ @vonhust @ruuddw

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boards/x86/galileo/CMakeLists.txt
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# SPDX-License-Identifier: Apache-2.0
if(CONFIG_PINMUX)
zephyr_library()
zephyr_library_sources(pinmux.c)
zephyr_library_include_directories(${ZEPHYR_BASE}/drivers)
endif()

57
boards/x86/galileo/Kconfig
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# Kconfig - Galileo Pinmux configuration options
#
# Copyright (c) 2016 Intel Corporation
#
# SPDX-License-Identifier: Apache-2.0
#
if PINMUX && BOARD_GALILEO
comment "Galileo Pinmux Options"
config PINMUX_GALILEO_EXP0_NAME
string "Name of the GPIO expander 0"
default "EXP0"
help
The name of the GPIO expander labeled as EXP0 in the schematic.
config PINMUX_GALILEO_EXP1_NAME
string "Name of the GPIO expander 1"
default "EXP1"
help
The name of the GPIO expander labeled as EXP1 in the schematic.
config PINMUX_GALILEO_EXP2_NAME
string "Name of the GPIO expander 2"
default "EXP2"
help
The name of the GPIO expander labeled as EXP2 in the schematic.
config PINMUX_GALILEO_PWM0_NAME
string "Name of the PWM LED expander 0"
default "PWM0"
help
The name of the PWM LED expander labeled as PWM0 in the schematic.
config PINMUX_GALILEO_GPIO_DW_NAME
string "Name of the DesignWare GPIO"
default "GPIO_0"
help
The name of the DesignWare GPIO with GPIO<0>..GPIO<7> in the schematic.
config PINMUX_GALILEO_GPIO_INTEL_CW_NAME
string "Name of the Legacy Bridge Core Well GPIO"
default "GPIO_M0"
help
The name of the Legacy Bridge Core Well GPIO with GPIO<8>..GPIO<9>
in the schematic.
config PINMUX_GALILEO_GPIO_INTEL_RW_NAME
string "Name of the Legacy Bridge Resume Well GPIO"
default "GPIO_M1"
help
The name of the Legacy Bridge Resume Well GPIO with
GPIO_SUS<0>..GPIO_SUS<5> in the schematic.
endif

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boards/x86/galileo/Kconfig.board
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# SPDX-License-Identifier: Apache-2.0
config BOARD_GALILEO
bool "Galileo Gen2"
depends on SOC_SERIES_QUARK_X1000
help
The Intel Galileo Gen 2 development board is a microcontroller board
based on the Intel Quark SoC X1000 application processor, a 32-bit
Intel(r) Pentium(r) brand system on a chip (SoC). It is the first board
based on Intel architecture designed to be hardware and software
pin-compatible with shields designed for the Arduino Uno* R3.

111
boards/x86/galileo/Kconfig.defconfig
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# SPDX-License-Identifier: Apache-2.0
if BOARD_GALILEO
config BUILD_OUTPUT_STRIPPED
default y
config BOARD
default "galileo"
config I2C
default y
config GPIO
default y
config PWM
default y
config SPI
default y
config SHARED_IRQ
default y
if GPIO && I2C
config GPIO_PCAL9535A
default y
if GPIO_PCAL9535A
config GPIO_PCAL9535A_0
default y
if GPIO_PCAL9535A_0
config GPIO_PCAL9535A_0_DEV_NAME
default "EXP0"
config GPIO_PCAL9535A_0_I2C_ADDR
default 0x25
config GPIO_PCAL9535A_0_I2C_MASTER_DEV_NAME
default "$(dt_str_val,DT_INST_0_SNPS_DESIGNWARE_I2C_LABEL)"
endif # GPIO_PCAL9535A_0
config GPIO_PCAL9535A_1
default y
if GPIO_PCAL9535A_1
config GPIO_PCAL9535A_1_DEV_NAME
default "EXP1"
config GPIO_PCAL9535A_1_I2C_ADDR
default 0x26
config GPIO_PCAL9535A_1_I2C_MASTER_DEV_NAME
default "$(dt_str_val,DT_INST_0_SNPS_DESIGNWARE_I2C_LABEL)"
endif # GPIO_PCAL9535A_1
config GPIO_PCAL9535A_2
default y
if GPIO_PCAL9535A_2
config GPIO_PCAL9535A_2_DEV_NAME
default "EXP2"
config GPIO_PCAL9535A_2_I2C_ADDR
default 0x27
config GPIO_PCAL9535A_2_I2C_MASTER_DEV_NAME
default "$(dt_str_val,DT_INST_0_SNPS_DESIGNWARE_I2C_LABEL)"
endif # GPIO_PCAL9535A_2
endif # GPIO_PCAL9535A
endif # GPIO && I2C
if PWM && I2C
config PWM_PCA9685
default y
if PWM_PCA9685
config PWM_PCA9685_0
default y
if PWM_PCA9685_0
config PWM_PCA9685_0_DEV_NAME
default "PWM0"
config PWM_PCA9685_0_I2C_ADDR
default 0x47
config PWM_PCA9685_0_I2C_MASTER_DEV_NAME
default "$(dt_str_val,DT_INST_0_SNPS_DESIGNWARE_I2C_LABEL)"
endif # PWM_PCA9685_0
endif # PWM_PCA9685
endif # PWM && I2C
# SPI uses GPIO pin for CS, so it needs to be initialized after
# the gpio_dw driver ( and the pinmux driver for port 1)
config SPI_INIT_PRIORITY
default 90 if SPI_INTEL
# Pin multiplexer uses PCAL9535A, needs to be initialized after it
config PINMUX_INIT_PRIORITY
default 80 if PINMUX
endif # BOARD_GALILEO

46
boards/x86/galileo/board.h
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/*
* Copyright (c) 2015 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __INC_BOARD_H
#define __INC_BOARD_H
/*
* PINMUX configuration settings
*/
#define PINMUX_NUM_PINS 20
/*
* The name of the GPIO expander labelled as EXP0 in the schematic.
*/
#define PINMUX_GALILEO_EXP0_NAME CONFIG_GPIO_PCAL9535A_0_DEV_NAME
/*
* The name of the GPIO expander labelled as EXP1 in the schematic.
*/
#define PINMUX_GALILEO_EXP1_NAME CONFIG_GPIO_PCAL9535A_1_DEV_NAME
/*
* The name of the GPIO expander labelled as EXP2 in the schematic.
*/
#define PINMUX_GALILEO_EXP2_NAME CONFIG_GPIO_PCAL9535A_2_DEV_NAME
/*
* The name of the PWM LED expander labelled as PWM0 in the schematic.
*/
#define PINMUX_GALILEO_PWM0_NAME CONFIG_PWM_PCA9685_0_DEV_NAME
/*
* The name of the DesignWare GPIO with GPIO<0>..GPIO<7> in the schematic.
*/
#define PINMUX_GALILEO_GPIO_DW_NAME CONFIG_GPIO_DW_0_NAME
/*
* The name of the Legacy Bridge Core Well GPIO with GPIO<8>..GPIO<9>
* in the schematic.
*/
#define PINMUX_GALILEO_GPIO_INTEL_CW_NAME CONFIG_GPIO_SCH_0_DEV_NAME
/*
* The name of the Legacy Bridge Resume Well GPIO with
* GPIO_SUS<0>..GPIO_SUS<5> in the schematic.
*/
#define PINMUX_GALILEO_GPIO_INTEL_RW_NAME CONFIG_GPIO_SCH_1_DEV_NAME
#endif /* __INC_BOARD_H */

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boards/x86/galileo/doc/index.rst
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.. _galileo:
Galileo Gen1/Gen2
#################
Overview
********
Intel Galileo is the first in a line of Arduino-certified development boards
based on Intel x86 architecture and is designed for the maker and education
communities. It features the Intel Quark SoC X1000, the first product from the
Intel Quark technology family of low-power, small-core products.
.. figure:: galileo.jpg
:width: 600px
:align: center
:alt: Galileo
Galileo (Credit: Intel)
This board configuration enables kernel support for the board's Intel |reg| Quark |trade| SoC,
along with the following devices:
* High Precision Event Timer (HPET)
* Peripheral Component Interconnect (PCI) bus query
* Serial Ports in Polling and Interrupt Driven Modes
.. note::
This board configuration may work with similar boards that are not officially
supported.
Hardware
********
This section provides information about the physical characteristics of the
board.
Subsections contain detailed information on pin names, jumper settings, memory
mappings, and board component layout.
Supported Features
==================
This board supports the following hardware features:
* HPET
* PCI bus
* Advanced Programmed Interrupt Controller (APIC)
* Serial Ports in Polling and Interrupt Driven Modes
* Ethernet in Interrupt Driven Mode
+-----------+------------+-----------------------+
| Interface | Controller | Driver/Component |
+===========+============+=======================+
| HPET | on-chip | system clock |
+-----------+------------+-----------------------+
| PCI | on-chip | PCI library |
+-----------+------------+-----------------------+
| APIC | on-chip | interrupt controller |
+-----------+------------+-----------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-----------------------+
| Ethernet | on-chip | Ethernet |
+-----------+------------+-----------------------+
The kernel currently does not support other hardware features.
See the `Intel Quark Core Hardware Reference Manual`_ for a
complete list of Galileo board hardware features, and the
`Intel Quark Software Developer Manual for Linux`_
PCI
----
PCI drivers assume that IO regions and IRQs for devices are
preconfigured identically by the firmware on all supported devices.
This configuration is specified in the Kconfig file for the Intel
Quark X1000 SoC. The PCI library supports dynamically enumerating PCI
devices, but that support is disabled by default.
.. note::
The PCI library does not support 64-bit devices.
Memory address and size storage only require 32-bit integers.
Serial Port Polling Mode Support
--------------------------------
The polling mode serial port allows debug output to be printed.
For more information, see `Intel Quark SoC X1000 Datasheet`_,
section 18.3.3 FIFO Polled-Mode Operation
Serial Port Interrupt Mode Support
----------------------------------
The interrupt mode serial port provides general serial communication
and external communication.
For more information, see `Intel Quark SoC X1000 Datasheet`_, section 21.12.1.4.5 Poll Mode
Interrupt Controller
--------------------
This board uses the kernel's static Interrupt Descriptor Table (IDT) to program the
Advanced Programmable Interrupt Controller (APIC) interrupt redirection table.
+-----+-------+---------+--------------------------+
| IRQ | Name | Remarks | Used by Zephyr Kernel |
+=====+=======+=========+==========================+
| 17 | INTB | UART | serial port when used in |
| | | | interrupt mode |
+-----+-------+---------+--------------------------+
| 20 | timer | HPET | timer driver |
+-----+-------+---------+--------------------------+
HPET System Clock Support
-------------------------
Galileo uses HPET timing with legacy-free timer support. The Galileo board
configuration uses HPET as a system clock timer.
Ethernet Support
-----------------
The Ethernet driver allocates a Direct Memory Access (DMA)-accessible
pair of receive and transmit buffers and descriptors. The driver
operates the network interface in store-and-forward mode and enables
the receive interrupt.
For more information, see `Intel Quark SoC X1000 Datasheet`_,
section 15.0 10/100 Mbps Ethernet
Connections and IOs
===================
For a component layout diagram showing pin names, see page 46 of the
`Intel Quark SoC X1000 Datasheet`_.
See also the `Intel Galileo Datasheet`_.
For the Galileo Board Connection Diagram see page 9 of the `Intel Galileo Board User Guide`_.
Jumpers & Switches
==================
The kernel uses the Galileo default jumper settings except for the IOREF jumper,
which must be set to match the external operating voltage of either 3.3 V or 5 V.
The Galileo default switch settings are:
+--------+--------------+
| Jumper | Setting |
+========+==============+
| IOREF | 3.3V or 5V |
+--------+--------------+
| VIN | 5V Jumpered |
+--------+--------------+
For more information, see page 14 of the
`Intel Galileo Board User Guide`_.
Memory Mappings
===============
This board configuration uses default hardware memory map
addresses and sizes.
For a list of memory mapped registers, see page 868 of the
`Intel Quark SoC X1000 Datasheet`_.
Component Layout
================
See page 3 of the Intel |reg| Galileo Datasheet for a component layout
diagram. Click the link to open the `Intel Galileo Datasheet`_.
For a block diagram, see page 38 of the `Intel Quark SoC X1000 Datasheet`_.
Programming and Debugging
*************************
Use the following procedures for booting an image on a Galileo board.
* `Creating a GRUB2 Boot Loader Image from a Linux Host`_
* `Preparing the Boot Device`_
* `Booting the Galileo Board`_
.. _grub2:
Creating a GRUB2 Boot Loader Image from a Linux Host
====================================================
If you are having problems running an application using the preinstalled
copy of GRUB, follow these steps to test on supported boards using a custom GRUB.
#. Install the requirements to build GRUB on your host machine.
On Ubuntu, type:
.. code-block:: console
$ sudo apt-get install bison autoconf libopts25-dev flex automake \
pkg-config gettext autopoint
On Fedora, type:
.. code-block:: console
$ sudo dnf install gnu-efi bison m4 autoconf help2man flex \
automake texinfo gettext-devel
#. Clone and build the GRUB repository using the script in Zephyr tree, type:
.. code-block:: console
$ cd $ZEPHYR_BASE
$ ./boards/x86/common/scripts/build_grub.sh i386
#. Find the binary at
:file:`$ZEPHYR_BASE/boards/x86/common/scripts/grub/bin/grub_i386.efi`.
Preparing the Boot Device
=========================
Prepare either an SD-micro card or USB flash drive to boot the Zephyr
application image on a Galileo board. The following instructions apply to both
devices.
#. Build a Zephyr application; for instance, to build the ``hello_world``
application on Galileo:
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: galileo
:goals: build
.. note::
A stripped project image file named :file:`zephyr.strip` is automatically
created in the build directory after the application is built. This image
has removed debug information from the :file:`zephyr.elf` file.
#. Use one of these cables for serial output:
`<http://www.ftdichip.com/Products/Cables/USBTTLSerial.htm>`_
#. Format a microSD as FAT
#. Create the following directories
:file:`efi`
:file:`efi/boot`
:file:`kernel`
#. Copy the kernel file :file:`outdir/galileo/zephyr.strip` to the :file:`$SDCARD/kernel` folder.
#. Copy your built version of GRUB to :file:`$SDCARD/efi/boot/bootia32.efi`
#. Create :file:`$SDCARD/efi/boot/grub.cfg` containing the following:
.. code-block:: console
set default=0
set timeout=10
menuentry "Zephyr Kernel" {
multiboot /kernel/zephyr.strip
}
Booting the Galileo Board
=========================
Boot the Galileo board from the boot device using GRUB2 with the firmware
present in the on-board flash.
Steps
-----
1. Insert the prepared boot device (micro-SD card or USB flash
drive) into the Galileo board.
2. Connect the board to the host system using the serial cable and
configure your host system to watch for serial data. See
`<https://software.intel.com/en-us/articles/intel-galileo-gen-2-board-assembly-using-eclipse-and-intel-xdk-iot-edition>`_
for the gen. 2 board,
`<https://software.intel.com/en-us/articles/intel-galileo-gen-1-board-assembly-using-eclipse-and-intel-xdk-iot-edition>`_
for the gen. 1 board, or the Getting Started guide that you
received with the board.
.. note::
On Windows, PuTTY has an option to set up configuration for
serial data. Use a baud rate of 115200 and the SCO keyboard
mode. The keyboard mode option is in a submenu of the Terminal
menu on the left side of the screen.
3. Power on the Galileo board.
4. When the following output appears, press :kbd:`F7`:
.. code-block:: console
Press [Enter] to directly boot.
Press [F7] to show boot menu options.
5. From the menu that appears, select :guilabel:`UEFI Misc Device` to
boot from a micro-SD card. To boot from a USB flash drive, select
the menu entry that describes that particular type of USB flash
drive.
GRUB2 starts and a menu shows entries for the items you added
to the file :file:`grub.cfg`.
6. Select the image you want to boot and press :guilabel:`Enter`.
When the boot process completes, you have finished booting the
Zephyr application image.
.. note::
If the following messages appear during boot, they can be safely
ignored.
.. code-block:: console
WARNING: no console will be available to OS
error: no suitable video mode found.
Known Problems and Limitations
******************************
At this time, the kernel does not support the following:
* Isolated Memory Regions
* Serial port in Direct Memory Access (DMA) mode
* Supervisor Mode Execution Protection (SMEP)
Bibliography
************
1. `Intel Galileo Datasheet`_, Order Number: 329681-003US
.. _Intel Galileo Datasheet:
https://www.intel.com/content/dam/support/us/en/documents/galileo/sb/galileo_datasheet_329681_003.pdf
2. `Intel Galileo Board User Guide`_.
.. _Intel Galileo Board User Guide:
http://download.intel.com/support/galileo/sb/galileo_boarduserguide_330237_001.pdf
3. `Intel Quark SoC X1000 Datasheet`_, Order Number: 329676-001US
.. _Intel Quark SoC X1000 Datasheet:
https://communities.intel.com/servlet/JiveServlet/previewBody/21828-102-2-25120/329676_QuarkDatasheet.pdf
4. `Intel Quark Core Hardware Reference Manual`_.
.. _Intel Quark Core Hardware Reference Manual:
https://www.intel.com/content/dam/support/us/en/documents/processors/quark/sb/329678_intelquarkcore_hwrefman_002.pdf
5. `Intel Quark Software Developer Manual for Linux`_.
.. _Intel Quark Software Developer Manual for Linux:
http://www.intel.com/content/dam/www/public/us/en/documents/manuals/quark-x1000-linux-sw-developers-manual.pdf

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boards/x86/galileo/galileo.dts
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/* SPDX-License-Identifier: Apache-2.0 */
/dts-v1/;
#include <mem.h>
#define DT_FLASH_SIZE DT_SIZE_K(1024)
#define DT_SRAM_SIZE DT_SIZE_M(32)
#include <quark_x1000.dtsi>
/ {
model = "galileo";
compatible = "intel,quark_x1000";
aliases {
uart-0 = &uart0;
uart-1 = &uart1;
};
chosen {
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,console = &uart1;
zephyr,shell-uart = &uart1;
};
};
&uart0 {
status = "okay";
current-speed = <115200>;
};
&uart1 {
status = "okay";
current-speed = <115200>;
};
&i2c0 {
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
};
&spi0 {
status = "okay";
};
&sharedirq0 {
status = "okay";
};

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boards/x86/galileo/galileo.yaml
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identifier: galileo
name: Galileo Gen2
type: mcu
arch: x86
toolchain:
- zephyr
supported:
- pci
- netif:eth

26
boards/x86/galileo/galileo_defconfig
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# SPDX-License-Identifier: Apache-2.0
CONFIG_X86=y
CONFIG_SOC_QUARK_X1000=y
CONFIG_SOC_SERIES_QUARK_X1000=y
CONFIG_BOARD_GALILEO=y
CONFIG_CPU_MINUTEIA=y
CONFIG_PCI_LEGACY_BRIDGE=y
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_NS16550=y
CONFIG_UART_CONSOLE=y
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=25000000
CONFIG_GPIO=y
CONFIG_GPIO_DW_0_IRQ_SHARED=y
CONFIG_PINMUX=y
CONFIG_I2C=y
CONFIG_I2C_DW=y
CONFIG_I2C_0=y
CONFIG_GPIO_PCAL9535A=y
CONFIG_GPIO_SCH=y
CONFIG_GPIO_SCH_0=y
CONFIG_GPIO_SCH_1=y
CONFIG_SHARED_IRQ=y
CONFIG_ETH_DW=y
CONFIG_ETH_DW_0=y

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boards/x86/galileo/pinmux.c
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/* pinmux_board_galileo.c - pin out mapping for the Galileo board */
/*
* Copyright (c) 2016 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <kernel.h>
#include "board.h"
#include <device.h>
#include <init.h>
#include <drivers/pinmux.h>
#include <drivers/i2c.h>
#include <drivers/gpio.h>
#include <drivers/pwm.h>
#include <pinmux/pinmux.h>
#include "pinmux_galileo.h"
/* max number of functions per pin */
#define NUM_PIN_FUNCS 4
enum gpio_chip {
NONE,
EXP0,
EXP1,
EXP2,
PWM0,
G_DW,
G_CW,
G_RW,
};
enum pin_level {
PIN_LOW = 0x00,
PIN_HIGH = 0x01,
DONT_CARE = 0xFF,
};
struct mux_pin {
enum gpio_chip mux;
u8_t pin;
enum pin_level level;
/* Pin configuration (e.g. direction, pull up/down, etc.) */
u32_t cfg;
};
/*
* This structure provides the breakdown mapping for the pinmux to follow to
* enable each functionality within the hardware. There should be nothing to
* edit here unless you absolutely know what you are doing
*/
struct mux_path {
u8_t io_pin;
u8_t func;
struct mux_pin path[5];
};
static struct mux_path _galileo_path[PINMUX_NUM_PINS * NUM_PIN_FUNCS] = {
{0, PINMUX_FUNC_A, {{ EXP1, 0, PIN_HIGH, (GPIO_DIR_OUT) }, /* GPIO3 out */
{ EXP1, 1, PIN_LOW, (GPIO_DIR_OUT) },
{ G_DW, 3, PIN_LOW, (GPIO_DIR_OUT) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{0, PINMUX_FUNC_B, {{ EXP1, 0, PIN_LOW, (GPIO_DIR_OUT) }, /* GPIO3 in */
{ EXP1, 1, PIN_LOW, (GPIO_DIR_OUT) },
{ G_DW, 3, PIN_LOW, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{0, PINMUX_FUNC_C, {{ EXP1, 0, PIN_HIGH, (GPIO_DIR_OUT) }, /* UART0_RXD */
{ EXP1, 1, PIN_LOW, (GPIO_DIR_OUT) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{0, PINMUX_FUNC_D, {{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) }, /* NONE */
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{1, PINMUX_FUNC_A, {{ EXP1, 13, PIN_LOW, (GPIO_DIR_OUT) }, /* GPIO4 out */
{ EXP0, 12, PIN_LOW, (GPIO_DIR_OUT) },
{ EXP0, 13, PIN_LOW, (GPIO_DIR_OUT) },
{ G_DW, 4, PIN_LOW, (GPIO_DIR_OUT) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{1, PINMUX_FUNC_B, {{ EXP1, 13, PIN_LOW, (GPIO_DIR_OUT) }, /* GPIO4 in */
{ EXP0, 12, PIN_HIGH, (GPIO_DIR_OUT) },
{ EXP0, 13, PIN_LOW, (GPIO_DIR_OUT) },
{ G_DW, 4, PIN_LOW, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{1, PINMUX_FUNC_C, {{ EXP1, 13, PIN_HIGH, (GPIO_DIR_OUT) }, /* UART0_TXD */
{ EXP0, 12, PIN_LOW, (GPIO_DIR_OUT) },
{ EXP0, 13, PIN_LOW, (GPIO_DIR_OUT) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{1, PINMUX_FUNC_D, {{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) }, /* NONE */
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{2, PINMUX_FUNC_A, {{ PWM0, 13, PIN_HIGH, (GPIO_DIR_OUT) }, /* GPIO5 out */
{ EXP1, 2, PIN_LOW, (GPIO_DIR_OUT) },
{ EXP1, 3, PIN_LOW, (GPIO_DIR_OUT) },
{ G_DW, 5, PIN_LOW, (GPIO_DIR_OUT) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{2, PINMUX_FUNC_B, {{ PWM0, 13, PIN_HIGH, (GPIO_DIR_OUT) }, /* GPIO5 in */
{ EXP1, 2, PIN_HIGH, (GPIO_DIR_OUT) },
{ EXP1, 3, PIN_LOW, (GPIO_DIR_OUT) },
{ G_DW, 5, PIN_LOW, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{2, PINMUX_FUNC_C, {{ PWM0, 13, PIN_LOW, (GPIO_DIR_OUT) }, /* UART1_RXD */
{ EXP1, 2, PIN_HIGH, (GPIO_DIR_OUT) },
{ EXP1, 3, PIN_HIGH, (GPIO_DIR_OUT) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{2, PINMUX_FUNC_D, {{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) }, /* NONE */
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{3, PINMUX_FUNC_A, {{ PWM0, 0, PIN_LOW, (GPIO_DIR_OUT) }, /* GPIO6 out */
{ PWM0, 12, PIN_LOW, (GPIO_DIR_OUT) },
{ EXP0, 0, PIN_LOW, (GPIO_DIR_OUT) },
{ EXP0, 1, PIN_LOW, (GPIO_DIR_OUT) },
{ G_DW, 6, PIN_LOW, (GPIO_DIR_OUT) } } },
{3, PINMUX_FUNC_B, {{ PWM0, 0, PIN_LOW, (GPIO_DIR_OUT) }, /* GPIO6 in */
{ PWM0, 12, PIN_LOW, (GPIO_DIR_OUT) },
{ EXP0, 0, PIN_HIGH, (GPIO_DIR_OUT) },
{ EXP0, 1, PIN_LOW, (GPIO_DIR_OUT) },
{ G_DW, 6, PIN_LOW, (GPIO_DIR_IN) } } },
{3, PINMUX_FUNC_C, {{ PWM0, 0, PIN_LOW, (GPIO_DIR_OUT) }, /* UART1_TXD */
{ PWM0, 12, PIN_HIGH, (GPIO_DIR_OUT) },
{ EXP0, 0, PIN_LOW, (GPIO_DIR_OUT) },
{ EXP0, 1, PIN_LOW, (GPIO_DIR_OUT) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{3, PINMUX_FUNC_D, {{ PWM0, 0, PIN_HIGH, (GPIO_DIR_OUT) }, /* PWM.LED1 */
{ PWM0, 12, PIN_LOW, (GPIO_DIR_OUT) },
{ EXP0, 0, PIN_LOW, (GPIO_DIR_OUT) },
{ EXP0, 1, PIN_LOW, (GPIO_DIR_OUT) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{4, PINMUX_FUNC_A, {{ EXP1, 4, PIN_LOW, (GPIO_DIR_OUT) }, /* GPIO_SUS4 out */
{ EXP1, 5, PIN_LOW, (GPIO_DIR_OUT) },
{ G_RW, 4, PIN_LOW, (GPIO_DIR_OUT) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{4, PINMUX_FUNC_B, {{ EXP1, 4, PIN_HIGH, (GPIO_DIR_OUT) }, /* GPIO_SUS4 in */
{ EXP1, 5, PIN_LOW, (GPIO_DIR_OUT) },
{ G_RW, 4, PIN_LOW, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{4, PINMUX_FUNC_C, {{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) }, /* NONE */
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{4, PINMUX_FUNC_D, {{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) }, /* NONE */
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{5, PINMUX_FUNC_A, {{ PWM0, 2, PIN_LOW, (GPIO_DIR_OUT) }, /* GPIO8 (out) */
{ EXP0, 2, PIN_LOW, (GPIO_DIR_OUT) },
{ EXP0, 3, PIN_LOW, (GPIO_DIR_OUT) },
{ G_CW, 0, PIN_LOW, (GPIO_DIR_OUT) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{5, PINMUX_FUNC_B, {{ PWM0, 2, PIN_LOW, (GPIO_DIR_OUT) }, /* GPIO8 (in) */
{ EXP0, 2, PIN_HIGH, (GPIO_DIR_OUT) },
{ EXP0, 3, PIN_LOW, (GPIO_DIR_OUT) },
{ G_CW, 0, PIN_LOW, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{5, PINMUX_FUNC_C, {{ PWM0, 2, PIN_HIGH, (GPIO_DIR_OUT) }, /* PWM.LED3 */
{ EXP0, 2, PIN_LOW, (GPIO_DIR_OUT) },
{ EXP0, 3, PIN_LOW, (GPIO_DIR_OUT) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{5, PINMUX_FUNC_D, {{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) }, /* NONE */
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{6, PINMUX_FUNC_A, {{ PWM0, 4, PIN_LOW, (GPIO_DIR_OUT) }, /* GPIO9 (out) */
{ EXP0, 4, PIN_LOW, (GPIO_DIR_OUT) },
{ EXP0, 5, PIN_LOW, (GPIO_DIR_OUT) },
{ G_CW, 1, PIN_LOW, (GPIO_DIR_OUT) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{6, PINMUX_FUNC_B, {{ PWM0, 4, PIN_LOW, (GPIO_DIR_OUT) }, /* GPIO9 (in) */
{ EXP0, 4, PIN_HIGH, (GPIO_DIR_OUT) },
{ EXP0, 5, PIN_LOW, (GPIO_DIR_OUT) },
{ G_CW, 1, PIN_LOW, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{6, PINMUX_FUNC_C, {{ PWM0, 4, PIN_HIGH, (GPIO_DIR_OUT) }, /* PWM.LED5 */
{ EXP0, 4, PIN_LOW, (GPIO_DIR_OUT) },
{ EXP0, 5, PIN_LOW, (GPIO_DIR_OUT) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{6, PINMUX_FUNC_D, {{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) }, /* NONE */
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{7, PINMUX_FUNC_A, {{ EXP1, 6, PIN_LOW, (GPIO_DIR_OUT) }, /* GPIO_SUS0 (out) */
{ EXP1, 7, PIN_LOW, (GPIO_DIR_OUT) },
{ G_RW, 0, PIN_HIGH, (GPIO_DIR_OUT) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{7, PINMUX_FUNC_B, {{ EXP1, 6, PIN_LOW, (GPIO_DIR_IN) }, /* GPIO_SUS0 (in) */
{ EXP1, 7, PIN_LOW, (GPIO_DIR_OUT) },
{ G_RW, 0, PIN_LOW, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{7, PINMUX_FUNC_C, {{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) }, /* NONE */
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{7, PINMUX_FUNC_D, {{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) }, /* NONE */
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{8, PINMUX_FUNC_A, {{ EXP1, 8, PIN_LOW, (GPIO_DIR_OUT) }, /* GPIO_SUS1 (out) */
{ EXP1, 9, PIN_LOW, (GPIO_DIR_OUT) },
{ G_RW, 1, PIN_LOW, (GPIO_DIR_OUT) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{8, PINMUX_FUNC_B, {{ EXP1, 8, PIN_LOW, (GPIO_DIR_IN) }, /* GPIO_SUS1 (in) */
{ EXP1, 9, PIN_LOW, (GPIO_DIR_OUT) },
{ G_RW, 1, PIN_LOW, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{8, PINMUX_FUNC_C, {{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) }, /* NONE */
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{8, PINMUX_FUNC_D, {{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) }, /* NONE */
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{9, PINMUX_FUNC_A, {{ PWM0, 6, PIN_LOW, (GPIO_DIR_OUT) }, /* GPIO_SUS2 (out) */
{ EXP0, 6, PIN_LOW, (GPIO_DIR_OUT) },
{ EXP0, 7, PIN_LOW, (GPIO_DIR_OUT) },
{ G_RW, 2, PIN_LOW, (GPIO_DIR_OUT) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{9, PINMUX_FUNC_B, {{ PWM0, 6, PIN_LOW, (GPIO_DIR_OUT) }, /* GPIO_SUS2 (in) */
{ EXP0, 6, PIN_HIGH, (GPIO_DIR_OUT) },
{ EXP0, 7, PIN_LOW, (GPIO_DIR_OUT) },
{ G_RW, 2, PIN_LOW, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{9, PINMUX_FUNC_C, {{ PWM0, 6, PIN_HIGH, (GPIO_DIR_OUT) }, /* PWM.LED7 */
{ EXP0, 6, PIN_LOW, (GPIO_DIR_OUT) },
{ EXP0, 7, PIN_LOW, (GPIO_DIR_OUT) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{9, PINMUX_FUNC_D, {{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) }, /* NONE */
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{10, PINMUX_FUNC_A, {{ PWM0, 10, PIN_LOW, (GPIO_DIR_OUT) }, /* GPIO2 (out) */
{ EXP0, 10, PIN_LOW, (GPIO_DIR_OUT) },
{ EXP0, 11, PIN_LOW, (GPIO_DIR_OUT) },
{ G_DW, 2, PIN_LOW, (GPIO_DIR_OUT) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{10, PINMUX_FUNC_B, {{ PWM0, 10, PIN_LOW, (GPIO_DIR_OUT) }, /* GPIO2 (in) */
{ EXP0, 10, PIN_HIGH, (GPIO_DIR_OUT) },
{ EXP0, 11, PIN_LOW, (GPIO_DIR_OUT) },
{ G_DW, 2, PIN_LOW, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{10, PINMUX_FUNC_C, {{ PWM0, 10, PIN_HIGH, (GPIO_DIR_OUT) }, /* PWM.LED11 */
{ EXP0, 10, PIN_LOW, (GPIO_DIR_OUT) },
{ EXP0, 11, PIN_LOW, (GPIO_DIR_OUT) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{10, PINMUX_FUNC_D, {{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) }, /* NONE */
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{11, PINMUX_FUNC_A, {{ EXP1, 12, PIN_LOW, (GPIO_DIR_OUT) }, /* GPIO_SUS3 (out) */
{ PWM0, 8, PIN_LOW, (GPIO_DIR_OUT) },
{ EXP0, 8, PIN_LOW, (GPIO_DIR_OUT) },
{ EXP0, 9, PIN_LOW, (GPIO_DIR_OUT) },
{ G_RW, 3, PIN_LOW, (GPIO_DIR_OUT) } } },
{11, PINMUX_FUNC_B, {{ EXP1, 12, PIN_LOW, (GPIO_DIR_OUT) }, /* GPIO_SUS3 (in) */
{ PWM0, 8, PIN_LOW, (GPIO_DIR_OUT) },
{ EXP0, 8, PIN_HIGH, (GPIO_DIR_OUT) },
{ EXP0, 9, PIN_LOW, (GPIO_DIR_OUT) },
{ G_RW, 3, PIN_LOW, (GPIO_DIR_IN) } } },
{11, PINMUX_FUNC_C, {{ EXP1, 12, PIN_LOW, (GPIO_DIR_OUT) }, /* PWM.LED9 */
{ PWM0, 8, PIN_HIGH, (GPIO_DIR_OUT) },
{ EXP0, 8, PIN_LOW, (GPIO_DIR_OUT) },
{ EXP0, 9, PIN_LOW, (GPIO_DIR_OUT) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{11, PINMUX_FUNC_D, {{ EXP1, 12, PIN_HIGH, (GPIO_DIR_OUT) }, /* SPI1_MOSI */
{ PWM0, 8, PIN_LOW, (GPIO_DIR_OUT) },
{ EXP0, 8, PIN_LOW, (GPIO_DIR_OUT) },
{ EXP0, 9, PIN_LOW, (GPIO_DIR_OUT) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{12, PINMUX_FUNC_A, {{ EXP1, 10, PIN_LOW, (GPIO_DIR_OUT) }, /* GPIO7 (out) */
{ EXP1, 11, PIN_LOW, (GPIO_DIR_OUT) },
{ G_DW, 7, PIN_LOW, (GPIO_DIR_OUT) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{12, PINMUX_FUNC_B, {{ EXP1, 10, PIN_HIGH, (GPIO_DIR_OUT) }, /* GPIO7 (in) */
{ EXP1, 11, PIN_LOW, (GPIO_DIR_OUT) },
{ G_DW, 7, PIN_LOW, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{12, PINMUX_FUNC_C, {{ EXP1, 10, PIN_HIGH, (GPIO_DIR_OUT) }, /* SPI1_MISO */
{ EXP1, 11, PIN_LOW, (GPIO_DIR_OUT) },
{ G_DW, 7, PIN_LOW, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{12, PINMUX_FUNC_D, {{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) }, /* NONE */
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{13, PINMUX_FUNC_A, {{ EXP1, 14, PIN_LOW, (GPIO_DIR_OUT) }, /* GPIO_SUS5 (out) */
{ EXP0, 14, PIN_LOW, (GPIO_DIR_OUT) },
{ EXP0, 15, PIN_LOW, (GPIO_DIR_OUT) },
{ G_RW, 5, PIN_LOW, (GPIO_DIR_OUT) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{13, PINMUX_FUNC_B, {{ EXP1, 14, PIN_LOW, (GPIO_DIR_OUT) }, /* GPIO_SUS5 (in) */
{ EXP0, 14, PIN_HIGH, (GPIO_DIR_OUT) },
{ EXP0, 15, PIN_LOW, (GPIO_DIR_OUT) },
{ G_RW, 5, PIN_LOW, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{13, PINMUX_FUNC_C, {{ EXP1, 14, PIN_HIGH, (GPIO_DIR_OUT) }, /* SPI1_CLK */
{ EXP0, 14, PIN_LOW, (GPIO_DIR_OUT) },
{ EXP0, 15, PIN_LOW, (GPIO_DIR_OUT) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{13, PINMUX_FUNC_D, {{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) }, /* NONE */
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{14, PINMUX_FUNC_A, {{ EXP2, 0, PIN_LOW, (GPIO_DIR_OUT) }, /* EXP2.P0_0 (out)/ADC.IN0 */
{ EXP2, 1, PIN_LOW, (GPIO_DIR_OUT) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{14, PINMUX_FUNC_B, {{ EXP2, 0, PIN_LOW, (GPIO_DIR_IN) }, /* EXP2.P0_0 (in)/ADC.IN0 */
{ EXP2, 1, PIN_LOW, (GPIO_DIR_OUT) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{14, PINMUX_FUNC_C, {{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) }, /* NONE */
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{14, PINMUX_FUNC_D, {{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) }, /* NONE */
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{15, PINMUX_FUNC_A, {{ EXP2, 2, PIN_LOW, (GPIO_DIR_OUT) }, /* EXP2.P0_2 (out)/ADC.IN1 */
{ EXP2, 3, PIN_LOW, (GPIO_DIR_OUT) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{15, PINMUX_FUNC_B, {{ EXP2, 2, PIN_LOW, (GPIO_DIR_IN) }, /* EXP2.P0_2 (in)/ADC.IN1 */
{ EXP2, 3, PIN_LOW, (GPIO_DIR_OUT) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{15, PINMUX_FUNC_C, {{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) }, /* NONE */
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{15, PINMUX_FUNC_D, {{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) }, /* NONE */
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{16, PINMUX_FUNC_A, {{ EXP2, 4, PIN_LOW, (GPIO_DIR_OUT) }, /* EXP2.P0_4 (out)/ADC.IN2 */
{ EXP2, 5, PIN_LOW, (GPIO_DIR_OUT) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{16, PINMUX_FUNC_B, {{ EXP2, 4, PIN_LOW, (GPIO_DIR_IN) }, /* EXP2.P0_4 (in)/ADC.IN2 */
{ EXP2, 5, PIN_LOW, (GPIO_DIR_OUT) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{16, PINMUX_FUNC_C, {{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) }, /* NONE */
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{16, PINMUX_FUNC_D, {{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) }, /* NONE */
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{17, PINMUX_FUNC_A, {{ EXP2, 6, PIN_LOW, (GPIO_DIR_OUT) }, /* EXP2.P0_6 (out)/ADC.IN3 */
{ EXP2, 7, PIN_LOW, (GPIO_DIR_OUT) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{17, PINMUX_FUNC_B, {{ EXP2, 6, PIN_LOW, (GPIO_DIR_IN) }, /* EXP2.P0_6 (in)/ADC.IN3 */
{ EXP2, 7, PIN_LOW, (GPIO_DIR_OUT) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{17, PINMUX_FUNC_C, {{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) }, /* NONE */
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{17, PINMUX_FUNC_D, {{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) }, /* NONE */
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{18, PINMUX_FUNC_A, {{ PWM0, 14, PIN_HIGH, (GPIO_DIR_OUT) }, /* EXP2.P1_0 (out) */
{ EXP2, 12, PIN_HIGH, (GPIO_DIR_OUT) },
{ EXP2, 8, PIN_LOW, (GPIO_DIR_OUT) },
{ EXP2, 9, PIN_LOW, (GPIO_DIR_OUT) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{18, PINMUX_FUNC_B, {{ PWM0, 14, PIN_LOW, (GPIO_DIR_OUT) }, /* ADC.IN4 (in) */
{ EXP2, 12, PIN_HIGH, (GPIO_DIR_OUT) },
{ EXP2, 8, PIN_LOW, (GPIO_DIR_IN) },
{ EXP2, 9, PIN_LOW, (GPIO_DIR_OUT) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{18, PINMUX_FUNC_C, {{ PWM0, 14, PIN_HIGH, (GPIO_DIR_OUT) }, /* I2C SDA */
{ EXP2, 9, PIN_LOW, (GPIO_DIR_OUT) },
{ EXP2, 12, PIN_LOW, (GPIO_DIR_OUT) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{18, PINMUX_FUNC_D, {{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) }, /* NONE */
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{19, PINMUX_FUNC_A, {{ PWM0, 15, PIN_HIGH, (GPIO_DIR_OUT) }, /* EXP2.P1_2 (out)*/
{ EXP2, 12, PIN_HIGH, (GPIO_DIR_OUT) },
{ EXP2, 10, PIN_LOW, (GPIO_DIR_OUT) },
{ EXP2, 11, PIN_LOW, (GPIO_DIR_OUT) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{19, PINMUX_FUNC_B, {{ PWM0, 15, PIN_LOW, (GPIO_DIR_OUT) }, /* ADC.IN5 */
{ EXP2, 12, PIN_HIGH, (GPIO_DIR_OUT) },
{ EXP2, 10, PIN_LOW, (GPIO_DIR_IN) },
{ EXP2, 11, PIN_LOW, (GPIO_DIR_OUT) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{19, PINMUX_FUNC_C, {{ PWM0, 15, PIN_HIGH, (GPIO_DIR_OUT) }, /* I2C SCL */
{ EXP2, 11, PIN_LOW, (GPIO_DIR_OUT) },
{ EXP2, 12, PIN_LOW, (GPIO_DIR_OUT) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
{19, PINMUX_FUNC_D, {{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) }, /* NONE */
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) },
{ NONE, 0, DONT_CARE, (GPIO_DIR_IN) } } },
};
int z_galileo_pinmux_set_pin(struct device *port, u8_t pin, u32_t func)
{
struct galileo_data * const drv_data = port->driver_data;
u8_t mux_index = 0U;
u8_t i = 0U;
struct mux_path *enable = NULL;
struct pin_config *mux_config = drv_data->mux_config;
if (pin > PINMUX_NUM_PINS) {
return -ENOTSUP;
}
mux_config[pin].mode = func;
/* NUM_PIN_FUNCS being the number of alt functions */
mux_index = NUM_PIN_FUNCS * pin;
/*
* functions are in numeric order, we can just skip to the index
* needed
*/
mux_index += func;
enable = &_galileo_path[mux_index];
for (i = 0U; i < 5; i++) {
switch (enable->path[i].mux) {
case EXP0:
gpio_pin_write(drv_data->exp0,
enable->path[i].pin,
enable->path[i].level);
gpio_pin_configure(drv_data->exp0,
enable->path[i].pin,
enable->path[i].cfg);
break;
case EXP1:
gpio_pin_write(drv_data->exp1,
enable->path[i].pin,
enable->path[i].level);
gpio_pin_configure(drv_data->exp1,
enable->path[i].pin,
enable->path[i].cfg);
break;
case EXP2:
gpio_pin_write(drv_data->exp2,
enable->path[i].pin,
enable->path[i].level);
gpio_pin_configure(drv_data->exp2,
enable->path[i].pin,
enable->path[i].cfg);
break;
case PWM0:
pwm_pin_set_cycles(drv_data->pwm0,
enable->path[i].pin,
100,
enable->path[i].level ? 100 : 0);
break;
case G_DW:
gpio_pin_write(drv_data->gpio_dw,
enable->path[i].pin,
enable->path[i].level);
gpio_pin_configure(drv_data->gpio_dw,
enable->path[i].pin,
enable->path[i].cfg);
break;
case G_CW:
gpio_pin_write(drv_data->gpio_core,
enable->path[i].pin,
enable->path[i].level);
gpio_pin_configure(drv_data->gpio_core,
enable->path[i].pin,
enable->path[i].cfg);
break;
case G_RW:
gpio_pin_write(drv_data->gpio_resume,
enable->path[i].pin,
enable->path[i].level);
gpio_pin_configure(drv_data->gpio_resume,
enable->path[i].pin,
enable->path[i].cfg);
break;
case NONE:
/* no need to do anything */
break;
default:
__ASSERT(false, "Invalid pinmux option");
break;
}
}
return 0;
}
int z_galileo_pinmux_get_pin(struct device *port, u32_t pin, u32_t *func)
{
struct galileo_data * const drv_data = port->driver_data;
struct pin_config *mux_config = drv_data->mux_config;
*func = mux_config[pin].mode;
return 0;
}
/* Alter this table to change the default pin settings on the Galileo Gen2
* boards. Specifically change the PINMUX_FUNC_* value to represent the
* functionaltiy desired
*/
static struct pin_config mux_config[PINMUX_NUM_PINS] = {
/* pin, selected mode <mode A, mode B, mode C, mode D> */
/* Analog Inputs */
{ 0, PINMUX_FUNC_C }, /* GPIO3 (out), GPIO3 (in), UART0_RXD, NA */
{ 1, PINMUX_FUNC_C }, /* GPIO4 (out), GPIO4 (in), UART0_TXD, NA */
{ 2, PINMUX_FUNC_C }, /* GPIO5 (out), GPIO5 (in), UART1_RXD, NA */
{ 3, PINMUX_FUNC_C }, /* GPIO6 (out), GPIO6 (in), UART1_TXD, PWM.LED1 */
{ 4, PINMUX_FUNC_B }, /* GPIO_SUS4 (out), GPIO_SUS4 (in), NA, NA */
{ 5, PINMUX_FUNC_B }, /* GPIO8 (out), GPIO8 (in), PWM.LED3, NA */
{ 6, PINMUX_FUNC_B }, /* GPIO9 (out), GPIO9 (in), PWM.LED5, NA */
{ 7, PINMUX_FUNC_A }, /* EXP1.P0_6 (out), EXP1.P0_6 (in), NA, NA */
{ 8, PINMUX_FUNC_A }, /* EXP1.P1_0 (out), EXP1.P1_0 (in), NA, NA */
{ 9, PINMUX_FUNC_B }, /* GPIO_SUS2 (out), GPIO_SUS2 (in), PWM.LED7, NA */
#if defined(CONFIG_SPI_1)
{ 10, PINMUX_FUNC_A }, /* GPIO2 (out), GPIO2 (in), PWM.LED11, NA */
{ 11, PINMUX_FUNC_D }, /* GPIO_SUS3 (out), GPIO_SUS3 (in), PWM.LED9, SPI1_MOSI */
{ 12, PINMUX_FUNC_C }, /* GPIO7 (out), GPIO7 (in), SPI1_MISO, NA */
{ 13, PINMUX_FUNC_C }, /* GPIO_SUS5 (out), GPIO_SUS5(in), SPI1_SCK, NA */
#else
{ 10, PINMUX_FUNC_B }, /* GPIO2 (out), GPIO2 (in), PWM.LED11, NA */
{ 11, PINMUX_FUNC_B }, /* GPIO_SUS3 (out), GPIO_SUS3 (in), PWM.LED9, SPI1_MOSI */
{ 12, PINMUX_FUNC_B }, /* GPIO7 (out), GPIO7 (in), SPI1_MISO, NA */
{ 13, PINMUX_FUNC_B }, /* GPIO_SUS5 (out), GPIO_SUS5(in), SPI1_SCK, NA */
#endif
{ 14, PINMUX_FUNC_B }, /* EXP2.P0_0 (out)/ADC.IN0, EXP2.P0_0 (in)/ADC.IN0, NA, NA */
{ 15, PINMUX_FUNC_B }, /* EXP2.P0_2 (out)/ADC.IN1, EXP2.P0_2 (in)/ADC.IN1, NA, NA */
{ 16, PINMUX_FUNC_B }, /* EXP2.P0_4 (out)/ADC.IN2, EXP2.P0_4 (in)/ADC.IN2, NA, NA */
{ 17, PINMUX_FUNC_B }, /* EXP2.P0_6 (out)/ADC.IN3, EXP2.P0_6 (in)/ADC.IN3, NA, NA */
{ 18, PINMUX_FUNC_C }, /* EXP2.P1_0 (out), ADC.IN4, I2C_SDA, NA */
{ 19, PINMUX_FUNC_C }, /* EXP2.P1_2 (out), ADC.IN5, I2C_SCL, NA */
};
static int pinmux_pullup(struct device *dev,
u32_t pin,
u8_t func)
{
/*
* Nothing to do.
* On Galileo the pullup operation is handled through the selection
* of an actual pin
*/
ARG_UNUSED(dev);
ARG_UNUSED(pin);
ARG_UNUSED(func);
return 0;
}
static int pinmux_input_enable(struct device *dev,
u32_t pin,
u8_t func)
{
/*
* Nothing to do.
* On Galileo select a pin for input enabling is handled through the
* selection of an actual pin user configuration.
*/
ARG_UNUSED(dev);
ARG_UNUSED(pin);
ARG_UNUSED(func);
return 0;
}
static int pinmux_set(struct device *dev,
u32_t pin,
u32_t func)
{
if (pin > PINMUX_NUM_PINS) {
return -EINVAL;
}
return z_galileo_pinmux_set_pin(dev, pin, func);
}
static int pinmux_get(struct device *dev,
u32_t pin,
u32_t *func)
{
if (pin > PINMUX_NUM_PINS) {
return -EINVAL;
}
return z_galileo_pinmux_get_pin(dev, pin, func);
}
static struct pinmux_driver_api api_funcs = {
.set = pinmux_set,
.get = pinmux_get,
.pullup = pinmux_pullup,
.input = pinmux_input_enable
};
struct galileo_data galileo_pinmux_driver = {
.exp0 = NULL,
.exp1 = NULL,
.exp2 = NULL,
.pwm0 = NULL,
.mux_config = mux_config,
};
static int pinmux_galileo_initialize(struct device *port)
{
struct galileo_data *dev = port->driver_data;
int i;
/* Grab the EXP0, EXP1, EXP2, and PWM0 now by name */
dev->exp0 = device_get_binding(PINMUX_GALILEO_EXP0_NAME);
if (!dev->exp0) {
return -EINVAL;
}
dev->exp1 = device_get_binding(PINMUX_GALILEO_EXP1_NAME);
if (!dev->exp1) {
return -EINVAL;
}
dev->exp2 = device_get_binding(PINMUX_GALILEO_EXP2_NAME);
if (!dev->exp2) {
return -EINVAL;
}
dev->pwm0 = device_get_binding(PINMUX_GALILEO_PWM0_NAME);
if (!dev->pwm0) {
return -EINVAL;
}
dev->gpio_dw = device_get_binding(PINMUX_GALILEO_GPIO_DW_NAME);
if (!dev->gpio_dw) {
return -EINVAL;
}
dev->gpio_core = device_get_binding(
PINMUX_GALILEO_GPIO_INTEL_CW_NAME);
if (!dev->gpio_core) {
return -EINVAL;
}
dev->gpio_resume = device_get_binding(
PINMUX_GALILEO_GPIO_INTEL_RW_NAME);
if (!dev->gpio_resume) {
return -EINVAL;
}
/*
* Now that we have everything, let us start parsing everything
* from the above mapping as selected by the end user
*/
for (i = 0; i < PINMUX_NUM_PINS; i++) {
z_galileo_pinmux_set_pin(port,
mux_config[i].pin_num,
mux_config[i].mode);
}
return 0;
}
/*
* This needs to be a level 2 or later init process due to the following
* dependency chain:
* 0 - I2C
* 1 - PCA9535 and PCAL9685
* 2 - pinmux
*/
DEVICE_AND_API_INIT(pmux, CONFIG_PINMUX_NAME, &pinmux_galileo_initialize,
&galileo_pinmux_driver, NULL,
POST_KERNEL, CONFIG_PINMUX_INIT_PRIORITY, &api_funcs);

36
boards/x86/galileo/pinmux_galileo.h
View file

@ -1,36 +0,0 @@
/* pinmux_galileo.h */
/*
* Copyright (c) 2016 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __PINMUX_GALILEO_PRIV_H
#define __PINMUX_GALILEO_PRIV_H
struct galileo_data {
struct device *exp0;
struct device *exp1;
struct device *exp2;
struct device *pwm0;
/* GPIO<0>..GPIO<7> */
struct device *gpio_dw;
/* GPIO<8>..GPIO<9>, which means to pin 0 and 1 on core well. */
struct device *gpio_core;
/* GPIO_SUS<0>..GPIO_SUS<5> */
struct device *gpio_resume;
struct pin_config *mux_config;
};
struct galileo_data galileo_pinmux_driver;
int z_galileo_pinmux_set_pin(struct device *port, u8_t pin, u32_t func);
int z_galileo_pinmux_get_pin(struct device *port, u32_t pin, u32_t *func);
#endif /* __PINMUX_GALILEO_PRIV_H */

1
doc/conf.py
View file

@ -409,7 +409,6 @@ html_redirect_pages = [
('boards/riscv32/qemu_riscv32/doc/board', 'boards/riscv32/qemu_riscv32/doc/index'),
('boards/riscv32/zedboard_pulpino/doc/zedboard_pulpino', 'boards/riscv32/zedboard_pulpino/doc/index'),
('boards/x86/arduino_101/doc/board', 'boards/x86/arduino_101/doc/index'),
('boards/x86/galileo/doc/galileo', 'boards/x86/galileo/doc/index'),
('boards/x86/minnowboard/doc/minnowboard', 'boards/x86/minnowboard/doc/index'),
('boards/x86/qemu_x86/doc/board', 'boards/x86/qemu_x86/doc/index'),
('boards/x86/tinytile/doc/board', 'boards/x86/tinytile/doc/index'),

118
dts/x86/quark_x1000.dtsi
View file

@ -1,118 +0,0 @@
/*
* Copyright (c) 2017 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "skeleton.dtsi"
#include <dt-bindings/interrupt-controller/intel-ioapic.h>
#include <dt-bindings/i2c/i2c.h>
#include <dt-bindings/pcie/pcie.h>
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "quark_x1000";
reg = <0>;
};
};
flash0: flash@100000{
compatible = "soc-nv-flash";
reg = <0x00100000 DT_FLASH_SIZE>;
};
sram0: memory@400000 {
device_type = "memory";
compatible = "mmio-sram";
reg = <0x00400000 DT_SRAM_SIZE>;
};
intc: ioapic@fec00000 {
compatible = "intel,ioapic";
reg = <0xfec00000 0x1000>;
interrupt-controller;
#interrupt-cells = <3>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges;
uart0: uart@0 {
compatible = "ns16550";
pcie; reg = <PCIE_BDF(0,0x14,1) PCIE_ID(0x8086,0x936)>;
label = "UART_0";
clock-frequency = <44236800>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW 0>;
interrupt-parent = <&intc>;
status = "disabled";
};
uart1: uart@1 {
compatible = "ns16550";
pcie; reg = <PCIE_BDF(0,0x14,5) PCIE_ID(0x8086,0x936)>;
label = "UART_1";
clock-frequency = <44236800>;
interrupts = <17 IRQ_TYPE_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
status = "disabled";
};
i2c0: i2c@0 {
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
pcie;
reg = <PCIE_BDF(0,21,2) PCIE_ID(0x8086,0x0934)>;
interrupts = <25 IRQ_TYPE_LEVEL_LOW 2>;
interrupt-parent = <&intc>;
label = "I2C_0";
status = "disabled";
};
spi0: spi@90009000 {
compatible = "intel,intel-spi";
reg = <0x90009000 0x400>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <16 IRQ_TYPE_EDGE_RISING 2>;
interrupt-parent = <&intc>;
label = "SPI_0";
status = "disabled";
};
spi1: spi@90008000 {
compatible = "intel,intel-spi";
reg = <0x90008000 0x400>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <17 IRQ_TYPE_EDGE_RISING 2>;
interrupt-parent = <&intc>;
label = "SPI_1";
status = "disabled";
};
};
sharedirq0: sharedirq0 {
compatible = "shared-irq";
label = "SHARED_IRQ0";
interrupts = <18 IRQ_TYPE_LEVEL_LOW 2>;
interrupt-parent = <&intc>;
status = "disabled";
};
};

8
soc/x86/intel_quark/quark_x1000/CMakeLists.txt
View file

@ -1,8 +0,0 @@
# SPDX-License-Identifier: Apache-2.0
zephyr_library_include_directories(${ZEPHYR_BASE}/drivers)
zephyr_cc_option(-march=lakemont -mtune=lakemont -msoft-float)
zephyr_sources(soc.c)

14
soc/x86/intel_quark/quark_x1000/Kconfig.defconfig.quark_x1000
View file

@ -1,14 +0,0 @@
# Kconfig - Quark X1000 configuration options
#
# Copyright (c) 2015-2016 Intel Corporation
#
# SPDX-License-Identifier: Apache-2.0
#
if SOC_QUARK_X1000
config SOC
default "quark_x1000"
endif # SOC_QUARK_X1000

188
soc/x86/intel_quark/quark_x1000/Kconfig.defconfig.series
View file

@ -1,188 +0,0 @@
# Kconfig - Quark X1000 SoC configuration options
#
# Copyright (c) 2014-2015 Wind River Systems, Inc.
# Copyright (c) 2015-2016 Intel Corporation
#
# SPDX-License-Identifier: Apache-2.0
#
if SOC_SERIES_QUARK_X1000
config SOC_SERIES
default "quark_x1000"
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 25000000 if HPET_TIMER
config CLFLUSH_DETECT
default y if CACHE_FLUSHING
if SHARED_IRQ
config SHARED_IRQ_0
default y
endif # SHARED_IRQ
if PCI_LEGACY_BRIDGE
config PCI_LEGACY_BRIDGE_BUS
default 0
config PCI_LEGACY_BRIDGE_DEV
default 31
config PCI_LEGACY_BRIDGE_VENDOR_ID
default 0x8086
config PCI_LEGACY_BRIDGE_DEVICE_ID
default 0x095e
endif # PCI_LEGACY_BRIDGE
if I2C
config I2C_DW
default y
if I2C_DW
config I2C_DW_CLOCK_SPEED
default 25
config I2C_0
default y
if I2C_0
config I2C_0_IRQ_PRI
default 2
endif # I2C_0
endif # I2C_DW
endif # I2C
if GPIO
config GPIO_SCH
default y
if GPIO_SCH
config GPIO_SCH_0
default y
config GPIO_SCH_1
default y
if GPIO_SCH_0
config GPIO_SCH_0_DEV_NAME
default "GPIO_CW"
endif # GPIO_SCH_0
if GPIO_SCH_1
config GPIO_SCH_1_DEV_NAME
default "GPIO_RW"
endif # GPIO_SCH_1
endif # GPIO_SCH
config GPIO_DW
default y
if GPIO_DW
config GPIO_DW_0
default y
if GPIO_DW_0
config GPIO_DW_0_NAME
default "GPIO_0"
config GPIO_DW_0_IRQ_PRI
default 2
endif # GPIO_DW_0
endif # GPIO_DW
endif # GPIO
if SPI
config SPI_INTEL
default y
if SPI_INTEL
config SPI_0
default y
config SPI_1
default n
endif # SPI_INTEL
endif # SPI
if UART_NS16550
config UART_NS16550_PORT_0
default y
if UART_NS16550_PORT_0
config UART_NS16550_PORT_0_OPTIONS
default 0
endif # UART_NS16550_PORT_0
config UART_NS16550_PORT_1
default y if PCI
if UART_NS16550_PORT_1
config UART_NS16550_PORT_1_OPTIONS
default 0
endif # UART_NS16550_PORT_1
endif # UART_NS16550
if NET_L2_ETHERNET
config ETH_DW
default y
if ETH_DW
config ETH_DW_0
default y
endif # ETH_DW
endif # NET_L2_ETHERNET
# Pin multiplexer uses PCAL9535A, needs to be initialized after it
config PINMUX_INIT_PRIORITY
default 80 if PINMUX
if UART_CONSOLE
endif
if BT_UART
config BT_UART_ON_DEV_NAME
default "UART_1"
endif
source "soc/x86/intel_quark/quark_x1000/Kconfig.defconfig.quark_x1000"
endif # SOC_SERIES_QUARK_X1000

15
soc/x86/intel_quark/quark_x1000/Kconfig.series
View file

@ -1,15 +0,0 @@
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_QUARK_X1000
bool "Intel Quark X1000 Series"
select CPU_MINUTEIA
select CPU_HAS_FPU
select HPET_TIMER
select PCI
select PCI_ENUMERATION
select PCIE
select PCIE_MSI
select SOC_FAMILY_QUARK
select HAS_I2C_DW
help
Intel Quark X1000 SoC.

15
soc/x86/intel_quark/quark_x1000/Kconfig.soc
View file

@ -1,15 +0,0 @@
# SPDX-License-Identifier: Apache-2.0
config SOC_QUARK_X1000
bool "Quark X1000"
select CPU_MINUTEIA
select CPU_HAS_FPU
select HPET_TIMER
select PCI
select PCI_ENUMERATION
select PCIE
select PCIE_MSI
select HAS_I2C_DW
depends on SOC_SERIES_QUARK_X1000
help
Intel Quark X1000 SoC.

55
soc/x86/intel_quark/quark_x1000/dts_fixup.h
View file

@ -1,55 +0,0 @@
/* SPDX-License-Identifier: Apache-2.0 */
#define DT_UART_NS16550_PORT_0_BASE_ADDR DT_INST_0_NS16550_BASE_ADDRESS
#define DT_UART_NS16550_PORT_0_SIZE DT_INST_0_NS16550_SIZE
#define DT_UART_NS16550_PORT_0_BAUD_RATE DT_INST_0_NS16550_CURRENT_SPEED
#define DT_UART_NS16550_PORT_0_NAME DT_INST_0_NS16550_LABEL
#define DT_UART_NS16550_PORT_0_IRQ DT_INST_0_NS16550_IRQ_0
#define DT_UART_NS16550_PORT_0_IRQ_PRI DT_INST_0_NS16550_IRQ_0_PRIORITY
#define DT_UART_NS16550_PORT_0_IRQ_FLAGS DT_INST_0_NS16550_IRQ_0_SENSE
#define DT_UART_NS16550_PORT_0_CLK_FREQ DT_INST_0_NS16550_CLOCK_FREQUENCY
#define DT_UART_NS16550_PORT_0_PCIE DT_INST_0_NS16550_PCIE
#define DT_UART_NS16550_PORT_1_BASE_ADDR DT_INST_1_NS16550_BASE_ADDRESS
#define DT_UART_NS16550_PORT_1_SIZE DT_INST_1_NS16550_SIZE
#define DT_UART_NS16550_PORT_1_BAUD_RATE DT_INST_1_NS16550_CURRENT_SPEED
#define DT_UART_NS16550_PORT_1_NAME DT_INST_1_NS16550_LABEL
#define DT_UART_NS16550_PORT_1_IRQ DT_INST_1_NS16550_IRQ_0
#define DT_UART_NS16550_PORT_1_IRQ_PRI DT_INST_1_NS16550_IRQ_0_PRIORITY
#define DT_UART_NS16550_PORT_1_IRQ_FLAGS DT_INST_1_NS16550_IRQ_0_SENSE
#define DT_UART_NS16550_PORT_1_CLK_FREQ DT_INST_1_NS16550_CLOCK_FREQUENCY
#define DT_UART_NS16550_PORT_1_PCIE DT_INST_1_NS16550_PCIE
#define DT_PHYS_RAM_ADDR CONFIG_SRAM_BASE_ADDRESS
#define DT_PHYS_LOAD_ADDR CONFIG_FLASH_BASE_ADDRESS
#define DT_RAM_SIZE CONFIG_SRAM_SIZE
#define DT_ROM_SIZE CONFIG_FLASH_SIZE
#define DT_IOAPIC_BASE_ADDRESS DT_INTEL_IOAPIC_FEC00000_BASE_ADDRESS
#define DT_SPI_0_BASE_ADDRESS DT_INTEL_INTEL_SPI_90009000_BASE_ADDRESS
#define DT_SPI_0_IRQ DT_INTEL_INTEL_SPI_90009000_IRQ_0
#define DT_SPI_0_IRQ_FLAGS DT_INTEL_INTEL_SPI_90009000_IRQ_0_SENSE
#define DT_SPI_0_IRQ_PRI DT_INTEL_INTEL_SPI_90009000_IRQ_0_PRIORITY
#define DT_SPI_0_NAME DT_INTEL_INTEL_SPI_90009000_LABEL
#define DT_SPI_1_BASE_ADDRESS DT_INTEL_INTEL_SPI_90008000_BASE_ADDRESS
#define DT_SPI_1_IRQ DT_INTEL_INTEL_SPI_90008000_IRQ_0
#define DT_SPI_1_IRQ_FLAGS DT_INTEL_INTEL_SPI_90008000_IRQ_0_SENSE
#define DT_SPI_1_IRQ_PRI DT_INTEL_INTEL_SPI_90008000_IRQ_0_PRIORITY
#define DT_SPI_1_NAME DT_INTEL_INTEL_SPI_90008000_LABEL
#ifdef CONFIG_I2C_0
#define DT_I2C_DW_0_IRQ_SHARED_NAME DT_SHARED_IRQ_SHAREDIRQ0_LABEL
#endif
#ifdef CONFIG_GPIO_DW_0
#define DT_GPIO_DW_0_IRQ_SHARED_NAME DT_SHARED_IRQ_SHAREDIRQ0_LABEL
#endif
#ifdef CONFIG_ETH_DW_0
#define DT_ETH_DW_0_IRQ_SHARED_NAME DT_SHARED_IRQ_SHAREDIRQ0_LABEL
#endif

46
soc/x86/intel_quark/quark_x1000/linker.ld
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@ -1,46 +0,0 @@
/*
* Copyright (c) 2011-2014, Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Linker command/script file
*
* This is the linker script for both standard images and XIP images.
*/
#include <autoconf.h>
#include <generated_dts_board.h>
/* physical address where the kernel is loaded */
#define PHYS_LOAD_ADDR DT_PHYS_LOAD_ADDR
/* physical address of RAM */
#ifdef CONFIG_XIP
#define PHYS_RAM_ADDR DT_PHYS_RAM_ADDR
#else /* !CONFIG_XIP */
#define PHYS_RAM_ADDR PHYS_LOAD_ADDR
#endif /* CONFIG_XIP */
MEMORY
{
#ifdef CONFIG_XIP
ROM (rx) : ORIGIN = PHYS_LOAD_ADDR, LENGTH = DT_ROM_SIZE*1K
RAM (wx) : ORIGIN = PHYS_RAM_ADDR, LENGTH = DT_RAM_SIZE*1K
#else /* !CONFIG_XIP */
RAM (wx) : ORIGIN = PHYS_LOAD_ADDR, LENGTH = DT_RAM_SIZE*1K
#endif /* CONFIG_XIP */
/*
* It doesn't matter where this region goes as it is stripped from the
* final ELF image. The address doesn't even have to be valid on the
* target. However, it shouldn't overlap any other regions.
*/
IDT_LIST : ORIGIN = 2K, LENGTH = 2K
}
#include <arch/x86/ia32/linker.ld>

66
soc/x86/intel_quark/quark_x1000/soc.c
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@ -1,66 +0,0 @@
/*
* Copyright (c) 2013-2015, Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief System/hardware module for the galileo platform
*
* This module provides routines to initialize and support board-level hardware
* for the galileo platform.
*
* Implementation Remarks:
* Handlers for the secondary serial port have not been added.
*/
#include <kernel.h>
#include <init.h>
#include <device.h>
#include <sys/printk.h>
#include <sys/__assert.h>
#include "soc.h"
#include <drivers/uart.h>
#include <drivers/pci/pci.h>
#include <drivers/pci/pci_mgr.h>
#include <drivers/interrupt_controller/ioapic.h>
#ifdef CONFIG_PCI_LEGACY_BRIDGE
/**
*
* @brief Configure PCI interrupt pin to IRQ mapping
*
* The routine detects PCI legacy bridge and if present,
* configures PCI interrupt pin to IRQ mapping for D:20
* and D:21 IO Fabric, that contains the following devices:
* - SPI0, SPI1;
* - I2C;
* - GPIO;
* - UART0, UART1;
* - SDIO/eMMC, USB, Ethernet.
*/
static int pci_legacy_bridge_irq_config(struct device *unused)
{
ARG_UNUSED(unused);
struct pci_dev_info info = {
.function = PCI_FUNCTION_ANY,
.bar = PCI_BAR_ANY,
};
if (pci_legacy_bridge_detect(&info) == 0) {
pci_legacy_bridge_configure(&info, 1, PCI_INTA, 16);
pci_legacy_bridge_configure(&info, 1, PCI_INTB, 17);
pci_legacy_bridge_configure(&info, 1, PCI_INTC, 18);
pci_legacy_bridge_configure(&info, 1, PCI_INTD, 19);
pci_legacy_bridge_configure(&info, 0, PCI_INTA, 17);
pci_legacy_bridge_configure(&info, 0, PCI_INTB, 18);
pci_legacy_bridge_configure(&info, 0, PCI_INTC, 19);
pci_legacy_bridge_configure(&info, 0, PCI_INTD, 16);
}
return 0;
}
SYS_INIT(pci_legacy_bridge_irq_config,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE);
#endif /* CONFIG_PCI_LEGACY_BRIDGE */

170
soc/x86/intel_quark/quark_x1000/soc.h
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@ -1,170 +0,0 @@
/*
* Copyright (c) 2013-2015, Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Board configuration macros for the Quark X1000 SoC
*
* This header file is used to specify and describe SoC-level aspects for
* the Quark X1000 SoC.
*/
#ifndef __SOC_H_
#define __SOC_H_
#include <sys/util.h>
#ifndef _ASMLANGUAGE
#include <device.h>
#include <random/rand32.h>
#endif
#ifdef CONFIG_IOAPIC
#include <drivers/interrupt_controller/ioapic.h>
#endif
/*
* Ethernet (DesignWare)
*/
#define ETH_DW_PCI_VENDOR_ID 0x8086
#define ETH_DW_PCI_DEVICE_ID 0x0937
#define ETH_DW_PCI_CLASS 0x02
#define ETH_DW_0_BASE_ADDR 0x90002000
#define ETH_DW_0_IRQ 18
#define ETH_DW_0_PCI_BUS 0
#define ETH_DW_0_PCI_DEV 20
#define ETH_DW_0_PCI_FUNCTION 6
#define ETH_DW_0_PCI_BAR 0
/*
* SPI
*/
#define SPI_INTEL_VENDOR_ID 0x8086
#define SPI_INTEL_DEVICE_ID 0x935
#define SPI_INTEL_CLASS 0x0C
#define SPI_INTEL_PORT_0_BUS 0
#define SPI_INTEL_PORT_0_DEV 21
#define SPI_INTEL_PORT_0_FUNCTION 0
#define SPI_INTEL_PORT_1_BUS 0
#define SPI_INTEL_PORT_1_DEV 21
#define SPI_INTEL_PORT_1_FUNCTION 1
/*
* GPIO
*/
#define GPIO_SCH_LEGACY_IO_PORTS_ACCESS
#define GPIO_SCH_0_BASE_ADDR 0x1080
#define GPIO_SCH_0_BITS 2
#define GPIO_SCH_1_BASE_ADDR 0x10A0
#define GPIO_SCH_1_BITS 6
#define GPIO_DW_PCI_VENDOR_ID 0x8086
#define GPIO_DW_PCI_DEVICE_ID 0x0934
#define GPIO_DW_PCI_CLASS 0x0C
#define DT_GPIO_DW_0_BASE_ADDR 0x90006000
#define DT_GPIO_DW_0_IRQ 18
#define DT_GPIO_DW_0_BITS 8
#define GPIO_DW_0_PCI_BUS 0
#define GPIO_DW_0_PCI_DEV 21
#define GPIO_DW_0_PCI_FUNCTION 2
#define GPIO_DW_0_PCI_BAR 1
#if defined(CONFIG_IOAPIC)
#define DT_GPIO_DW_0_IRQ_FLAGS (IOAPIC_LEVEL | IOAPIC_LOW)
#endif
#ifdef CONFIG_IOAPIC
#define UART_IRQ_FLAGS (IOAPIC_LEVEL | IOAPIC_LOW)
#endif /* CONFIG_IOAPIC */
#ifdef __cplusplus
extern "C" {
#endif
#define NUM_STD_IRQS 16 /* number of "standard" IRQs on an x86 platform */
#define INT_VEC_IRQ0 0x20 /* Vector number for IRQ0 */
/*
* The IRQ_CONNECT() API connects to a (virtualized) IRQ and the
* associated interrupt controller is programmed with the allocated vector.
* The Quark board virtualizes IRQs as follows:
*
* - The first CONFIG_IOAPIC_NUM_RTES IRQs are provided by the IOAPIC
* - The remaining IRQs are provided by the LOAPIC.
*
* Thus, for example, if the IOAPIC supports 24 IRQs:
*
* - IRQ0 to IRQ23 map to IOAPIC IRQ0 to IRQ23
* - IRQ24 to IRQ29 map to LOAPIC LVT entries as follows:
*
* IRQ24 -> LOAPIC_TIMER
* IRQ25 -> LOAPIC_THERMAL
* IRQ26 -> LOAPIC_PMC
* IRQ27 -> LOAPIC_LINT0
* IRQ28 -> LOAPIC_LINT1
* IRQ29 -> LOAPIC_ERROR
*/
/* PCI definitions */
#define PCI_BUS_NUMBERS 2
#define PCI_CTRL_ADDR_REG 0xCF8
#define PCI_CTRL_DATA_REG 0xCFC
#define PCI_INTA 1
#define PCI_INTB 2
#define PCI_INTC 3
#define PCI_INTD 4
/**
*
* @brief Convert PCI interrupt PIN to IRQ
*
* The routine uses "standard design consideration" and implies that
* INTA (pin 1) -> IRQ 16
* INTB (pin 2) -> IRQ 17
* INTC (pin 3) -> IRQ 18
* INTD (pin 4) -> IRQ 19
*
* In case a mini-PCIe card is used, the IRQs are swizzled:
* INTA (pin 1) -> IRQ 17
* INTB (pin 2) -> IRQ 18
* INTC (pin 3) -> IRQ 19
* INTD (pin 4) -> IRQ 16
*
* @return IRQ number, -1 if the result is incorrect
*
*/
static inline int pci_pin2irq(int bus, int dev, int pin)
{
ARG_UNUSED(dev);
if (bus < 0 || bus > 1) {
return -1;
}
if ((pin < PCI_INTA) || (pin > PCI_INTD)) {
return -1;
}
return NUM_STD_IRQS + ((pin - 1 + bus) & 3);
}
#ifdef __cplusplus
}
#endif
#endif /* __SOC_H_ */

4
tests/kernel/threads/no-multithreading/testcase.yaml
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@ -2,7 +2,3 @@ tests:
kernel.threads.no-multithreading:
tags: kernel
filter: not CONFIG_SMP
# Pulls in GPIO by default, which needs missing APIs (why?!), but
# its headers won't build with GPIO disabled.
platform_exclude: galileo