drivers: adc: enable ADC on STM32WB
Enable ADC on STM32WB Signed-off-by: Rick Conrey <rick.conrey@witiproducts.com>
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12a9ff3b0d
commit
837f07a301
3 changed files with 37 additions and 16 deletions
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@ -147,7 +147,8 @@ static const u32_t table_samp_time[] = {
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SMP_TIME(79, S_5),
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SMP_TIME(160, S_5),
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};
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#elif defined(CONFIG_SOC_SERIES_STM32L4X)
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#elif defined(CONFIG_SOC_SERIES_STM32L4X) || \
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defined(CONFIG_SOC_SERIES_STM32WBX)
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static const u16_t acq_time_tbl[8] = {3, 7, 13, 25, 48, 93, 248, 641};
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static const u32_t table_samp_time[] = {
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SMP_TIME(2, S_5),
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@ -216,7 +217,8 @@ static void adc_stm32_start_conversion(struct device *dev)
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#if defined(CONFIG_SOC_SERIES_STM32F0X) || \
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defined(CONFIG_SOC_SERIES_STM32F3X) || \
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defined(CONFIG_SOC_SERIES_STM32L0X) || \
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defined(CONFIG_SOC_SERIES_STM32L4X)
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defined(CONFIG_SOC_SERIES_STM32L4X) || \
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defined(CONFIG_SOC_SERIES_STM32WBX)
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LL_ADC_REG_StartConversion(adc);
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#else
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LL_ADC_REG_StartConversionSWStart(adc);
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@ -279,7 +281,8 @@ static int start_read(struct device *dev, const struct adc_sequence *sequence)
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#if defined(CONFIG_SOC_SERIES_STM32F0X) || \
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defined(CONFIG_SOC_SERIES_STM32F3X) || \
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defined(CONFIG_SOC_SERIES_STM32L0X) || \
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defined(CONFIG_SOC_SERIES_STM32L4X)
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defined(CONFIG_SOC_SERIES_STM32L4X) || \
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defined(CONFIG_SOC_SERIES_STM32WBX)
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LL_ADC_EnableIT_EOC(adc);
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#elif defined(CONFIG_SOC_SERIES_STM32F1X)
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LL_ADC_EnableIT_EOS(adc);
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@ -454,7 +457,8 @@ static void adc_stm32_calib(struct device *dev)
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ADC_TypeDef *adc = config->base;
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#if defined(CONFIG_SOC_SERIES_STM32F3X) || \
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defined(CONFIG_SOC_SERIES_STM32L4X)
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defined(CONFIG_SOC_SERIES_STM32L4X) || \
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defined(CONFIG_SOC_SERIES_STM32WBX)
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LL_ADC_StartCalibration(adc, LL_ADC_SINGLE_ENDED);
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#elif defined(CONFIG_SOC_SERIES_STM32F0X) || \
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defined(CONFIG_SOC_SERIES_STM32L0X)
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@ -491,20 +495,22 @@ static int adc_stm32_init(struct device *dev)
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return -EIO;
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}
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#if defined(CONFIG_SOC_SERIES_STM32L4X)
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#if defined(CONFIG_SOC_SERIES_STM32L4X) || \
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defined(CONFIG_SOC_SERIES_STM32WBX)
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/*
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* L4 series STM32 needs to be awaken from deep sleep mode, and restore
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* its calibration parameters if there are some previously stored
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* calibration parameters.
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* L4 and WB series STM32 needs to be awaken from deep sleep mode, and
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* restore its calibration parameters if there are some previously
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* stored calibration parameters.
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*/
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LL_ADC_DisableDeepPowerDown(adc);
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#endif
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/*
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* F3 and L4 ADC modules need some time to be stabilized before
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* F3, L4, and WB ADC modules need some time to be stabilized before
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* performing any enable or calibration actions.
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*/
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#if defined(CONFIG_SOC_SERIES_STM32F3X) || \
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defined(CONFIG_SOC_SERIES_STM32L4X)
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defined(CONFIG_SOC_SERIES_STM32L4X) || \
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defined(CONFIG_SOC_SERIES_STM32WBX)
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LL_ADC_EnableInternalRegulator(adc);
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k_busy_wait(LL_ADC_DELAY_INTERNAL_REGUL_STAB_US);
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#endif
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@ -513,7 +519,8 @@ static int adc_stm32_init(struct device *dev)
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defined(CONFIG_SOC_SERIES_STM32L0X)
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LL_ADC_SetClock(adc, LL_ADC_CLOCK_SYNC_PCLK_DIV4);
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#elif defined(CONFIG_SOC_SERIES_STM32F3X) || \
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defined(CONFIG_SOC_SERIES_STM32L4X)
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defined(CONFIG_SOC_SERIES_STM32L4X) || \
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defined(CONFIG_SOC_SERIES_STM32WBX)
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LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(),
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LL_ADC_CLOCK_SYNC_PCLK_DIV4);
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#endif
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@ -530,7 +537,8 @@ static int adc_stm32_init(struct device *dev)
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#endif
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#if defined(CONFIG_SOC_SERIES_STM32F0X) || \
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defined(CONFIG_SOC_SERIES_STM32L0X)
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defined(CONFIG_SOC_SERIES_STM32L0X) || \
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defined(CONFIG_SOC_SERIES_STM32WBX)
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if (LL_ADC_IsActiveFlag_ADRDY(adc)) {
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LL_ADC_ClearFlag_ADRDY(adc);
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}
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@ -545,7 +553,8 @@ static int adc_stm32_init(struct device *dev)
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#if defined(CONFIG_SOC_SERIES_STM32F0X) || \
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defined(CONFIG_SOC_SERIES_STM32F3X) || \
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defined(CONFIG_SOC_SERIES_STM32L0X) || \
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defined(CONFIG_SOC_SERIES_STM32L4X)
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defined(CONFIG_SOC_SERIES_STM32L4X) || \
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defined(CONFIG_SOC_SERIES_STM32WBX)
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/*
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* ADC modules on these series have to wait for some cycles to be
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* enabled.
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@ -566,10 +575,11 @@ static int adc_stm32_init(struct device *dev)
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LL_ADC_Enable(adc);
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#ifdef CONFIG_SOC_SERIES_STM32L4X
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#if defined(CONFIG_SOC_SERIES_STM32L4X) || \
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defined(CONFIG_SOC_SERIES_STM32WBX)
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/*
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* Enabling ADC modules in L4 series may fail if they are still not
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* stabilized, this will wait for a short time to ensure ADC modules
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* Enabling ADC modules in L4 and WB series may fail if they are still
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* not stabilized, this will wait for a short time to ensure ADC modules
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* are properly enabled.
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*/
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u32_t countTimeout = 0;
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@ -148,4 +148,11 @@
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#define DT_TIM_STM32_17_CLOCK_BITS DT_ST_STM32_TIMERS_40014800_CLOCK_BITS
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#define DT_TIM_STM32_17_CLOCK_BUS DT_ST_STM32_TIMERS_40014800_CLOCK_BUS
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#define DT_ADC_1_BASE_ADDRESS DT_ST_STM32_ADC_50040000_BASE_ADDRESS
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#define DT_ADC_1_IRQ DT_ST_STM32_ADC_50040000_IRQ_0
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#define DT_ADC_1_IRQ_PRI DT_ST_STM32_ADC_50040000_IRQ_0_PRIORITY
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#define DT_ADC_1_NAME DT_ST_STM32_ADC_50040000_LABEL
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#define DT_ADC_1_CLOCK_BITS DT_ST_STM32_ADC_50040000_CLOCK_BITS_0
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#define DT_ADC_1_CLOCK_BUS DT_ST_STM32_ADC_50040000_CLOCK_BUS_0
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/* End of SoC Level DTS fixup file */
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@ -61,6 +61,10 @@
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#include <stm32wbxx_ll_spi.h>
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#endif /* CONFIG_SPI_STM32 */
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#ifdef CONFIG_ADC_STM32
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#include <stm32wbxx_ll_adc.h>
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#endif
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#endif /* !_ASMLANGUAGE */
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#endif /* _STM32WBX_SOC_H_ */
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