Commit graph

2589 commits

Author SHA1 Message Date
Chay Guo
a4c9e13ea8 boards: arm: Enable flash for storage on mimxrt595_evk
- The MX25UM51345G flash is connected to FLEXSPI PortA for
  mimxrt595_evk.
- Updated flexspi_mx25um51345g driver to support DTR OPI mode.
- Tested with tests/drivers/flash.

Signed-off-by: Chay Guo <changyi.guo@nxp.com>
2022-06-13 12:10:57 +02:00
Chay Guo
c846537820 boards: arm: Add wdog support on mimxrt595_evk
Add watchdog support to the mimxrt595 platform.
The mimxrt595 platform is excluded from the watchdog
test case because the test case uses variables in the
noinit section that need to be retained through a reset
but the rt595 does not retain this memory through a
reset.

Signed-off-by: Chay Guo <changyi.guo@nxp.com>
2022-06-13 12:10:57 +02:00
Chay Guo
fdca36e1cc boards: arm: mimxrt595: Add CTimer driver for mimxrt595_evk
Add counter support using CTimer for RT595.
Tested with samples/drivers/counter/alarm.

Signed-off-by: Chay Guo <changyi.guo@nxp.com>
2022-06-13 12:10:57 +02:00
Chay Guo
77a0bc2135 boards: mimxrt595: Add SPI support
Enable access to the HS_SPI pins(JP26) on the mimxrt595_evk board.
Using DMA mode, tested with spi_loopback testcase.

Signed-off-by: Chay Guo <changyi.guo@nxp.com>
2022-06-13 12:10:57 +02:00
Chay Guo
705ab550d1 boards: arm: Added DMA support on MIMXRT595-EVK
Added DMA driver support.
Tested with tests/drivers/dma/loop_transfer

Signed-off-by: Chay Guo <changyi.guo@nxp.com>
2022-06-13 12:10:57 +02:00
Chay Guo
0d64506130 boards: Add I2C and sensor driver support on MIMXRT595-EVK
Enable I2C access to FXOS7000 sensor on the mixrt595_evk board
Tested using samples/sensor/fxos8700 for mimxrt595_evk_cm33.

Signed-off-by: Chay Guo <changyi.guo@nxp.com>
2022-06-13 12:10:57 +02:00
Bartosz Bilas
bc853b8960 soc: select HAS_MCUX_ADC_ETC for MIMXRT1062
Select HAS_MCUX_ADC_ETC Kconfig symbol for MIMXRT1062,
since the ADC External Trigger Control eripheral is present
on this SOC.

Signed-off-by: Bartosz Bilas <bartosz.bilas@hotmail.com>
2022-06-10 09:48:50 +02:00
Chay Guo
191f93c325 boards: Add analog comparator support on MIMXRT1170 EVK
Updated mcux_acmp sample to support discrete mode config.
Add ACMP support on MIMXRT1170 EVK.

Signed-off-by: Chay Guo <changyi.guo@nxp.com>
2022-06-09 11:30:49 +02:00
Dylan Hung
8b7ec919c8 soc: arm: aspeed: enable cache for AST10x0 series SOC
Enable cache for AST10x0 series SOC in platform initialization.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
2022-06-05 14:28:50 +02:00
Dylan Hung
1c3810ded2 soc: arm: select CACHE_ASPEED for Aspeed AST10x0 series SOC
Select CACHE_ASPEED to enable Aspeed cache driver for AST10x0 series
SOC.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
2022-06-05 14:28:50 +02:00
Dylan Hung
7d9f8adbeb soc: arm: select SYSCON for Aspeed AST10x0 series SOC
Aspeed AST10x0 series SOC has a SYSCON hardware block at address
0x7e6e2000.  Enable this option to enable relative driver.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
2022-06-05 14:28:50 +02:00
Jay Vasanth
de5296203a soc: pm: Microchip MEC172x SoC based power management
Add support for SoC power management for Microchip MEC172x.

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2022-06-05 14:28:25 +02:00
Nickolas Lapp
b425627629 RT10xx Power Management: Enable RT1060 Soft Off Mode and Fixup PM API
This PR adds a soft off mode to the RT10xx Power Management API.
Additionally, it corrects the PM API function in rt10xx_power.c to
use the correct function prototype to be properly overridden.

Signed-off-by: Nickolas Lapp <nickolaslapp@gmail.com>
2022-06-05 14:16:43 +02:00
Erwan Gouriou
af4a044e6f soc: stm32wb: Move MB_MEM2 linker section to SRAM1
There was a confusion on MB_MEMx definitions. Both MB_MEM1/2
should be located in SRAM1. Fix this.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2022-05-27 17:46:49 -07:00
Fabio Baltieri
e24314f10f include: add more missing zephyr/ prefixes
Adds few missing zephyr/ prefixes to leftover #include statements that
either got added recently or were using double quote format.

Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
2022-05-27 15:20:27 -07:00
Gerson Fernando Budke
5b7734c926 drivers: adc: sam0: Fix adc_reference implementation
The current sam0 adc driver not implement correctly the adc_reference
enum values. This try homonize adc input referece by tracking VDDANA
at ADC_REF_VDD_1. The ADC_REF_VDD_1_2 were fixed with correct INTVCCx
channel selection.

Fixes #45443

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2022-05-25 13:36:10 -07:00
Francois Ramu
39c8ba32ff soc: arm: stm32f7 soc without Dcache
The stm32f7 (like stm32H7) should be able to disable
the Dcache when using the DMA. This is to avoid any
pb of cache coherency on the DMA buffers.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2022-05-25 11:38:05 -07:00
Stephanos Ioannidis
b2c8f26e34 soc: npcx: scripts: Initialise Colorama during module load
This commit adds a call to the Colorama initialisation function during
the module execution so that ANSI color sequences are properly
converted to the relevant Win32 API calls on the Windows.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2022-05-24 09:00:16 -07:00
Lukasz Majewski
0f9c8c2935 arm: stm32h7: Enable DCache when CONFIG_DCACHE is defined
Up till now the usage of CONFIG_NOCACHE_MEMORY also explicitly disables
data cache on the STM32H7 SoC.

With this change the usage of CONFIG_NOCACHE_MEMORY has been decoupled
from data cache enabling as new Kconfig option - namely
CONFIG_DCACHE is now used to explicitly enable it.

After this change it would be possible to use data cache on STM32H7
with DMA buffers, fragile to cache coherency issues, defined with
'__nocache' attribute.

Such approach would improve the overall STM32H7 performance until the
moment when proper (i.e. in-DMA) buffer cache management is developed.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2022-05-24 08:47:20 -07:00
Mulin Chao
0f18c4c4ab pinctrl: npcx: config pwm open-drain without enabling STORE_REG
Config pwm open-drain mode without enabling STORE_REG. This CL
collects all active PWM's base address and related index in an
array. Then, pinctrl driver configs its open-drain mode by
finding the corresponding 'channel' index.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2022-05-20 12:36:22 +02:00
Jose Alberto Meza
4e443dac34 soc: arm: microchip: mec172x: Enclose macro in brackets
Macro should be in brackets.

Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
2022-05-20 12:35:37 +02:00
Krzysztof Chruscinski
99fb57652a soc: arm: nordic: Change tick rate for non-tickless kernel
Set SYS_CLOCK_TICKS_PER_SEC to 128 for non-tickless kernel.
Previously it was set to 32768 disregarding kernel mode and that
lead to too frequent interrupts in non-tickless mode (tick every
30 us). Change to smaller value.

Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
2022-05-19 11:03:50 +02:00
Henrik Brix Andersen
a195f98265 soc: arm: gigadevice: undefine CAN_MODE_NORMAL
The GigaDevice HAL defines CAN_MODE_NORMAL, which conflicts with the
zephyr/drivers/can.h header definition. Undefine it in soc.h.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2022-05-16 12:56:50 +02:00
Nazar Palamar
5a99e93d69 soc: arm: cypress: Update PSoC 6 implementation to use mtb-pdl-cat1
Updated PSoC 6 implementation to use hal_infineon/mtb-pdl-cat1

This PR is reflected changes according to Task#1 for RFC#42883.

Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
2022-05-13 21:34:59 +02:00
Thomas Altenbach
cc51031445 drivers/entropy: stm32: fix inter-core race condition
On STM32WB and dual-core STM32H7 MCUs, the RNG peripheral is shared
between the cores and its access is protected by a hardware semaphore.
Locking was not performed in the current entropy driver, leading to a
race condition when multiple cores concurrently used the RNG. This
commit implements the necessary logic for locking the HSEM during entropy
generation on multi-core STM32 MCUs. It also reconfigures the RNG in case
the configuration was changed by the other core, as this can happen e.g
on STM32WB MCUs.

Signed-off-by: Thomas Altenbach <taltenbach@witekio.com>
2022-05-13 10:28:53 -05:00
Daniel DeGrasse
dea2e642b2 soc: mimx8ml8_m7: add pin control support for mimx8ml8_m7
Add pin control support for IOMUXC peripheral present
on mimx8ml8_m7 soc. This reuses the existing pin
control driver for the IOMUXC peripheral, but uses a
new header and compatible binding to handle the
different register layout on this SOC.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-05-12 16:57:17 -05:00
Daniel DeGrasse
e1ef51ce39 soc: mimx8mm6_m4: add pin control support.
Add pin control support for mimx8mm6_m4 IOMUXC peripheral.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-05-12 16:57:17 -05:00
Daniel DeGrasse
e3b4c0b314 soc: mimx8mq6_m4: add pin control support
Add pin control support for IOMUXC peripheral present
on mimx8mq6_m4 soc. This reuses the existing pin
control driver for the IOMUXC peripheral, but uses a
new header and compatible binding to handle the
different register layout on this SOC.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-05-12 16:57:17 -05:00
Daniel DeGrasse
5d374d7b29 soc: mcimx7_m4: add pin control support
Add pin control support for mcimx7_m4 SOC. This reuses the existing pin
control driver for the IOMUXC peripheral, but uses a new header and
compatible binding to handle the different register layout on this SOC.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-05-12 16:57:17 -05:00
Daniel DeGrasse
e5fd7d8e67 soc: mcimx6x_m4 add pin control support
Add pin control support for mcimx6x. The IOMUXC peripheral present on
this SOC is identical to the one used on the iMX RT10xx series, so the
dts bindings are reused.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-05-12 16:57:17 -05:00
Daniel DeGrasse
bc841e1fb7 drivers: pinctrl: refactor pin control support for imx rt
Refactor iMX RT pin control support to use more generic names, as the
IOMUXC peripheral is present on non RT iMX application cores.
Additionally, make selection of the pin control driver occur at the SOC
level.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-05-12 16:57:17 -05:00
Mulin Chao
d53d574bf0 drivers: pinctrl: npcx: add initial pin-controller driver
This CL is the initial version for npcx pinctrl driver and introduces
pinctrl nodes for both IO-pads and peripheral devices for each npcx
series. Users can set pin configuration via these nodes in the board
layout DT file. It also wraps all configurations related to pin-muxing
in pinctrl_soc.h. Regarding the other pin properties, we will implement
them later.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2022-05-12 14:24:03 -05:00
Mahesh Mahadevan
14ed412359 soc: rt: Add MIPI support for MXRT1170
Add MIPI support for NXP's MXRT1170

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2022-05-12 09:26:50 -05:00
Gerard Marull-Paretas
9678bd6970 pinctrl: nrf: prefix custom drive-mode property
The drive-mode property is nRF specific, so prefix it with `nordic,`,
same as the `nordic,invert` property.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-12 09:22:12 +02:00
Jun Lin
51978d9d61 driver: eSPI: npcx: workaround the errata rev1_2, No.3.10
Enabling an eSPI channel (r.g. Peripheral Channel, Virtual Wire Channel,
etc.) during an eSPI transaction might (with low probability) cause the
eSPI_SIF module to transition to a wrong state and therefore response
with FATAL_ERROR on an incoming transaction.
This CL workarounds this issue by clearing the bit 4 of NPCX eSPI
specific register#2.

Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
2022-05-12 09:21:24 +02:00
Henrik Brix Andersen
3f97d11afd drivers: can: convert enum can_mode to a bit field
Convert the can_mode enum to a bit field to prepare for future extensions
(CAN-FD mode, transmitter delay compensation, one-shot mode, 3-samples
mode, ...).

Rename the existing modes:
- CAN_NORMAL_MODE   -> CAN_MODE_NORMAL
- CAN_SILENT_MODE   -> CAN_MODE_LISTENONLY
- CAN_LOOPBACK_MODE -> CAN_MODE_LOOPBACK

These mode names align with the Linux naming for CAN control modes.

The old CAN_SILENT_LOOPBACK_MODE can be set with the bitmask
(CAN_MODE_LISTENONLY | CAN_MODE_LOOPBACK).

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2022-05-11 10:47:54 +02:00
Georgij Cernysiov
827343a3da soc: stm32: h7: add support for stm32h730xx
Adds support for STM32H730XX SoC.

Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
2022-05-11 10:47:43 +02:00
Daniel DeGrasse
fed6d6b754 soc: lpc11u6x: enable pin control
Enable pin control for lpc11u6x soc by selecting CONFIG_PINCTRL=y.
At this time no drivers are ported.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-05-10 17:27:44 -05:00
Daniel DeGrasse
dc4d168952 soc: lpc11u6x: add pin control header
add pin control header to enable pin control support for lpc11u6x

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-05-10 17:27:44 -05:00
Daniel DeGrasse
ea9df42b25 soc: lpc11u6x: add pin control definitions to LPC11u6x soc file
add pin control definitions to LPC11u6x soc file, to handle the lack of
a HAL for this SOC.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-05-10 17:27:44 -05:00
Esteban Valverde
11ba0802b5 soc: arm: Add Cyclone V SoC FPGA Support
soc: arm: privilege: add Cyclone V SoC FPGA suppport
Add support for the Intel Cyclone V SoC FPGA (arm Cortex-A9).

Signed-off-by: Esteban Valverde <esteban.valverde.vega@intel.com>
2022-05-10 13:29:47 -04:00
Andrzej Głąbek
e7b389ddf5 dts: nordic: Add missing qdec0 node labels
This is a follow-up to commit 586e26e8fc.

Add missing `qdec0` node labels in definitions of SoCs that have only
one QDEC instance so that the `HAS_HW_NRF_QDEC0` option is properly set
for them. Use the same pattern as in the WDT case and keep the existing
`qdec` labels for backward compatibility.
Also update validation of base addresses so that both QDEC0/QDEC and
QDEC1 are checked.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2022-05-10 18:41:14 +02:00
Bernardo Perez Priego
2fc78a9b39 drivers: adc: Add threshold_reg_offset to NPCX adc config structure
ADC threshold control register offset is provided by devicetree, this
change will add this property into `adc_npcx_config` structure and
update macro to access register accordingly. Driver behavior is not
meant to be impacted.

Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
2022-05-10 18:40:24 +02:00
Piotr Dymacz
15b22e066f soc: arm: cc13x2_cc26x2: Kconfig: select CPU_HAS_ARM_MPU
This adds missing 'CPU_HAS_ARM_MPU' for Texas Instruments SimpleLink
CC13x2 and CC26x2 SoC series.

Signed-off-by: Piotr Dymacz <pepe2k@gmail.com>
2022-05-10 18:33:50 +02:00
Flavio Ceolin
99be4358af soc: nxmp: rt10xx: Fix pm callbacks
The pm hooks for this target were not updated to follow the current API.
These weak functions will never be called for the pm subsystem.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2022-05-10 09:44:17 -05:00
Gerard Marull-Paretas
4b91c2d79f asm: update files with <zephyr/...> include prefix
Assembler files were not migrated with the new <zephyr/...> prefix.
Note that the conversion has been scripted, refer to #45388 for more
details.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-09 12:45:29 -04:00
Gerard Marull-Paretas
d342e4c4c1 linker: update files with <zephyr/...> include prefix
Linker files were not migrated with the new <zephyr/...> prefix.  Note
that the conversion has been scripted, refer to #45388 for more details.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-09 12:45:29 -04:00
Henrik Brix Andersen
03bece0b70 soc: arm: atmel: samv71: enable the UPLL clock
Enable the UTMI PLL (UPLL) clock and add a static definition of its clock
frequency.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Co-authored-by: Gerson Fernando Budke <nandojve@gmail.com>
2022-05-09 09:27:40 +02:00
Henrik Brix Andersen
f0fc59f0a2 soc: arm: atmel: same70: enable the UPLL clock
Enable the UTMI PLL (UPLL) clock and add a static definition of its clock
frequency.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Co-authored-by: Gerson Fernando Budke <nandojve@gmail.com>
2022-05-09 09:27:40 +02:00
Gerard Marull-Paretas
0e69129fb3 soc: migrate includes to <zephyr/...>
In order to bring consistency in-tree, migrate all soc code to the
new prefix <zephyr/...>. Note that the conversion has been scripted,
refer to zephyrproject-rtos#45388 for more details.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-06 19:57:59 +02:00