Convert the can_mode enum to a bit field to prepare for future extensions
(CAN-FD mode, transmitter delay compensation, one-shot mode, 3-samples
mode, ...).
Rename the existing modes:
- CAN_NORMAL_MODE -> CAN_MODE_NORMAL
- CAN_SILENT_MODE -> CAN_MODE_LISTENONLY
- CAN_LOOPBACK_MODE -> CAN_MODE_LOOPBACK
These mode names align with the Linux naming for CAN control modes.
The old CAN_SILENT_LOOPBACK_MODE can be set with the bitmask
(CAN_MODE_LISTENONLY | CAN_MODE_LOOPBACK).
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Enable pin control for lpc11u6x soc by selecting CONFIG_PINCTRL=y.
At this time no drivers are ported.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
soc: arm: privilege: add Cyclone V SoC FPGA suppport
Add support for the Intel Cyclone V SoC FPGA (arm Cortex-A9).
Signed-off-by: Esteban Valverde <esteban.valverde.vega@intel.com>
This is a follow-up to commit 586e26e8fc.
Add missing `qdec0` node labels in definitions of SoCs that have only
one QDEC instance so that the `HAS_HW_NRF_QDEC0` option is properly set
for them. Use the same pattern as in the WDT case and keep the existing
`qdec` labels for backward compatibility.
Also update validation of base addresses so that both QDEC0/QDEC and
QDEC1 are checked.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
ADC threshold control register offset is provided by devicetree, this
change will add this property into `adc_npcx_config` structure and
update macro to access register accordingly. Driver behavior is not
meant to be impacted.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
The pm hooks for this target were not updated to follow the current API.
These weak functions will never be called for the pm subsystem.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Assembler files were not migrated with the new <zephyr/...> prefix.
Note that the conversion has been scripted, refer to #45388 for more
details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Linker files were not migrated with the new <zephyr/...> prefix. Note
that the conversion has been scripted, refer to #45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Enable the UTMI PLL (UPLL) clock and add a static definition of its clock
frequency.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Co-authored-by: Gerson Fernando Budke <nandojve@gmail.com>
Enable the UTMI PLL (UPLL) clock and add a static definition of its clock
frequency.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Co-authored-by: Gerson Fernando Budke <nandojve@gmail.com>
In order to bring consistency in-tree, migrate all soc code to the
new prefix <zephyr/...>. Note that the conversion has been scripted,
refer to zephyrproject-rtos#45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
This reverts commit 91d4b7766c.
Zephyr SDK 0.14.1 now includes QEMU 6.2, which supports the emulation
of the MVE instructions.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Update the Microchip XEC PS2 driver to support MEC172x.
NOTE: MEC15xx has two PS2 controllers and
MEC172x has one.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
add pincontrol headers for IOCON peripheral present on NXP iMX RT600
and RT500 SOCs, and update LPC pin control driver for iMX RT family
differences.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
added support for NXP iMX RT600/RT500 to use to SDHC driver, with SD
subsystem. Tested with RT685 EVK
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Enable new USDHC driver for all RT10xx boards, since those will have
the SDHC driver selected by Kconfig
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
In c5b59282d6, Kconfig option
CPU_CORTEX_M_HAS_CACHE was added only to a subset of stm32h7 soc
descriptions.
There is no reason not to extend to all socs as they all actually
feature a cache.
Fixes#45073
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
We no longer need to relocate the SDK power management
source file to SRAM. Instead specific functions from the
SDK file are relocated to the ramfunc section.
This commit fixes Issue#44670
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
If a Zephyr binary is booted on the Zynq-7000 not via JTAG download,
but via u-boot's ELF boot function instead, Zephyr will have to revert
certain changes made by u-boot in order to boot properly:
- clear the ICache/DCache enable, branch prediction enable and
strict alignment enforcement enable bits in the SCTLR register.
By default, u-boot will also set up the MMU prior to Zephyr
doing so as well, this can be avoided by changing the u-boot
build configuration. Therefore, the MMU enable bit is not changed
at this point.
- set the VBAR register to 0. U-boot moves the interrupt vector
table to a non-standard location using the VBAR register (no
change is made by u-boot for SCTLR.V, only VBAR is changed
to a non-zero memory location).
Without these changes, Zephyr will crash upon the first context
switch at latest, when SVC is invoked and u-boot's vector table
is used rather than the vectors copied to address zero by Zephyr.
In order to perform these changes before coming anwhere near the
MMU / device driver / kernel initialization stages or even the
first context switch, the z_arm_platform_init hook is used, which
is now enabled for the Zynq via the Kconfig.defconfig file.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
pin control definitions present for LPC55xx are not generic to all LPC
IOCON controllers. Make pin control header file LPC55xx specific.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
all the consumers of the obsolete pinmux driver is
updated to use pinctrl API, this commit removes
the pinmux driver and assosciated sections.
Signed-off-by: Vaishnav Achath <vaishnav@beagleboard.org>
Add pinctrl driver for CC13XX/CC26XX family of SoCs
to facilitate transition from pinmux to pinctrl.
`IOCPortConfigureSet()` from TI hal driverlib used to
implement the generic pinctrl driver.
Signed-off-by: Vaishnav Achath <vaishnav@beagleboard.org>
The Cache is an optional configuration of both the ARM Cortex-M7 and
Cortex-M55. Previously, it was just checking that it was just an M7
rather than knowing that the CPU actually was built with the cache.
Signed-off-by: Ryan McClelland <ryanmcclelland@fb.com>
Zephyr kernel will always execute WFI in k_cpu_idle(), so access to TCM
will be gated. Keep the AHB clock enabled in sleep unless CONFIG_PM is
selected, to avoid this error.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add MPU REGION_FLASH_SIZE definitions for 128M-512M flash sizes, to handle
arm SOCs with large flash regions.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
When we use a third-party or custom bootloader, there is also
need to remove the boot header. Change the select to imply,
so that the boot header can be removed by configuration when
MCUBoot is not used.
Signed-off-by: Frank Li <lgl88911@163.com>
DBGMCU register, which is used for SWO pin configuration,
may not have TRACE_MODE bits in some STM32 MCUs.
Replace register access with LL functions selected based on SoC family.
Fixes#44584
Signed-off-by: Alexander Vasiliev <alex.m.vasil@gmail.com>
Due to a wide range of variuation in the LSI RC oscillator
characteristics given by the datasheet of the soc,
It is necessary to add a delay for hardware watchdog.
This is done by the CONFIG_TASK_WDT_HW_FALLBACK_DELAY
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add soc_secure_mem_read implementation for secure.
This simplifies users code so that ifdefs are not required.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
The limitation on HWINFO_NRF depending on not nonsecure was removed in
52be3030aa.
This caused problems when TF-M was not enabled.
This happens on the thingy53_nrf5340_cpuapp_ns board since this board
is not supported by TF-M.
Introduce proper dependency handling for the soc secure functions
to make HWINFO_NRF unavailable when no secure services exist in
nonsecure.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
Add pinctrl definition header, to parse pinctrl groups in board level
DTS into pinctrl_soc_pin_t values.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The autoconf.h header is not required because the definitions present in
the file are exposed using the compiler `-imacros` flag.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
