Commit graph

2589 commits

Author SHA1 Message Date
Kumar Gala
5c57a36f9d i2c: remove Kconfig.defconfig setting of I2C drivers
Now that I2C drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.

Typically the Kconfig.defconfig* will blindly enable a
sensor and not respect the devicetree state of the I2C.
Additionally we can get problems with prj.conf/defconfig
getting incorrectly overridden.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-08-01 18:01:44 +02:00
Jay Vasanth
3e0f738cb2 mec15xx: pinctrl for both mec15xx and mec17xx
Changes to compile pinctrl driver for both mec15xx
and mec17xx. Also add mec15xx pinctrl dtsi

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2022-08-01 10:28:23 +02:00
Kumar Gala
5b9e0b615c clock_control: remove Kconfig.defconfig setting of clk control drivers
Now that clock control drivers are enabled based on devicetree we
need to remove any cases of them getting enabled by Kconfig.defconfig*
files as this can lead to errors.

Typically the Kconfig.defconfig* will blindly enable a sensor and not
respect the devicetree state of the clock control.  Additionally we
can get problems with prj.conf/defconfig getting incorrectly overridden.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-29 14:12:12 +02:00
Jun Lin
ec4f700202 driver: PECI: npcx: add driver support for Nuvoton npcx family
This commit add the PECI driver for Nuvoton npcx family to support PECI
APIs.

Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
2022-07-29 14:09:17 +02:00
Kumar Gala
65e1c6fb1e pwm: remove Kconfig.defconfig setting of PWM drivers
Now that PWM drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.

Typically the Kconfig.defconfig* will blindly enable a
sensor and not respect the devicetree state of the PWM.
Additionally we can get problems with prj.conf/defconfig
getting incorrectly overridden.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-27 18:43:54 +02:00
Kumar Gala
960f2f1a37 spi: remove Kconfig.defconfig setting of SPI drivers
Now that SPI drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.

Typically the Kconfig.defconfig* will blindly enable a
sensor and not respect the devicetree state of the SPI.
Additionally we can get problems with prj.conf/defconfig
getting incorrectly overridden.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-27 09:49:00 +02:00
Kumar Gala
9a501e0922 serial: remove Kconfig.defconfig setting of serial drivers
Now that serial drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.

Typically the Kconfig.defconfig* will blindly enable a
sensor and not respect the devicetree state of the serial.
Additionally we can get problems with prj.conf/defconfig
getting incorrectly overridden.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-26 09:29:24 -05:00
Kumar Gala
600d749cf3 gpio: remove Kconfig.defconfig setting of GPIO drivers
Now that gpio drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.

Typically the Kconfig.defconfig* will blindly enable a
sensor and not respect the devicetree state of the GPIO.
Additionally we can get problems with prj.conf/defconfig
getting incorrectly overridden.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-26 08:49:38 +02:00
HaiLong Yang
ef1ad14c78 soc: arm: fix gd32f4xx series config
This add soc check for series config, also fix a miss spelling issue.

Signed-off-by: HaiLong Yang <hailong.yang@brainco.cn>
2022-07-25 15:14:21 +02:00
Kumar Gala
df0c6d4c43 sensors: remove defconfig setting of sensor drivers
Now that sensor drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.

Typically the Kconfig.defconfig* will blindly enable a
sensor and not respect the devicetree state of the sensor.
Additionally we can get problems with prj.conf/defconfig
as well getting incorrectly overridden.

Fixes #48198

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-25 09:40:14 +02:00
Mulin Chao
8cf0feb3e2 power: npcx: add leakage-io support for better power consumption
This CL adds a DT node, 'power_leakage_io', which property,
'leak-gpios', contains GPIOs that have leakage current. In oerder to get
better power consumption, npcx power driver will disable the connections
between these io pads and input buffers before entering deep sleep.
Then, restore the connections after ec wakes up.

The users can overwrite this property at board DT file. Here is an
example:

    &power_leakage_io {
        leak-gpios = <&gpio0 0 0
                      &gpiob 1 0>;
    };

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2022-07-22 10:33:03 +02:00
Mulin Chao
9267655f42 driver: gpio: npcx: Support GPIO_VOLTAGE_1P8 flag
This CL configures low-voltage (1.8V) detection via GPIO driver with
GPIO_VOLTAGE_1P8 flag. It also adds support for this flag in
pin_get_config() function.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2022-07-22 10:33:03 +02:00
Mulin Chao
a5fee4c6de driver: scfg: npcx: cleanup low-voltage detection configuration
Cleanup npcx low-voltage (1.8V) detection configuration. It removes
unused soc utilities, macros, and DT node. We will configure this
feature by GPIO driver with GPIO_VOLTAGE_1P8 flag later.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2022-07-22 10:33:03 +02:00
Kumar Gala
2d88414c4e drivers: serial: pl011: Remove unused Kconfig symbols
The driver has be DT_INST based for a while so the Kconfig
symbols CONFIG_UART_PL011_PORT0<n> aren't used.  So lets
remove them.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-21 16:40:28 +00:00
Simon Hein
c29d0a3c4f soc: arm: comply to coding guidelines MISRA C:2012 Rule 14.4
MISRA C:2012 Rule 14.4 (The controlling expression of an if statement
and the controlling expression of an iteration-statement shall have
essentially Boolean type.)

Use `do { ... } while (false)' instead of `do { ... } while (0)'.

This commit is a subset of the original commit:
5d02614e34a86b549c7707d3d9f0984bc3a5f22a

Signed-off-by: Simon Hein <SHein@baumer.com>
2022-07-21 10:31:00 +02:00
Tomislav Milkovic
0fe2c1fe90 everywhere: Fix legacy include paths
Any project with Kconfig option CONFIG_LEGACY_INCLUDE_PATH set to n
couldn't be built because some files were missing zephyr/ prefix in
includes
Re-run the migrate_includes.py script to fix all legacy include paths

Signed-off-by: Tomislav Milkovic <milkovic@byte-lab.com>
2022-07-18 16:16:47 +00:00
Bernard Lee
5658e9e30d soc: arm: nordic_nrf: include linker sections header
Include linker sections header to move z_arm_platform_init to text
section. It is now is placed in the TEXT section.

Signed-off-by: Bernard Lee <bernard.lee@nordicsemi.no>
2022-07-18 16:11:50 +00:00
Attie Grande
7ded40de84 soc: atmel_sam0: The ADC reference is locked while enabled for SAML21
For SAML21-based parts, the REFCTRL register is locked while the ADC is
enabled. Permit some parts to declare that they need the ADC to be
disabled before modifying REFCTRL.

Signed-off-by: Attie Grande <attie.grande@argentum-systems.co.uk>
2022-07-18 10:35:46 +00:00
Attie Grande
a10b8cb1c0 soc: atmel_sam0: Add support for SAMR34 and SAMR35 parts
Implement support for SAMR34 and SAMR35 parts, tested on a SAMR34
Xplained Pro dev board. Confirmed operational peripherals: UART, GPIO,
PWM, ADC.

NOTE: The SAMR34 datasheet lists NVIC line 20 for the ADC's interrupt,
but the SAML21 datasheet gives line 22. It appears that the SAMR34 sheet
is incorrect (the ADC doesn't function with line 20), and as such, I have
also omitted the adjustments for TC4 and AC...

Signed-off-by: Attie Grande <attie.grande@argentum-systems.co.uk>
2022-07-18 10:35:46 +00:00
Attie Grande
64e4200d94 soc: atmel_sam0: Add support for SAML21 parts
Implement support for SAML21 parts, tested on a SAML21 Xplained Pro dev
board. Confirmed operational peripherals: UART, GPIO, PWM, ADC.

Signed-off-by: Attie Grande <attie.grande@argentum-systems.co.uk>
2022-07-18 10:35:46 +00:00
Mulin Chao
24fb705cdd npcx: scfg: psl: cleanup unused functions and DT files
Clean up unused psl functions in scfg.c, unused DT macros, unused psl DT
nodes and related yaml files. Currently, PSL pad configurations are made
by pinctrl mechanism. Please refer
https://issuetracker.google.com/234861079 for more detail.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2022-07-15 10:00:15 +02:00
Johann Fischer
3c971307dc arch/kernel/soc/samples: use unsigned int for irq_lock()
irq_lock() returns an unsigned integer key.
Generated by spatch using semantic patch
scripts/coccinelle/irq_lock.cocci

Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
2022-07-14 14:37:13 -05:00
Mulin Chao
3468a02f72 npcx: scfg: pinmux: cleanup unused functions and macro
Clean up unused pinmux function 'npcx_pinctrl_mux_configure()' and
related 'NPCX_DT_IO_ALT*' macro functions.

Please refer https://issuetracker.google.com/234861079 for more detail.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2022-07-13 10:38:49 +02:00
Jay Vasanth
7c88336171 soc: device_power: MEC172x: fix incorrect for loop check
fix incorrect iteration condition in MEC172x device_power.c

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2022-07-12 09:24:30 -05:00
Jeppe Odgaard
af6f975391 soc: select HAS_MCUX_SRC for MIMXRT1052
Select missing HAS_MCUX_SRC Kconfig symbol for MIMXRT1052,
that allows using NXP i.MX mcux SRC hwinfo driver.

Fixes https://github.com/zephyrproject-rtos/zephyr/issues/47025

Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
2022-07-12 10:17:38 +02:00
Pieter De Gendt
3cde5a0aaa soc: mimxrt1064: Remove unused low power header include
The included header file wasn't used.

Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
2022-07-11 17:51:18 -05:00
Pieter De Gendt
3556bf6fa9 soc: mimxrt1064: Fix low power build issue with video PLL
Fix build error if CONFIG_PM and CONFIG_INIT_VIDEO_PLL are enabled.
Added 2 missing semicolons.

Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
2022-07-11 17:51:18 -05:00
Carlo Caione
2f5fef960e sample: s2ram: Introduce S2RAM sample
Introduce a template / sample for S2RAM running on rf5340dk.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-07-11 15:26:26 +02:00
Julien Massot
08f5fb5cdb soc: arm: fvp_aemv8r_aarch32: define static mpu regions
Add static MPU regions for this SoC.
These regions will be initialized as static region during system boot.

Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
2022-07-11 11:17:02 +02:00
Francois Ramu
c1782a096e soc: arm: new stm32f412Rx device
This adds a new stm32f412Rx in the list of stm32F4 devices.
The module stm32cube/stm32f4/soc/stm32f412rx.h exists

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2022-07-08 10:49:31 +02:00
Mulin Chao
851e357aa4 pinctrl: npcx: add pinctrl support for psl pads
This CL introduces how to configure PSL (Power Switch Logic) pads
properties such as input detection mode/polarity, pin-muxing and so
on via pinctrl mechanism. It includes:

1. Add two pinctrl properties and their enums for PSL input
   detection configuration.
    psl-in-mode:
      - "level"
      - "mode"
    psl-in-pole:
      - "low-falling"
      - "high-rising"

2. Add macro functions to get PSL input detection and pin-muxing
   configurations from 'pinmux', 'psl-offset' abd 'psl-polarity'
   properties.

Here is an example to configure PSL_IN2 as the PSL detection input and
its mode and polarity.

/* A falling edge detection type for PSL_IN2 */
&psl_in2_gp00 {
	psl-in-mode = "edge";
	psl-in-pol = "low-falling";
};

A device will be introduced later which uses this pinctrl node to
configure PSL input detection settings and how to turn off VCC1 power
rail by PSL_OUT.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2022-07-07 14:12:52 +00:00
Joep Buruma
7e0fff24c7 drivers: pwm: add pwm driver for rpi_pico
Add pwm driver implementation for rpi pico family.
Adds myself as codeowner of drivers/pwm/*rpi_pico*

Signed-off-by: Joep Buruma <burumaj50@gmail.com>
2022-07-07 15:17:26 +02:00
Anas Nashif
782b083686 soc: add mising braces to single line if statements
Following zephyr's style guideline, all if statements, including single
line statements shall have braces.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-07-06 11:00:45 -04:00
Alexandre Duchesne
1561b1046f soc: arm: gigadevice: Initial support for gd32f470
add initial support for gd32f470 SoC

Signed-off-by: Alexandre Duchesne <alexandre.duchesne@rtone.fr>
2022-07-06 13:22:25 +02:00
Christian Taedcke
e71c2d1893 boards: efm32pg_stk3402a: Add minimal pwm support
With this additions samples/basic/blinky_pwm works.
LED0 is used as pwm output.

Signed-off-by: Christian Taedcke <hacking@taedcke.com>
2022-07-04 15:51:11 +02:00
Alex Sergeev
f7f35af277 soc: gd32: Add HAS_SEGGER_RTT
Enable SEGGER RTT for GigaDevice family.

Signed-off-by: Alex Sergeev <asergeev@carbonrobotics.com>
2022-07-04 09:50:35 +02:00
Kumar Gala
287acdbb9d i2c: sam0: Set driver Kconfig default based on devicetree
Change Kconfig default to be based on if the devicetree has the
atmel,i2c-sam0 driver enabled.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-01 15:05:55 -05:00
Kumar Gala
d200321767 video: mcux_csi: Set driver Kconfig default based on devicetree
Change Kconfig default to be based on if the devicetree has the
nxp,imx-csi driver enabled.

Signed-off-by: Kumar Gala <galak@kernel.org>
2022-07-01 14:56:33 -05:00
Bartosz Bilas
33a4c78699 soc: select HAS_MCUX_XBARA for MIMXRT1062
Select HAS_MCUX_XBARA Kconfig symbol for MIMXRT1062,
since the XBARA Inter-Peripheral Crossbar Switch peripheral is present
on this SOC.

Signed-off-by: Bartosz Bilas <b.bilas@grinn-global.com>
2022-07-01 16:23:11 +00:00
Jay Vasanth
e74978cc03 microchip: mec: zephyr spi image generation
Added mchp mec zephyr image generator python script. It takes
zephyr.bin as input and produces zephyr.mchp.bin.
The default behavior is to not pad to SPI flash size.
(Enable through CONFIG_MCHP_MEC_UNSIGNED_HEADER=y and
CONFIG_MCHP_MEC_HEADER_FLASH_SIZE_256K=y)

zephyr.mchp.bin is composed of:
1. First 4KB contains TAG at offset 0 and header at offset 0x100
2. Offset 0x1000 is the start of zephyr.bin which has been padded
to a multiple of 128 bytes.
3. Boot-ROM EC Info Block (128 bytes)
4. Boot-ROM Co-Signature Block (96 bytes)
5. Boot-ROM trailer (160 bytes) contains the SHA-384 digest of 2-4.

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2022-07-01 11:35:13 +02:00
Bartosz Bilas
091a54202a soc: arm: nxp_imx: rt: add new MIMXRT1062CVJ5B part number
Add missing MIMXRT1062CVJ5B SOC.

Signed-off-by: Bartosz Bilas <b.bilas@grinn-global.com>
2022-06-30 19:50:03 +00:00
Bartosz Bilas
dcf2d4d542 soc: arm: nxp_imx: rt: add new MIMXRT1062CVJ5A part number
Add missing MIMXRT1062CVJ5A SOC.

Signed-off-by: Bartosz Bilas <b.bilas@grinn-global.com>
2022-06-30 19:50:03 +00:00
Alexandre Duchesne
7109e7dc20 soc: st_stm32f7: Add stm32f750xx SoC
add initial support for STM32F750xx SoC

Signed-off-by: Alexandre Duchesne <alexandre.duchesne@rtone.fr>
2022-06-30 13:41:06 +00:00
Daniel DeGrasse
69d153cd3d soc: nxp_imx: rt: enable SWO output for iMX RT 10xx series
enable swo output for iMX RT 10xx series. SWO pinmux settings are
currently only present for the RT1060 and RT1064

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-06-28 16:02:09 -05:00
Henrik Brix Andersen
9d51d9145b soc: arm: xilinx: zynq7000: default to 1 CPU core
Default to 1 CPU core on the Xilinx Zynq-7000 SoC series since Zephyr does
not yet suppport SMP on aarch32.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2022-06-28 20:46:11 +02:00
Henrik Brix Andersen
e8df5bdf5b soc: arm: xilinx: zynq7000: add pinctrl header file
Add Xilinx Zynq-70000 pinctrl header file to define SoC specific
pinctrl_soc_t structure. This is used to store pin configurations for the
pinctrl driver.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2022-06-28 20:46:11 +02:00
Henrik Brix Andersen
982d379808 soc: arm: xilinx: zynq7000: unlock the slcr at boot
Unlock the Xilinx Zynq-7000 System Level Control Registers (SLCR) at boot
to allow write access using the generic syscon driver.

Since the generic syscon driver uses the DEVICE_MMIO_* APIs for
memory-mapped IO we can remove the dedicated SLCR MMU region.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2022-06-28 20:46:11 +02:00
Jeremy Bettis
6ede43b078 npcx: Set hex_file automatically w/ npcx hex image
When using CONFIG_NPCX_IMAGE_OUTPUT_HEX, set the hex_file
runners_yaml_props_target property, so that west flash will flash the
correct file.

Change the cmake flash rules to populate the hex_file value in the
runners.yaml file if either CONFIG_BUILD_OUTPUT_HEX is enabled or some
cmake file set the runners_yaml_props_target hex_file property.

Update the npcx9m6f_evb instructions now that the filename is implicit.

Signed-off-by: Jeremy Bettis <jbettis@google.com>
2022-06-28 11:09:35 +02:00
Bartosz Bilas
63e9fb6190 soc: select HAS_MCUX_SRC for MIMXRT1062
Select missing HAS_MCUX_SRC Kconfig symbol for MIMXRT1062,
that allows using NXP i.MX mcux SRC hwinfo driver.

Signed-off-by: Bartosz Bilas <b.bilas@grinn-global.com>
2022-06-24 12:30:11 -05:00
Aurelien Jarno
e54224ddab soc: stm32: h7: Generate MPU regions from DT nodes
Commit b91d21d32c added the possibility to define MPU regions from the
device tree, however commit c276088567 removed that possibility for H7
SoC, as it now uses a SoC specific definition of the MPU regions without
the DT-defined regions (probably because the two PRs got developped in
parallel).

Fix that by adding the macro which adds the DT-defined regions to the
STM32H7 specific file.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2022-06-20 10:27:52 +02:00