Have ov7670 and video smartdma use video interfaces binding. With
this, we can fix the chicken-egg issue in init priority and don't need
the workaround anymore.
Signed-off-by: Phi Bang Nguyen <phibang.nguyen@nxp.com>
The CH32V003 CPU is a QingKe V2A while others in the CH32V00x series
use the QingKe V2C. Prepare for adding support for the CH32V006 moving
to the more specifc qingke-v2a, moving some cases of SOC_CH32V003
actually meaning SOC_FAMILY_QINGKE_V2A.
Signed-off-by: Michael Hope <michaelh@juju.nz>
Add PM action for the NXP LCDIC driver so that we can
recover from a lower power mode where we lose the register
settings and we need to reconfigure the block.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
I3C is now a bus supported, by relying on RTIO IODEV which is supported
for all buses (I2C, I3C and SPI). Tested backwards compatibility: I2C
and I3C.
No IBI support yet.
Signed-off-by: Luis Ubieda <luisf@croxel.com>
Add clock control support for RZ/A2M
Signed-off-by: Hoang Nguyen <hoang.nguyen.jx@bp.renesas.com>
Signed-off-by: Binh Nguyen <binh.nguyen.xw@renesas.com>
Adds a dtsi file for the STM32F401XD family of devices. These devices
are closely related to the STM32F401XE family of devices but with a
reduced flash memory from 512kB to 384kB.
Signed-off-by: Ricardo Rivera-Matos <ricardo.rivera-matos@cirrus.com>
Add Bouffalo Lab serial driver. The driver uses pinctrl to configure
pins and have power management capabilities.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Add it515xx analog to digital converter driver which supports 8 channels
ch0 ~ ch7 and 12-bit resolution.
Signed-off-by: Yunshao Chiang <Yunshao.Chiang@ite.com.tw>
When GPIO17 or 16 is used as an external REF_CLK signal, the output is
enabled in eth_esp32.c This was added in PR number #65759 and then refined
in PR #74442. However this does not work for PHYs which need the REF_CLK
for MDIO communication, such as LAN8720A. In such cases phy_mii driver
tries to get the ID of such a PHY before REF_CLK is present. Therefore
in this PR I propose to move REF_CLK initialization from eth_esp32.c to
mdio_esp32.c which gets initialized before PHY and ETH.
Signed-off-by: Łukasz Iwaszkiewicz <lukasz.iwaszkiewicz@gmail.com>
Switches back to equal sized partitions, this fixes an issue
whereby the number of overhead sectors for a swap mode was
incorrectly listed as 2 when it should have been 1, and also
allows using any swap mode. This means that when using swap
using mode, 1 sector in the secondary partition will be unusable,
and when using swap using offset, 1 sector in the primary
partition will be unusable
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Enhanced uart-controller.yaml to expand parity type support,
now including 'mark' and 'space' options.
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Introduce NXP NCNano driver using MIPI DBI class. This peripheral
supports 8080 and 6800 mode. The driver also supports used with
nxp,mipi_dsi_2l driver, for the panel with DPHY bus, such as g1120b0mipi.
Signed-off-by: Kate Wang <yumeng.wang@nxp.com>
Update nxp,dcnano-lcdif to support IP change on RT700. There are extra
registers need to be configured for the lcdif on RT700. Add new binding
item "version" to tell which version of the IP the SoC has.
Signed-off-by: Kate Wang <yumeng.wang@nxp.com>
To split bus support into separate files. This patch does not introduce
any functionality, but rather precedes a patch introducing I2C bus
support.
Signed-off-by: Luis Ubieda <luisf@croxel.com>
In STM32N6, AXISRAM1 is next to the 400kB FLEXRAM.
By default, the FLEXRAM is configured to extend the AXISRAM1 which put
its total size to 1024kB.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Use the default kernel clock (HCLK5) for the XSPI instances instead of the
peripheral clock which may not be enabled at all.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Errata sheet ES0620 indicates that STM32N6 APB prescalers cannot be
modified.
Fixes the value of all APB prescalers to 1 (default value).
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
