Add support for the Renesas RA Direct Memory Access Controller,
including driver source files, Kconfig options, and DTS bindings.
- Add initial implementation of the RA DMAC driver
- Add dedicated Kconfig and CMake integration
- Provide Devicetree bindings for the RA DMAC
- Update module Kconfig to include the new driver
This enables DMA functionality on Renesas RA series MCUs.
Signed-off-by: Khanh Nguyen <khanh.nguyen.wz@bp.renesas.com>
Add stm32l083xx SoC variants that are similar to stm32l073xx with an added
AES accelerator.
Signed-off-by: Marek Maškarinec <marek.maskarinec@hardwario.com>
Change hardware cycle count (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC) to 594
MHz. Move that value to the SoC layer's DT.
Validated with the amp_blinky example - the period of the blinking LED
is exactly 2 seconds, like was programmed.
Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>
Add dts for stm32c051.
STM32C051 is just an STM32c071 w/o USB and different memory configuration.
Therefore STM32C091 can directly include STM32C051 and no longer needs
to delete the usb nodes.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Add a UART driver for the VIRTIO console device.
This driver has support for both polling- and interrupt-based i/o,
as well as interacting with up to 32 console ports (disabled by
default). Based on the Xen HVC driver.
Tested with the console subsystem sample programs. Aside from
enabling CONFIG_PCIE, setting CONFIG_HEAP_MEM_POOL_SIZE to a
high enough value (for example 100000) is necessary -- as is done
in the virtiofs sample.
Signed-off-by: Jakub Klimczak <jklimczak@internships.antmicro.com>
Add support for clock subsystem configuration and pinctrl in the
DesignWare I3C driver to enable proper clock control and pin
management on platforms that require them.
Changes include:
- Add clock_subsys field to dw_i3c_config structure.
- Update clock_control_get_rate() and clock_control_on() calls to use
the configured clock subsystem instead of NULL.
- Use COND_CODE_1 with DT_INST_PHA_HAS_CELL to conditionally extract
clock subsystem ID from devicetree, providing backward compatibility
for platforms without clkid cell.
- Include pinctrl-device.yaml in devicetree binding to enable pinctrl
support for platforms that need pin configuration.
- Gracefully fallback to NULL behavior when clkid is not specified.
This follows the same pattern used by other I3C drivers (mcux, renesas_ra)
and enables proper clock management for SoCs that require clock subsystem
identifiers while maintaining compatibility with existing devicetree
configurations.
Signed-off-by: Shreehari HK <shreehari.hk@alifsemi.com>
add range of cpu power states (run/sleep, stop and standby) for MSPM0
series. add exit latencies ranging from 1.5-15.7µs and minimum
residency times of 5-10ms for optimal power management transitions.
Signed-off-by: Sanjay Vallimanalan <sanjay@linumiz.com>
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
Extend vpr_launcher and device tree bindings to support configuring
the DMA secure attribute.
Signed-off-by: Dhanoo Surasarang <dhanoo.surasarang@nordicsemi.no>
Use both cores for Zephyr by default. I did enable SMP, however forgot
to enable PSCI to turn on the other cores in the initial PR.
Tested with samples: `tests/arch/arm64/arm64_psci/` and
`samples/arch/smp/pi`
Requires [0].
[0]: https://github.com/zephyrproject-rtos/zephyr/pull/95325
Signed-off-by: Ayush Singh <ayush@beagleboard.org>
This change makes improvements and bug fixes for the Infineon PWM
driver. These include:
* Removes hard coded register addresss from driver.
* Addresses issues causing pwm_api and pwm_gpio_loopback tests to
fail, as well as functional failures.
* Restructures device tree file to better represent the hardware
architecture of the tcpwm module.
* Allows configuration of hardware behavior when PWM is disabled.
Signed-off-by: Bill Waters <bill.waters@infineon.com>
