This commit add a system timer driver for Renesas RX using the
CMT peripheral. The driver supports both system ticks and
high-resolution cycle counting
- Configures CMT0 as the system tick timer
- Configures CMT1 as a free-running cycle timer for precise
time tracking
- Handles timer overflows to maintain a continuous cycle count.
- Implements sys_clock_cycle_get_32() and sys_clock_cycle_get_64()
for high-resolution timing
- Supports Zephyr tickless kernel mode by tracking elapsed cycles
- Enables interrupt-based tick announcement using CMT0
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Signed-off-by: Yuichi Nakada <yuichi.nakada.sx@renesas.com>
Initial support of clock control driver for RX MCU
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Signed-off-by: Tran Van Quy <quy.tran.pz@renesas.com>
The qemu-system-rx is based on RX62N, this commit added
support for the RX62N SOC layer. MCU is using RXv1 core and
system timer running at 6MHz
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Add disabled qdec subnodes to timers TIM1 through TIM5 and TIM8
for STM32F2 series MCUs. This enables Zephyr to provide consistent
QDEC support across all supported encoder-capable STM32 timers.
Signed-off-by: Amaan Singh <amaansingh160@gmail.com>
Clean up dt binding descriptions and introduce titles where
needed to make board documentation pages look nice. The supported
hardware table on board documentation pages sources its data
from dt bindings, and needs succinct titles.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Added USB device node with compatible "st,stm32-usb".
Added usb_fs_phy node with compatible "usb-nop-xceiv".
Signed-off-by: IBEN EL HADJ MESSAOUD Marwa <marwa.ibenelhadjmessaoud-ext@st.com>
K3 series is a Nuvoton embedded controller based on NPCX series.
Add npck3m8k dtsi
Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
WKUP3 is only available for g0b0/1 and g0c1 variants.
WKUP5 is only available in larger packages. However, package sizes
are currently not considered in the devicetree file schema for STM32.
Signed-off-by: Martin Jäger <martin@libre.solar>
Add driver capability to properly set high performance mode
while setting data rate (thru lis2duxxx_mode_set() API)
based on how power-mode is set into DTS: if it is set to
LIS2DUX12_OPER_MODE_HIGH_PERFORMANCE then configure HP mode,
LP/ULP mode otherwise.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
The st,stm32-xspi compatible is defining the reg property
with the register address and size at first index
followed by the external memory base address and max allocated
xspi1 is addressing max 256 MBytes from 0x90000000
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The st,stm32-xspi compatible is defining the reg property
with the register address and size at first index
followed by the external memory base address and max allocated
size. For the stm32N6 serie,
xspi1 is addressing max 256 MBytes from 0x90000000
xspi2 is addressing max 256 MBytes from 0x70000000
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Uses sub-partitions to allow having a dedicated secure and
non-secure partition area in flash partitions, which also allows
the main application slot to be extended when TF-M is not in use
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Introduces a driver for ST75256 Display Controller that
supports mono and greyscale but not i2c mode.
Signed-off-by: Camille BAUD <mail@massdriver.space>
The VS1838B is one of the most found infrared receiver
found in electronic kits and is easy to setup with only
a single GPIO used for signal transmission (apart from
VCC and GND).
This new driver let applications use the VS1838B as an
input with events relayed as 0x0000<address><command>.
Only the NEC protocol is supported in this version but
more can be added later.
Link: https://github-wiki-see.page/m/CoreELEC/remotes/wiki/08.-NEC-IR-Protocol-Datasheet
This has been tested using the input_dump sample.
Signed-off-by: Bastien JAUNY <bastien.jauny@smile.fr>
IRONside calls are remote procedure calls which comprise the runtime
interface of Nordic IRONside SE. They are realized using a simple IPC
mechanism.
A local domain (client) issues requests to the server by exchanging data
in shared memory, which is divided into evenly sized buffers. The client
selects a buffer, writes a request into it, and sends it to the server.
The server processes that request and writes a response into the same
buffer before returning it to the client.
This patch adds the initial client-side implementation on top of MBOX.
It features cache management and a blocking alloc/dispatch/release API
for synchronous, zero-copy transfers.
A new devicetree binding is added to support this implementation. It is
patterned after the `zephyr,ipc-*` bindings, where each node associates
a pair of mailboxes and a shared memory region.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Implement the functions of I2C host and target.
I2CM: supports nine hosts and each one able located at I2C interface
0~12.
supports two 32 bytes dedicated FIFO mode for read and write.
I2CS: supports three targets and each one able located at I2C
interface 0~8.
supports 16 bytes dedicated FIFO mode that only supports write or
read mode and the maximum buffer size is 256 bytes.
support non-FIFO write to shared FIFO read mode. The maximum
shared FIFO size for read is 256 bytes.
The APIs test include: i2c_write(), i2c_read(), i2c_burst_read(),
i2c_burst_write(), i2c_write_read()
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Move all the vendor-specific dtsi files that were in dts/common to a
new folder under dts/ designated for vendor-specific files,
since they are not common at all, except for one vendor.
Change MAINTAINERS.yml to reflect the moving of the files.
Update migration guide for this change.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
This commit adds a RAM lock node for both NPCX9 and NPCX4. Then, the
user can use this node to configure the RAM lock settings.
Signed-off-by: Tom Chang <CHChang19@nuvoton.com>
Add driver support for xlnx SD/EMMC host controller. The driver
currently support SD host controller version 3.0 and EMMC host
controller version 5.1. This driver functions with the SDHC subsystem to
perform operations on device.
Driver support both interrupt and polled mode data transfer. Uses ADMA2
to perform data transfer.
Signed-off-by: Paul Alvin <alvin.paulp@amd.com>
MAX32657 is Cortex-M33 based Analog Devices MCU.
It supports ARM TrustZone security model.
There will be two boards of this MCU Secure and Non-Secure
This commit defines Secure version of peripherals.
Basic feature of MAX32657 device:
- Core is Cortex-M33
- 50MHz IPO clock
- There are 54 interrupt vectors
- 1MB flash & 256 SRAM
- MAX32657 has:
- 1 x UART
- 1 x I2C/I3C
- 1 x SPI
- 6 x TIMER
- 1 x RTC
- 1 x WDT
- 1 x TRNG
Signed-off-by: Sadik Ozer <sadik.ozer@analog.com>
