Add a CPU frequency scaling subsystem, allowing a policy
algorithm to control the frequency of a given SoC/MCU
automatically at runtime.
Implement a basic, "on-demand" policy algorithm which
iterates through the P-states supported by the SoC and
selects the first P-state where it's trigger threshold is
less than the CPU load.
The CPU frequency scaling subsystem does not currently
support SMP. The CPU load measurement can be made to support
SMP since statistics are measured from the scheduler.
Co-authored-by: Eric Hay <Eric.Hay@analog.com>
Signed-off-by: Sean Kyer <Sean.Kyer@analog.com>
For all GPIO headers/connectors, add a short mention of the header file
that can be used to access pin numbers macros.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Updating standby exit latency time according worst case value
from stm32wba5 and stm32wba6 datasheets.
Signed-off-by: Alessandro Manganaro <alessandro.manganaro@st.com>
Add wsen_isds_2536030320001 driver with
the corrected name and compatibility with
the hal update as well as added new features.
Signed-off-by: Wajdi ELMuhtadi <wajdi.elmuhtadi@we-online.com>
Add mention of ARDUINO_HEADER_R3_* constants in binding description for
the Arduino Uno (R3) header.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Add a stupid binding for doc purposes. Terrible coupling when we have to
configure DT in order to generate documentation properly. At least we
get rid of one of the stupid HAS_MCUX_ kconfigs in the process.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
1.Update dts bindings to move clock-source properties from
nxp,ftm-pwm.yaml to nxp,ftm.yaml.
2.Provide counter driver based on FTM driver from NXP mcux-sdk-ng
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Define the vbatts-pins for the RA4E1, RA4M1, RA4M2, RA4M3, RA4W1
RA6E1, RA6M1, RA6M2, RA6M3, RA6M4, and RA6M5
Signed-off-by: Jeremy Dick <jdick@pivotint.com>
Splits up partition configuration for nrf5340-based cpuapp board
targets for secure and non-secure versions, the secure version now
has an extra 16KiB per slot which was previously wrongly reserved
for TF-M partitions which the secure board target does not use
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Fix CI issues whereby arch.arm.swap.common.no_optimizations test is
failing due to overlapping sections
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
There is a "native" RTC driver for DS3231 now (maxim,ds3231-rtc, one of
the multiple functions implemented as MFD) so do all we can to
discourage the use of the legacy, counter-API based, driver.
Flag the compatible as deprecated.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
The AT25XV021A variant is a flash variant of Atmel's AT25 family
that adds extra protections, requiring additional writes to the
device to program or erase data.
This commit adds a flash driver for AT25XV021A devices instead of
modifying (1) the existing AT45 SPI flash driver or (2) the
existing AT24/25 EEPROM driver because this variant poses
fundamental changes that affect all aspects of the driver.
Notably,
- AT25XV021A includes a second status register, and the format
and functions of the existing status register is
changed from the existing drivers.
- AT25XV021A requires executing page or chip erase commands
before writing, making it incompatible with the
existing AT24/25 EEPROM driver.
- AT25XV021A adds a software protection layer that requires
extra writes before executing program or erase commands.
Tested writing to and erasing from an AT25XV021A device. Tested
reading from an AT25XV021A device across page boundaries. Tested
chip erase function. Tested driver initialization from varying
initial hardware states.
Signed-off-by: Liam Ogletree <liam.ogletree@cirrus.com>
Add EM4 wakeup capable pin mapping to GPIO port node. Pins
capable of EM4 wakeup have dedicated interrupt flags.
Add EM4 as a soft-off power state that is disabled by default.
Marking it as disabled allows users to enter it with
`pm_state_force()`, while preventing the power management
subsystem from selecting the state automatically.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
There are 14 TIMG and 2 TIMA, all which can be either a counter or a pwm,
so let's fix the names to avoid ambiguity and enforce uniqueness.
Rule applied here being:
tim<g/a><n>: tim<g/a><n>@<address> {
...
counter<g/a><n>: counter<g/a><n> {
...
};
pwm<g/a><n>: pwm<g/a><n> {
...
};
};
It will be much easier then once get the 16 timer nodes included.
Signed-off-by: Tomasz Bursztyka <tobu@bang-olufsen.dk>
Those memories should be disabled by default and enabled
at application level.
Incidentally, fix the way Kconfig symbol is enabled as
we should not parse status of ramcfg, but status of enabled
memory nodes.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Remove the universal, unconditional declaration of the RAM area
at the SoC level, due to:
- the hardcoded base address 0 overlapping the exception vectors,
the ATCM and the BTCM areas.
- the availability of the BTCM not being guaranteed unconditionally
(config pin dependant)
- the possibility of having a 'black hole' between the ATCM and
the BTCM depending on the operating mode of the R-cores cluster,
which leads to a part of the text section being unavailable
- qemu not properly implementing the configuration-dependant
behaviour of the ATCM and BTCM areas.
Signed-off-by: Immo Birnbaum <mail@birnbaum.immo>
Because the EC host command with SHI/SPI backend is timing sensitive, it
required the CPU to response the SHI interrrupt as soon as possible.
This commit re-arranges the default interrupt priority by:
1. keep the SHI's interrupt priority to 1.
2. Decrease the priority of the other peripherals by 1.
(i.e. increase the priority `value` by 1)
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
When compiling, the following warning occurs:
Warning (simple_bus_reg): /soc/sai1@452005804: simple-bus unit address
format error, expected "52005804"
Looking at table 3 in the reference manual[1] for the stm32n6 it seems that
the sai1_a address simply had a typo, where a "4" was added in front of the
correct address.
Fix the typo.
[1] RM0486 Rev 2: https://www.st.com/resource/en/reference_manual/rm0486-stm32n647657xx-armbased-32bit-mcus-stmicroelectronics.pdf
Signed-off-by: Emil Dahl Juhl <emil@s16s.ai>
Add tearing effect support for better display synchronization. If
tearing effect is configured in the mipi_dbi device, the display
controller configures its tearing effect register.
Display orientation configuration is updated to also rotated the
direction of the display pixel vertical scanline, such that scan order
matches the display orientation.
Signed-off-by: Christian Rask <christianrask2@gmail.com>
Add tearing effect support for better display synchronization. This
allows users to configure an external interrupt on falling/rising edges
of the gpio connected to the display controllers tearing effect pin.
See dt-bindings/mipi_dbi/mipi_dbi.h for details of how this works for
mipi_dbi display interfaces.
Signed-off-by: Christian Rask <christianrask2@gmail.com>
Change the compatible of CPU core for qemu_rx, rx130 and rx261
target accroding to the change of dt-binding for rx cpu core
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Adding bindings for rx cpu core version and remove the redundant
compatible in the qemu_rx and rsk_rx130 boards
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
The wdog0 unit address and reg entry pointed to the secure
alias, while the SMU was configured to expect the non-secure
alias.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
