- Replace the UARTs with the ones defined in k3-am62-main.dtsi.
- Also ends up adding main prefix to the uarts.
- Adjust the board dts to use the new names.
- Since the same file is also used by m4 cores, do not add interrupt
properties, since they are different between m4 and a53
Signed-off-by: Ayush Singh <ayush@beagleboard.org>
Add support for BGM220P modules. Enable oscillators in SoC DTS
since the necessary crystals are present in the modules.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Add missing EUART0 peripheral to devicetree for xg22.
Fix NUM_IRQS, there are 64 external interrupts on xg22.
Remove `select` of UART_INTERRUPT_DRIVEN at SoC level, this doesn't
belong here, since it prevents disabling the UART. This should be a
board or application level decision.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Describe the DSI block available from STM32F767 and onward
and allow to output data generated by the LTDC to a DSI
panel.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Add initial support for interrupt generated from the axp2101. For
the time being only support for power button is added but others can
be added in the future if necessary.
Signed-off-by: Valerio Setti <vsetti@baylibre.com>
Fix dts property description of de-deassert-time for stm32-uart driver.
Old text was copy'n'pasted from de-assert-time.
Signed-off-by: Thomas Decker <decker@jb-lighting.de>
Reformat devicetree files:
* Sort nodes by unit address or name
* Sort properties by category and name
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
- Use DT_FREQ_M() and DT_FREQ_K() for DTS frequency property
for better readability.
- Include freq.h in dts to use DT_FREQ_M/K()
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
The SIUL2 external interrupt driver is a native implementation usable
across all NXP SoCs with SIUL2 IP. Remove the "S32" prefix to allow
clean reuse by other families.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
The SIUL2 GPIO driver is a native implementation usable across all
NXP SoCs with SIUL2 IP. Remove the "S32" prefix to allow clean
reuse by other families.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
The SIUL2 pin control driver is a native implementation usable across
all NXP SoCs with SIUL2 IP. Remove the "S32" prefix to allow clean
reuse by other families.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Add support for the Renesas RA Capture Engine Unit (CEU),
including driver source files, Kconfig options, and DTS bindings.
- Add initial implementation of the RA CEU driver
- Add dedicated Kconfig and CMake integration
- Provide Devicetree bindings for the RA CEU
- Update module Kconfig to include the new driver
This enables image capture functionality using the CEU peripheral
on Renesas RA series MCUs.
Signed-off-by: Duy Vo <duy.vo.xc@bp.renesas.com>
Signed-off-by: Khanh Nguyen <khanh.nguyen.wz@bp.renesas.com>
Originally the driver is selected if `HAS_MCUX_SRC_V2` is
selected in SOC level kConfig.
Change to use dts to mark the driver is avaiable for some SOC.
Signed-off-by: Jason Yu <zejiang.yu@nxp.com>
RT1160 and RT1170 have different sizes for OCRAM1 and OCRAM2 this PR moves
the static ocram1 and ocram2 labels to the soc specific dtsi and defines
their sizes according to the RM. For RT1160, it combines the OCRAM1,
OCRAM2, and OCRAM M7 (FlexRAM ECC) into 1 node for a better user
experience. 256KB total as opposed to 64KB.
Signed-off-by: Jacob Wienecke <jacob.wienecke@nxp.com>
Provide the soc configuration for fdcan1 and fdcan2 controllers.
This includes registers address, clocks and interrupt lines
details.
Signed-off-by: Thomas Decker <decker@jb-lighting.de>
Some x86_64 platforms have only one CPU node defined in their
respective devicetree files, while setting `CONFIG_MP_MAX_NUM_CPUS`
to two.
This commit adds missing CPU nodes in said devicetree files.
Signed-off-by: Adrian Ściepura <asciepura@internships.antmicro.com>
Add the Texas Instruments INA228 Power/Energy/Charge
monitor. This chip is similar to the INA237, but has
a more precise ADC and added energy/charge channels.
Signed-off-by: Wilkins White <ww@novadynamics.com>
This commit renames the ina23x folder and common files to ina2xx.
The more generic name will support, e.g., the INA237 and INA228
series chips.
Signed-off-by: Wilkins White <ww@novadynamics.com>
The uart driver for nRF54h20 doesn't call pm_device_runtime_enable().
During an uart driver init `pm_device_driver_init()` return early,
because the `pm_device_is_powered()` returns `false`. Power domains,
where uarts are instantiated, are disabled: `pm->domain->pm_base->state`
is not equal to `PM_DEVICE_STATE_ACTIVE`.
At the end of the day, an uart instance is left disabled.
This is a workaround to make the uart usable when CONFIG_PM,
CONFIG_PM_DEVICE and CONFIG_PM_DEVICE_RUNTIME are enabled.
Signed-off-by: Piotr Pryga <piotr.pryga@nordicsemi.no>
This follows change of ethos-u core driver (hal_ethos_u) which
removes cache flush/invalidate mask function ethosu_set_basep_cache_mask.
Signed-off-by: Chun-Chieh Li <ccli8@nuvoton.com>
Remove the hash node from STM32755x SoC DTSI. The node was broken
(wrong node name and compatible property) and seems unused and moreover
most STM32H7xx have an HASH peripheral so a proper fix would rather
be to add the node to all relevant SoC. This will be done later, if
the need arises and after proper validation.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Create separate memory regions for each OFS register. With a single
region the linker will gap fill the load segment with zeros between
each option setting section that gets placed in the region when
generating the .elf file.
Signed-off-by: Jeremy Dick <jdick@pivotint.com>
Introduce nordic NRFS SWEXT power domain bindings and add it to
relevant SoC devicetree files.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
