driver: flash: add flash driver for the RV32M1 SOC
Add driver and device tree for the flash controller for the RV32M1 SOC Signed-off-by: Lyle Zhu <lyle.zhu@nxp.com>
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9 changed files with 224 additions and 0 deletions
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@ -15,6 +15,7 @@ zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_SAM flash_sam.c)
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zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_NIOS2_QSPI soc_flash_nios2_qspi.c)
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zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_GECKO flash_gecko.c)
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zephyr_library_sources_ifdef(CONFIG_FLASH_NATIVE_POSIX flash_native_posix.c)
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zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_RV32M1 soc_flash_rv32m1.c)
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if(CONFIG_CLOCK_CONTROL_STM32_CUBE)
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zephyr_sources(flash_stm32.c)
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@ -69,4 +69,6 @@ source "drivers/flash/Kconfig.w25qxxdv"
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source "drivers/flash/Kconfig.simulator"
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source "drivers/flash/Kconfig.rv32m1"
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endif # FLASH
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17
drivers/flash/Kconfig.rv32m1
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17
drivers/flash/Kconfig.rv32m1
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@ -0,0 +1,17 @@
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#
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# Copyright (c) 2019 NXP
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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config SOC_FLASH_RV32M1
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bool "RV32M1 flash shim driver"
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depends on HAS_RV32M1_FTFX
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select FLASH_HAS_PAGE_LAYOUT
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select FLASH_HAS_DRIVER_ENABLED
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help
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Enables the RV32M1 flash shim driver.
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WARNING: This driver will disable the system interrupts for
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the duration of the flash erase/write operations. This will
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have an impact on the overall system performance - whether
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this is acceptable or not will depend on the use case.
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168
drivers/flash/soc_flash_rv32m1.c
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168
drivers/flash/soc_flash_rv32m1.c
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@ -0,0 +1,168 @@
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/*
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* Copyright (c) 2016 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <kernel.h>
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#include <device.h>
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#include <string.h>
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#include <flash.h>
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#include <errno.h>
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#include <init.h>
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#include <soc.h>
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#include "flash_priv.h"
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#include "fsl_common.h"
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#include "fsl_flash.h"
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#define CONFIG_FLASH_SIZE DT_FLASH_SIZE
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struct flash_priv {
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flash_config_t config;
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/*
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* HACK: flash write protection is managed in software.
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*/
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struct k_sem write_lock;
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u32_t pflash_block_base;
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};
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/*
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* Interrupt vectors could be executed from flash hence the need for locking.
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* The underlying MCUX driver takes care of copying the functions to SRAM.
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*
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* For more information, see the application note below on Read-While-Write
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* http://cache.freescale.com/files/32bit/doc/app_note/AN4695.pdf
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*
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*/
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static int flash_mcux_erase(struct device *dev, off_t offset, size_t len)
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{
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struct flash_priv *priv = dev->driver_data;
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u32_t addr;
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status_t rc;
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unsigned int key;
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if (k_sem_take(&priv->write_lock, K_NO_WAIT)) {
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return -EACCES;
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}
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addr = offset + priv->pflash_block_base;
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key = irq_lock();
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rc = FLASH_Erase(&priv->config, addr, len, kFLASH_ApiEraseKey);
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irq_unlock(key);
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k_sem_give(&priv->write_lock);
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return (rc == kStatus_Success) ? 0 : -EINVAL;
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}
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static int flash_mcux_read(struct device *dev, off_t offset,
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void *data, size_t len)
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{
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struct flash_priv *priv = dev->driver_data;
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u32_t addr;
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/*
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* The MCUX supports different flash chips whose valid ranges are
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* hidden below the API: until the API export these ranges, we can not
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* do any generic validation
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*/
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addr = offset + priv->pflash_block_base;
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memcpy(data, (void *) addr, len);
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return 0;
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}
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static int flash_mcux_write(struct device *dev, off_t offset,
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const void *data, size_t len)
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{
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struct flash_priv *priv = dev->driver_data;
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u32_t addr;
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status_t rc;
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unsigned int key;
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if (k_sem_take(&priv->write_lock, K_NO_WAIT)) {
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return -EACCES;
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}
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addr = offset + priv->pflash_block_base;
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key = irq_lock();
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rc = FLASH_Program(&priv->config, addr, (uint32_t *) data, len);
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irq_unlock(key);
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k_sem_give(&priv->write_lock);
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return (rc == kStatus_Success) ? 0 : -EINVAL;
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}
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static int flash_mcux_write_protection(struct device *dev, bool enable)
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{
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struct flash_priv *priv = dev->driver_data;
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int rc = 0;
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if (enable) {
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rc = k_sem_take(&priv->write_lock, K_FOREVER);
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} else {
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k_sem_give(&priv->write_lock);
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}
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return rc;
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}
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#if defined(CONFIG_FLASH_PAGE_LAYOUT)
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static const struct flash_pages_layout dev_layout = {
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.pages_count = KB(CONFIG_FLASH_SIZE) /
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DT_SOC_NV_FLASH_0_ERASE_BLOCK_SIZE,
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.pages_size = DT_SOC_NV_FLASH_0_ERASE_BLOCK_SIZE,
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};
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static void flash_mcux_pages_layout(
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struct device *dev,
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const struct flash_pages_layout **layout,
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size_t *layout_size)
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{
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*layout = &dev_layout;
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*layout_size = 1;
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}
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#endif /* CONFIG_FLASH_PAGE_LAYOUT */
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static struct flash_priv flash_data;
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static const struct flash_driver_api flash_mcux_api = {
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.write_protection = flash_mcux_write_protection,
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.erase = flash_mcux_erase,
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.write = flash_mcux_write,
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.read = flash_mcux_read,
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#if defined(CONFIG_FLASH_PAGE_LAYOUT)
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.page_layout = flash_mcux_pages_layout,
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#endif
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.write_block_size = FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE,
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};
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static int flash_mcux_init(struct device *dev)
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{
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struct flash_priv *priv = dev->driver_data;
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u32_t pflash_block_base;
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status_t rc;
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CLOCK_EnableClock(kCLOCK_Mscm);
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k_sem_init(&priv->write_lock, 0, 1);
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rc = FLASH_Init(&priv->config);
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FLASH_GetProperty(&priv->config, kFLASH_PropertyPflashBlockBaseAddr,
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(uint32_t *)&pflash_block_base);
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priv->pflash_block_base = (u32_t) pflash_block_base;
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return (rc == kStatus_Success) ? 0 : -EIO;
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}
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DEVICE_AND_API_INIT(flash_mcux, DT_FLASH_DEV_NAME,
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flash_mcux_init, &flash_data, NULL, POST_KERNEL,
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &flash_mcux_api);
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@ -15,3 +15,10 @@ config HAS_RV32M1_LPI2C
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bool
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help
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Set if the low power i2c (LPI2C) module is present in the SoC.
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config HAS_RV32M1_FTFX
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bool
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help
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Set if the flash memory (FTFA, FTFE, or FTFL) module is present in
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the SoC.
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@ -3,3 +3,4 @@ zephyr_include_directories(.)
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zephyr_sources(fsl_clock.c)
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zephyr_sources_ifdef(CONFIG_UART_RV32M1_LPUART fsl_lpuart.c)
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zephyr_sources_ifdef(CONFIG_I2C_RV32M1_LPI2C fsl_lpi2c.c)
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zephyr_sources_ifdef(CONFIG_SOC_FLASH_RV32M1 fsl_flash.c)
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@ -173,4 +173,14 @@ config I2C_RV32M1_LPI2C
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endif # I2C
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if FLASH
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config SOC_FLASH_RV32M1
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default y
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config FLASH_BASE_ADDRESS
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default $(dt_hex_val,DT_FLASH_BASE_ADDRESS)
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endif # FLASH
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endif # SOC_OPENISA_RV32M1_RISCV32
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@ -14,6 +14,8 @@ config SOC_OPENISA_RV32M1_RISCV32
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select VEGA_SDK_HAL
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select RISCV_SOC_INTERRUPT_INIT
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select CLOCK_CONTROL
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select HAS_RV32M1_FTFX
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select HAS_FLASH_LOAD_OFFSET
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help
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Enable support for OpenISA RV32M1 RISC-V processors. Choose
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this option to target the RI5CY or ZERO-RISCY core. This
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16
soc/riscv32/openisa_rv32m1/dts_fixup.h
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16
soc/riscv32/openisa_rv32m1/dts_fixup.h
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/*
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* Copyright (c) 2019 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* SoC level DTS fixup file */
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#if defined(CONFIG_SOC_OPENISA_RV32M1_RISCV32)
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#define DT_FLASH_DEV_BASE_ADDRESS DT_OPENISA_RV32M1_FTFE_40023000_BASE_ADDRESS
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#define DT_FLASH_DEV_NAME DT_OPENISA_RV32M1_FTFE_40023000_LABEL
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#endif /* CONFIG_SOC_OPENISA_RV32M1_RISCV32 */
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/* End of SoC Level DTS fixup file */
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