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drivers: i2c: enable I2C on STM32WB

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Enable I2C on STM32WB

Signed-off-by: Roger N'Guessan <roger.nguessan@st.com>
This commit is contained in:
Roger N'Guessan 2019-06-06 16:48:05 +02:00 • committed by Anas Nashif
commit 0a9d547cc1
5 changed files with 32 additions and 3 deletions
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4
drivers/i2c/Kconfig.stm32
View file

@ -23,13 +23,13 @@ config I2C_STM32_V1
config I2C_STM32_V2
bool
depends on SOC_SERIES_STM32F0X || SOC_SERIES_STM32F3X || SOC_SERIES_STM32F7X || SOC_SERIES_STM32L0X || SOC_SERIES_STM32L4X
depends on SOC_SERIES_STM32F0X || SOC_SERIES_STM32F3X || SOC_SERIES_STM32F7X || SOC_SERIES_STM32L0X || SOC_SERIES_STM32L4X || SOC_SERIES_STM32WBX
select HAS_DTS_I2C
select USE_STM32_LL_I2C
select USE_STM32_LL_RCC if SOC_SERIES_STM32F0X || SOC_SERIES_STM32F3X
select I2C_STM32_INTERRUPT if I2C_SLAVE
help
Enable I2C support on the STM32 F0, F3, F7 and L4X family of processors.
Enable I2C support on the STM32 F0, F3, F7, L4 and WBX family of processors.
This driver also supports the L0 series.
If I2C_SLAVE is enabled it selects I2C_STM32_INTERRUPT, since slave mode
is only supported by this driver with interrupts enabled.

2
drivers/i2c/i2c_ll_stm32_v2.c
View file

@ -4,7 +4,7 @@
*
* SPDX-License-Identifier: Apache-2.0
*
* I2C Driver for: STM32F0, STM32F3, STM32F7, STM32L0 and STM32L4
* I2C Driver for: STM32F0, STM32F3, STM32F7, STM32L0, STM32L4 and STM32WB
*
*/

7
soc/arm/st_stm32/stm32wb/Kconfig.defconfig.series
View file

@ -25,4 +25,11 @@ config GPIO_STM32_PORTH
endif # GPIO_STM32
if I2C_STM32
config I2C_STM32_V2
default y
endif # I2C_STM32
endif # SOC_SERIES_STM32WBX

19
soc/arm/st_stm32/stm32wb/dts_fixup.h
View file

@ -83,5 +83,24 @@
#define DT_FLASH_DEV_BASE_ADDRESS DT_ST_STM32WB_FLASH_CONTROLLER_58004000_BASE_ADDRESS
#define DT_FLASH_DEV_NAME DT_ST_STM32WB_FLASH_CONTROLLER_58004000_LABEL
#define DT_I2C_1_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005400_BASE_ADDRESS
#define DT_I2C_1_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40005400_IRQ_EVENT_PRIORITY
#define DT_I2C_1_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40005400_IRQ_ERROR_PRIORITY
#define CONFIG_I2C_1_NAME DT_ST_STM32_I2C_V2_40005400_LABEL
#define DT_I2C_1_EVENT_IRQ DT_ST_STM32_I2C_V2_40005400_IRQ_EVENT
#define DT_I2C_1_ERROR_IRQ DT_ST_STM32_I2C_V2_40005400_IRQ_ERROR
#define DT_I2C_1_BITRATE DT_ST_STM32_I2C_V2_40005400_CLOCK_FREQUENCY
#define DT_I2C_1_CLOCK_BITS DT_ST_STM32_I2C_V2_40005400_CLOCK_BITS
#define DT_I2C_1_CLOCK_BUS DT_ST_STM32_I2C_V2_40005400_CLOCK_BUS
#define DT_I2C_3_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005C00_BASE_ADDRESS
#define DT_I2C_3_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40005C00_IRQ_EVENT_PRIORITY
#define DT_I2C_3_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40005C00_IRQ_ERROR_PRIORITY
#define CONFIG_I2C_3_NAME DT_ST_STM32_I2C_V2_40005C00_LABEL
#define DT_I2C_3_EVENT_IRQ DT_ST_STM32_I2C_V2_40005C00_IRQ_EVENT
#define DT_I2C_3_ERROR_IRQ DT_ST_STM32_I2C_V2_40005C00_IRQ_ERROR
#define DT_I2C_3_BITRATE DT_ST_STM32_I2C_V2_40005C00_CLOCK_FREQUENCY
#define DT_I2C_3_CLOCK_BITS DT_ST_STM32_I2C_V2_40005C00_CLOCK_BITS
#define DT_I2C_3_CLOCK_BUS DT_ST_STM32_I2C_V2_40005C00_CLOCK_BUS
/* End of SoC Level DTS fixup file */

3
soc/arm/st_stm32/stm32wb/soc.h
View file

@ -46,6 +46,9 @@
#ifdef CONFIG_FLASH
#include <stm32wbxx_ll_hsem.h>
#endif /* CONFIG_FLASH */
#ifdef CONFIG_I2C
#include <stm32wbxx_ll_i2c.h>
#endif
#endif /* !_ASMLANGUAGE */