drivers: i2c: enable I2C on STM32WB
Enable I2C on STM32WB Signed-off-by: Roger N'Guessan <roger.nguessan@st.com>
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3df5ae68a7
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0a9d547cc1
5 changed files with 32 additions and 3 deletions
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@ -23,13 +23,13 @@ config I2C_STM32_V1
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config I2C_STM32_V2
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bool
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depends on SOC_SERIES_STM32F0X || SOC_SERIES_STM32F3X || SOC_SERIES_STM32F7X || SOC_SERIES_STM32L0X || SOC_SERIES_STM32L4X
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depends on SOC_SERIES_STM32F0X || SOC_SERIES_STM32F3X || SOC_SERIES_STM32F7X || SOC_SERIES_STM32L0X || SOC_SERIES_STM32L4X || SOC_SERIES_STM32WBX
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select HAS_DTS_I2C
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select USE_STM32_LL_I2C
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select USE_STM32_LL_RCC if SOC_SERIES_STM32F0X || SOC_SERIES_STM32F3X
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select I2C_STM32_INTERRUPT if I2C_SLAVE
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help
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Enable I2C support on the STM32 F0, F3, F7 and L4X family of processors.
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Enable I2C support on the STM32 F0, F3, F7, L4 and WBX family of processors.
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This driver also supports the L0 series.
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If I2C_SLAVE is enabled it selects I2C_STM32_INTERRUPT, since slave mode
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is only supported by this driver with interrupts enabled.
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@ -4,7 +4,7 @@
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* I2C Driver for: STM32F0, STM32F3, STM32F7, STM32L0 and STM32L4
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* I2C Driver for: STM32F0, STM32F3, STM32F7, STM32L0, STM32L4 and STM32WB
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*
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*/
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@ -25,4 +25,11 @@ config GPIO_STM32_PORTH
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endif # GPIO_STM32
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if I2C_STM32
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config I2C_STM32_V2
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default y
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endif # I2C_STM32
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endif # SOC_SERIES_STM32WBX
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@ -83,5 +83,24 @@
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#define DT_FLASH_DEV_BASE_ADDRESS DT_ST_STM32WB_FLASH_CONTROLLER_58004000_BASE_ADDRESS
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#define DT_FLASH_DEV_NAME DT_ST_STM32WB_FLASH_CONTROLLER_58004000_LABEL
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#define DT_I2C_1_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005400_BASE_ADDRESS
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#define DT_I2C_1_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40005400_IRQ_EVENT_PRIORITY
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#define DT_I2C_1_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40005400_IRQ_ERROR_PRIORITY
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#define CONFIG_I2C_1_NAME DT_ST_STM32_I2C_V2_40005400_LABEL
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#define DT_I2C_1_EVENT_IRQ DT_ST_STM32_I2C_V2_40005400_IRQ_EVENT
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#define DT_I2C_1_ERROR_IRQ DT_ST_STM32_I2C_V2_40005400_IRQ_ERROR
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#define DT_I2C_1_BITRATE DT_ST_STM32_I2C_V2_40005400_CLOCK_FREQUENCY
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#define DT_I2C_1_CLOCK_BITS DT_ST_STM32_I2C_V2_40005400_CLOCK_BITS
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#define DT_I2C_1_CLOCK_BUS DT_ST_STM32_I2C_V2_40005400_CLOCK_BUS
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#define DT_I2C_3_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005C00_BASE_ADDRESS
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#define DT_I2C_3_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40005C00_IRQ_EVENT_PRIORITY
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#define DT_I2C_3_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40005C00_IRQ_ERROR_PRIORITY
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#define CONFIG_I2C_3_NAME DT_ST_STM32_I2C_V2_40005C00_LABEL
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#define DT_I2C_3_EVENT_IRQ DT_ST_STM32_I2C_V2_40005C00_IRQ_EVENT
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#define DT_I2C_3_ERROR_IRQ DT_ST_STM32_I2C_V2_40005C00_IRQ_ERROR
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#define DT_I2C_3_BITRATE DT_ST_STM32_I2C_V2_40005C00_CLOCK_FREQUENCY
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#define DT_I2C_3_CLOCK_BITS DT_ST_STM32_I2C_V2_40005C00_CLOCK_BITS
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#define DT_I2C_3_CLOCK_BUS DT_ST_STM32_I2C_V2_40005C00_CLOCK_BUS
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/* End of SoC Level DTS fixup file */
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@ -46,6 +46,9 @@
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#ifdef CONFIG_FLASH
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#include <stm32wbxx_ll_hsem.h>
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#endif /* CONFIG_FLASH */
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#ifdef CONFIG_I2C
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#include <stm32wbxx_ll_i2c.h>
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#endif
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#endif /* !_ASMLANGUAGE */
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