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drivers/plic: Remove DTS fixups for RISC-V PLIC

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Change the DT macros used by the RISC-V PLIC driver so that fixups
are no longer required.

Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
This commit is contained in:
Nathaniel Graff 2019-03-20 16:02:40 -07:00 • committed by Anas Nashif
commit 627e27a25f
2 changed files with 10 additions and 26 deletions
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20
drivers/interrupt_controller/plic.c
View file

@ -42,7 +42,7 @@ void riscv_plic_irq_enable(u32_t irq)
u32_t key;
u32_t plic_irq = irq - RISCV_MAX_GENERIC_IRQ;
volatile u32_t *en =
(volatile u32_t *)DT_PLIC_IRQ_EN_BASE_ADDR;
(volatile u32_t *)DT_RISCV_PLIC0_0_IRQ_EN_BASE_ADDRESS;
key = irq_lock();
en += (plic_irq >> 5);
@ -68,7 +68,7 @@ void riscv_plic_irq_disable(u32_t irq)
u32_t key;
u32_t plic_irq = irq - RISCV_MAX_GENERIC_IRQ;
volatile u32_t *en =
(volatile u32_t *)DT_PLIC_IRQ_EN_BASE_ADDR;
(volatile u32_t *)DT_RISCV_PLIC0_0_IRQ_EN_BASE_ADDRESS;
key = irq_lock();
en += (plic_irq >> 5);
@ -88,7 +88,7 @@ void riscv_plic_irq_disable(u32_t irq)
int riscv_plic_irq_is_enabled(u32_t irq)
{
volatile u32_t *en =
(volatile u32_t *)DT_PLIC_IRQ_EN_BASE_ADDR;
(volatile u32_t *)DT_RISCV_PLIC0_0_IRQ_EN_BASE_ADDRESS;
u32_t plic_irq = irq - RISCV_MAX_GENERIC_IRQ;
en += (plic_irq >> 5);
@ -109,14 +109,14 @@ int riscv_plic_irq_is_enabled(u32_t irq)
void riscv_plic_set_priority(u32_t irq, u32_t priority)
{
volatile u32_t *prio =
(volatile u32_t *)DT_PLIC_PRIO_BASE_ADDR;
(volatile u32_t *)DT_RISCV_PLIC0_0_PRIO_BASE_ADDRESS;
/* Can set priority only for PLIC-specific interrupt line */
if (irq <= RISCV_MAX_GENERIC_IRQ)
return;
if (priority > DT_PLIC_MAX_PRIORITY)
priority = DT_PLIC_MAX_PRIORITY;
if (priority > DT_RISCV_PLIC0_0_RISCV_MAX_PRIORITY)
priority = DT_RISCV_PLIC0_0_RISCV_MAX_PRIORITY;
prio += (irq - RISCV_MAX_GENERIC_IRQ);
*prio = priority;
@ -140,7 +140,7 @@ int riscv_plic_get_irq(void)
static void plic_irq_handler(void *arg)
{
volatile struct plic_regs_t *regs =
(volatile struct plic_regs_t *)DT_PLIC_REG_BASE_ADDR;
(volatile struct plic_regs_t *) DT_RISCV_PLIC0_0_REG_BASE_ADDRESS;
u32_t irq;
struct _isr_table_entry *ite;
@ -186,11 +186,11 @@ static int plic_init(struct device *dev)
ARG_UNUSED(dev);
volatile u32_t *en =
(volatile u32_t *)DT_PLIC_IRQ_EN_BASE_ADDR;
(volatile u32_t *)DT_RISCV_PLIC0_0_IRQ_EN_BASE_ADDRESS;
volatile u32_t *prio =
(volatile u32_t *)DT_PLIC_PRIO_BASE_ADDR;
(volatile u32_t *)DT_RISCV_PLIC0_0_PRIO_BASE_ADDRESS;
volatile struct plic_regs_t *regs =
(volatile struct plic_regs_t *)DT_PLIC_REG_BASE_ADDR;
(volatile struct plic_regs_t *)DT_RISCV_PLIC0_0_REG_BASE_ADDRESS;
int i;
/* Ensure that all interrupts are disabled initially */

16
soc/riscv32/riscv-privilege/sifive-freedom/dts_fixup.h
View file

@ -1,16 +0,0 @@
/*
* Copyright (c) 2018 SiFive Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/* PLIC */
#define DT_PLIC_MAX_PRIORITY \
DT_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY
#define DT_PLIC_PRIO_BASE_ADDR \
DT_RISCV_PLIC0_C000000_PRIO_BASE_ADDRESS
#define DT_PLIC_IRQ_EN_BASE_ADDR \
DT_RISCV_PLIC0_C000000_IRQ_EN_BASE_ADDRESS
#define DT_PLIC_REG_BASE_ADDR \
DT_RISCV_PLIC0_C000000_REG_BASE_ADDRESS