Remove the redundant cast to struct device * from struct device * in
some of the GPIO API syscall handlers in gpio_handlers.c
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
The following APIs
- gpio_port_set_masked()
- gpio_port_set_bits()
- gpio_port_clear_bits()
- gpio_port_set_clr_bits_raw()
- gpio_port_set_clr_bits()
- gpio_pin_get_raw()
- gpio_pin_get()
- gpio_pin_set_raw()
- gpio_pin_set()
- gpio_pin_toggle()
are currently not syscalls, while the following are:
- gpio_port_set_bits_raw()
- gpio_port_get_raw()
It is therefore possible to set and get any pin of the entire port
from userspace, but only through a few of the APIs.
These APIs should all be either syscalls, or not syscalls.
Align the APIs so they are all syscalls and add syscall handlers for
them in gpio_handler.c
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
After DWC2 core is disabled the registers should no longer be accessed
to prevent CPU hangs. While the concurrent access is guarded by mutex,
there was no mechanism to ensure that driver thread won't access any
register after udc_disable() was called. Solve the issue by executing
disable in driver thread context.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Add driver for Nordic USB PD Charging-Type detector.
This driver depends on the USBHS wrapper driver.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Co-authored-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Use USBHS wrapper driver to register VREGUSB regulator callback and
enable USB peripheral.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Co-authored-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Nordic USBHS wrapper is a set of registers used by both USB BC12 driver
and vendor specific part in UDC driver. The wrapper can be considered
to be MFD device. Both drivers depends on the VBUS regulator driver and
require some synchronisation when accessing wrapper register.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Co-authored-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Add the option to explicitly request the HFXO while the UARTE peripheral
is active for nRF54L series devices. While the UARTE peripheral requests
a high frequency clock from the clock controller, both the HFINT and
HFXO oscillators satisfy this request. The problem is that the HFXO
oscillator is required to reach the highest bitrate accuracies (and
mitigate errata 30).
Signed-off-by: Jordan Yates <jordan@embeint.com>
make CONFIG_SSD135X a hidden symbol similar to other display driver groups
so that it doesn't bleed into the main display drivers menu.
Fix spelling of the prompt for the actual drivers to also align with other
drivers.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
In addition to `ERROR`, also abort on `+CME ERROR`, which is a 3GPP
documented (TS.128.007 v18.6.0 9.2) alternative error code.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Move standalone (not using `modem_cellular.c`) drivers to a dedicated
subfolder, keeping the top level folder clean for common utilities.
Signed-off-by: Jordan Yates <jordan@embeint.com>
A flash manager thread is created and allocated to
process Flash Manager Process.
Definition of KConfigs STM32WBA_FLASH_MNGR_THREAD_STACK_SIZE,
and STM32WBA_FLASH_MNGR_THREAD_PRIO to configure the
flash manager thread.
STM32WBA_FLASH_MNGR_THREAD_STACK_SIZE is setting by default
to 768 bytes. This value was chosen empirically since reasonable
to cover generic cases.
Signed-off-by: Vincent Tardy <vincent.tardy@st.com>
Repeat the call to `i2c_nrfx_twim_rtio_start` until there are either
no more operations queued, or an asynchronous operation is pending
completion. This fixes a queue of operations that contains an operation
that completes inside of `i2c_nrfx_twim_rtio_start` (e.g.
`RTIO_OP_I2C_CONFIGURE`) from not starting the remaining operations,
which then forever blocks any pending callers.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Fixes a compilation failure on NXP MCX E-series (and other NXP SoCs)
where FSL_FEATURE_SAI_HAS_BIT_CLOCK_SWAP is 0 or undefined.
The driver was unconditionally assigning to a non-existent struct
member. Resolved by wrapping the assignment in the proper feature
macro checks.
Signed-off-by: Jan Willem Smaal <usenet@gispen.org>
3GPP TS 27.010 section 5.4.6.3.2 specifies a PSC frame exchange when
entering power save and section 5.4.7 specifies a flag-byte exchange
when exiting. modem_cmux blocks at T3 timeout on either half if the
peer does not implement the exchange, which is the case for modems
that manage sleep and wake out-of-band (hardware lines or
modem-control AT commands).
Add an opt-in DT property cmux-no-powersave-handshake (default off)
on the cellular-modem common binding. When set,
modem_cmux_runtime_pm_handler skips modem_cmux_send_psc and the T3
reschedule on entry and transitions directly to STATE_POWERSAVE;
powersave_wait_wakeup skips the wake-pattern transmission and the
STATE_RESYNC wait on exit and transitions directly to STATE_CONNECTED.
Signed-off-by: Paulo Santos <paulo.santos-ext@hexagon.com>
spi_mcux_init_common() can fail, propagate the error on TURN_ON
instead of silently ignoring it.
Signed-off-by: Sofian Elmotiem <sofianelmotiem@gmail.com>
For PM2 (suspend-to-idle), flexcomm registers are retained so a full
init_common is not needed. Instead, disable the I2C master before
applying the sleep pinctrl state on SUSPEND, and re-enable it after
restoring the default pinctrl state on RESUME.
Initialize the master with enableMaster = false in init_common so that
TURN_ON does not prematurely enable the master before RESUME restores
the pinctrl state. pm_device_driver_init always calls RESUME after
TURN_ON so the master is enabled correctly on both first boot and PM3
wakeup.
Signed-off-by: Sofian Elmotiem <sofianelmotiem@gmail.com>
Re-added irq_update API for UART.
It is required to clean the FIFO status, which flushes
the content correctly.
Signed-off-by: Davide Di Lello <Davide.Dilello@Infineon.com>
Install default stepper and stepper_ctrl API delegates to avoid
unitialized variables when no delegate is installed by the
application/test suite.
Signed-off-by: Jilay Pandya <jilay.pandya@outlook.com>
This commit fixes the command packet size allocation. It allocates an
'hci_cmd_buf' buffer to store the HCI command packet to send. The buffer
size supports the maximum command packet size and the maximum event size.
This commit also fixes an issue where the buf argument was not unreferenced
when bt_buf_get_evt() failed in the BT_HCI_H4_CMD command case.
Signed-off-by: Vincent Tardy <vincent.tardy@st.com>
IT8XXX2 currently enables I2C_TARGET_BUFFER_MODE for all I2C targets.
This affects unrelated drivers such as the LPC55S69 custom target sample.
Limit the IT8XXX2 target defaults to the ITE enhance I2C driver, so
non-ITE targets stay in byte mode unless they opt in.
Guard Ambiq IOS buffer callbacks behind I2C_TARGET_BUFFER_MODE and enable
buffer mode explicitly for Nordic TWIS target API test builds.
Fixes#108902
Signed-off-by: Manjae Cho <manjae.cho@samsung.com>
The arm_arch_timer driver only uses the architecture-level
IRQ_CONNECT/irq_enable abstractions, both of which dispatch through
arch_irq_*() and therefore work whether the underlying interrupt
controller is a GIC or a SoC-supplied custom controller. The latter
is selected via CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER, in which
case the arm64 arch layer maps the calls to the SoC-provided
z_soc_irq_* hooks.
The "depends on GIC" predates custom-intc support landing in arm64
and is artificially restrictive. Relax it so non-GIC arm64 SoCs can
reuse the canonical timer driver instead of cloning it.
The driver itself is unchanged.
Signed-off-by: Jonathan Elliot Peace <jep@alphabetiq.com>
Fixing some target misbehaviors I found while working with
a multi-target setup. Namely:
1. Potential missing event when swapping directions / repeated
starts
2. Make target more robust against controller timing between
ACK and sending first byte
3. Target defaulted to ACKing every address, now checks for match
4. Set pins back to default gpio when unregistering, and
reconfigure them for i2c when registering. This prevents an
unregistered I2C from breaking the bus by holding it low
5. Disabled NVIC when unregistering targets. Infineon has dedicated
interrupts for SCBs, so this is safe.
6. Preemptively arm wrie buffer to avoid a potential race condition
when target RX auto-ACK is enabled
Restructure the event handler since it was getting too large - split
out a target path
Assisted-by: Claude:claude-opus-4.7
Signed-off-by: Zayne Stites <Zayne.Stites@infineon.com>
The implementation of the "system timer low-power companion interface"
when CONFIG_SYSTEM_TIMER_LPM_COMPANION_COUNTER is selected is generic,
but was done in the Cortex-M SysTick driver for historical reasons.
Move the implementation to a common source file included in the build
when CONFIG_SYSTEM_TIMER_LPM_COMPANION_COUNTER is selected. This cleans
up the Cortex-M SysTick driver and allows other system timer drivers to
benefit from the code.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
The Digital Filter for Sigma Delta Modulators (DFSDM) is dedicated to
interface external Σ∆ modulators.
It features:
* Up to 8 multiplexed input digital serial channels:
– SPI or Manchester-coded 1 wire interface
– clock output for Σ∆ modulators
* Up to 8 internal digital parallel channels:
– up to 16 bit resolution
– internal sources: memory (CPU/DMA write) data streams
* Adjustable digital signal processing
* Up to 24-bit output data resolution
* Signed output data format
* Continuous or one-shot conversion
* “regular” or “injected” conversions
* Analog watchdog
* Short-circuit detector
* Min/Max extremes detector
* DMA read access
* Interrupts for end of conversion, overrun, analog watchdog,
short-circuit, channel clock absence
Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>
The LLI descriptor cache flush was unconditionally performed even
when a Cache Coherence Unit (CCU) is present. When CCU is enabled,
hardware guarantees a consistent data view between the DMA and
processor, making software cache maintenance redundant.
Signed-off-by: Hareem Sadiq <hareemx.sadiq@altera.com>
The max_channel is a compile time constant derived from device tree
and never modified at runtime.
Adding it to read only dev_cfg structure and using this variable from
dev_cfg structure
Signed-off-by: Hareem Sadiq <hareemx.sadiq@altera.com>
Abstract DT reset property check into a reset_supported macro,
update variable type to uint32_t, and remove channel < 0
check which is always false because of the uint32_t type
variable
Signed-off-by: Hareem Sadiq <hareemx.sadiq@altera.com>
The driver used a plain enum for channel state tracking which is
not safe on multi-core systems. A plain enum read-modify-write is
not guaranteed atomic on SMP a concurrent read on another core
could observe a torn or intermediate state value.
Replace ch_state with atomic_t and use atomic_set()/atomic_get()
for all channel state transitions. This ensures state visibility
across all cores without blocking, and preserves ISR callability
as required by the Zephyr DMA API
Signed-off-by: Hareem Sadiq <hareemx.sadiq@altera.com>
Previously, upstream left the AXI CTL fields at 0. Now adding the
AxCache and AxProt attributes macro and setting to the values
required for cache-coherent interconnect in Agilex5.
Signed-off-by: Hareem Sadiq <hareemx.sadiq@altera.com>
The driver currently checks for DT_INST_PROP_OR(n, ...). n is not
defined, it should be inst.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
The stop_det handler resets dw->state to READY and clears
read_in_progress before calling the target's stop() callback.
The driver is already in READY stateand a concurrent interrupt
may observe an inconsistent view.
Invoke stop() first, then reset state. This matches the ordering of
most other Zephyr I2C target drivers and keeps the state transition
atomic with respect to the callback.
Signed-off-by: Sudarshan Iyengar <sudarshan.iyengar@alifsemi.com>
dw->read_in_progress is only cleared in the stop_det branch of the
target ISR and at target_register() time. If a master read is
aborted by NACK (tx_abrt) or by bus error (rx_under/rx_over/tx_over)
without a terminating STOP, the flag remains set. The next legitimate
master read then takes the else branch and invokes read_processed()
instead of read_requested(), so the target never sees a fresh
read transaction and returns stale data.
Clear read_in_progress in every error path that resets dw->state
to READY.
i2c_dw_slave_read_clear_intr_bits() previously re-read IC_INTR_STAT
locally, while i2c_dw_isr() had already cached the same register at
entry. Two independent reads of a hardware status register create a
race: bits can be asserted by hardware between the two reads, causing
the helper and the ISR to observe different views of the interrupt
state.
Signed-off-by: Sudarshan Iyengar <sudarshan.iyengar@alifsemi.com>
Assisted-by: Claude:claude-opus-4.7
The target ISR gates write_requested() on `dw->state != CMD_SEND` so
that back-to-back rx_full interrupts during a single write do not
re-enter the callback. However, dw->state is only transitioned back
to READY on stop_det. If the STOP interrupt is lost (glitch, bus
reset, another master drives STOP while we are servicing the ISR),
or if the master issues a repeated START with the same direction
(WRITE-Sr-WRITE, which is legal in I2C), the state stays CMD_SEND
forever and write_requested() is never called again for the rest of
the target's life.
i2c_dw_slave_read_clear_intr_bits() already handles start_det by
resetting state to READY, but START_DET is not in the enabled
interrupt mask in i2c_dw_slave_register(), so that path is dead code.
Unmask START_DET so the boundary of every new (re)START on the bus
is observed and state is correctly reset before the rx_full handler
decides whether to call write_requested().
Signed-off-by: Sudarshan Iyengar <sudarshan.iyengar@alifsemi.com>
Replace the driver-private spinlock with the unified timer lock API
introduced by commit 32b1399669 ("kernel/timeout: introduce
sys_clock_lock() and sys_clock_announce_locked()"), following the
pattern already applied to other SMP-capable timer drivers.
No in-tree board enables CONFIG_SMP on a Cortex-M, so the specific
two-CPU race that motivated that commit does not apply here. The
same two-lock window is still reachable in UP, though: a nested IRQ
handler that uses time facilities can fire between sys_clock_isr()'s
update of the hardware baseline (cycle_count, announced_cycles,
under the driver-private lock) and the sys_clock_announce() call
that advances curr_tick (under the kernel's timeout_lock), see the
two halves of "now" out of sync, and observe time going backwards
from one call to the next. Putting the hardware cycle baseline and
curr_tick under a single lock closes that window the same way it
does on SMP.
As a direct consequence, sys_clock_set_timeout() and
sys_clock_elapsed() no longer need to acquire anything -- the caller
already holds the kernel timeout lock across both the driver call
and the following sys_clock_announce(). The driver is now consistent
with the convention used by all the other timer drivers.
sys_clock_cycle_get_32() / sys_clock_cycle_get_64() /
sys_clock_idle_exit() / z_sys_clock_hw_cycles_per_sec_update() are
called from contexts that do not hold the kernel's timeout lock, so
they acquire it via sys_clock_lock() themselves.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Rework sys_clock_set_timeout() along the same lines as the RISC-V
machine timer (drivers/timer/riscv_machine_timer.c) and ARM generic
timer (drivers/timer/arm_arch_timer.c) drivers: compute the absolute
cycle target for the next fire and program SysTick for the delta to
it, rather than reconstructing a tick-aligned fire point on every
call through the old "-1, round up to tick boundary, subtract
unannounced" dance.
The core of the computation shrinks from:
delay = ticks * CYC_PER_TICK;
delay += unannounced;
delay = DIV_ROUND_UP(delay, CYC_PER_TICK) * CYC_PER_TICK;
delay -= unannounced;
delay = MAX(delay, MIN_DELAY);
if (delay > MAX_CYCLES) { last_load = MAX_CYCLES; }
else { last_load = delay; }
into:
int64_t want = ((uint64_t)last_elapsed + ticks) * CYC_PER_TICK;
int64_t delta = want - unannounced;
cycles = CLAMP(delta, MIN_DELAY, MAX_CYCLES);
SysTick->LOAD = cycles - 1;
No tick-boundary realignment and no DIV_ROUND_UP round-trip. The
64-bit intermediate absorbs arbitrarily large 'ticks' without
overflowing the 32-bit cycle product. The division-by-CYC_PER_TICK
that lived in the hot path is gone (divisions by non-constant
divisors are costly even on 32 bits, so avoiding them where we can
is worthwhile).
Concretely:
* Track last_elapsed -- the tick count most recently returned to the
kernel via sys_clock_elapsed() -- and use it as the "now" reference
when computing the deadline. sys_clock_isr() resets last_elapsed
to 0 on every announce.
* The pre-clamp on 'ticks' and the MAX_TICKS derivation are gone:
the clamp applies to the computed cycle count (the quantity the
hardware LOAD register actually constrains), and MAX_CYCLES is
the 24-bit COUNTER_MAX directly.
* Explicitly clear SCB->ICSR PENDSTCLR on every reprogram. Writing
SysTick->VAL = 0 clears CTRL.COUNTFLAG but leaves any pending
SysTick exception from the old schedule armed in ICSR. Without this
explicit clear, a wrap that fired between sys_clock_elapsed() and
the LOAD/VAL reset would still trigger the ISR once interrupts are
re-enabled, with the ISR then reading the new LOAD/VAL and
mis-accounting the elapsed time. Matches the pattern already used
in the LPM RESET_BY_LPM path.
The elapsed() helper, overflow_cyc bookkeeping, LPM companion paths,
runtime frequency update, 64-bit cycle counter variant, the val1/val2
drift-compensation dance around the LOAD/VAL write, and the
non-tickless fallback are untouched. The wire-level behaviour is
identical in the normal case; the only observable behaviour change
is the PENDSTCLR write, which closes a latent race that could delay
a stale ISR by one LOAD worth of cycles.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Added autonomous analog CTDAC for PSE84 device.
This implementation uses the autonomous controller (MFD)
that is shared with other autanalog drivers.
The CTDAC stands for Continuous Time DAC. It is a programmable DAC
residing inside the autonomous (aut) analog subsystem. It is
controlled using the autonomous controller (AC), which is a
programmable state machine. The AC is shared across all autonomous
analog peripherals including the SAR, PRB, PTComp, CTB, and CTDAC.
The DAC output can either be software controlled or be driven
through the AC hardware by loading through an internal LUT memory.
AC MFD references the DAC configuration, and brings together all
other autanalog peripherals into a single AC setup for the application.
Assisted-by: Claude:claude-opus-4.6
Signed-off-by: Richard Mc Sweeney <Richard.McSweeney@infineon.com>
This PR introduces the `sda-hold-time-ns` DeviceTree property for
DesignWare I2C controllers. The driver logic is updated to prioritize
this nanosecond configuration, calculating the necessary hardware clock
ticks at build time using the new `HOLD_TIME_TO_TICKS` macro. If the
property is not defined, it safely falls back to the legacy
`sda-hold-tx` tick configuration.
Fixes#83437
Signed-off-by: Akansh Sinha <akansh.sinha.dev@gmail.com>
Add support for configuring the minimum timer delay via the Devicetree
property 'zephyr,min-timeout-cycles'. This is particularly useful for
platforms using low-frequency clock sources (e.g., 32.768 kHz).
The driver's default MIN_DELAY is MAX(1024, CYC_PER_TICK / 16). On a
system with a 32.768 kHz clock and CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000,
CYC_PER_TICK is 32. This results in a MIN_DELAY of 1024 cycles, which
translates to a ~31 ms minimum timeout. This granularity is too
coarse for tickless operation and causes failures in tests that expect
sub-10ms precision.
This change allows boards to override this limit, enabling finer timing
resolution while maintaining the existing default for backward
compatibility.
Signed-off-by: Zhiyuan Tang <zhiyuan_tang@realsil.com.cn>
Allow configuring the clock source for TI's dmtimer using syscon driver for
MMR writes. The new property "clksel" takes offset and value to select
the mux configuration.
This is required since there are no clock parent APIs in the clock
controller subsystem as of now.
Signed-off-by: Amneesh Singh <amneesh@ti.com>
The i2c bus may be pulled low by unstable environment.
Check the status before I2C transfer and
skip transmission if the bus is not ready.
Signed-off-by: Lin Yu-Cheng <lin_yu_cheng@realtek.com>
- Switch binding to zephyr,cellular-modem-device.yaml
- Use MODEM_DT_INST_PPP_DEFINE to properly associate PPP with the modem
device and preserve runtime PM integration
Signed-off-by: Luca Impagliazzo <Luca.Impagliazzo@telit.com>
