On ESP32-C6, esp32_cpu_clock_configure() switches the analog I2C
master to the sel_160m = 0 clock source before enabling the BBPLL.
That source is routed through modem_lpcon state which
esp_system_reset_modules_on_exit() resets on shutdown and which the
ROM's soft-boot path does not restore (the ROM's full power-on path
does). After any software reset — including the reboot MCUboot-based
applications perform to install a firmware update — the BBPLL
calibration in rtc_clk_bbpll_configure() then spins forever on
regi2c_ctrl_ll_bbpll_calibration_is_done() reading a clockless
register: the chip hangs pre-console until power is cycled, while the
USB device stays enumerated. Power-on boots are unaffected, which
makes the hang easy to miss in bring-up testing.
Select the PLL-derived I2C master clock instead, exactly like the IDF
second-stage bootloader (bootloader_esp32c6.c,
bootloader_hardware_init()): on the C6 the BBPLL is alive on every
boot path, since the ROM requires it for USB-Serial-JTAG and
esp_restart() deliberately keeps it running.
Root-caused with early-boot breadcrumbs on ESP32-C6 hardware
(MCUboot + application, Zephyr v4.4.1 and current main code paths):
before the fix every 'kernel reboot cold' and every OTA install
reboot hung in the MCUboot image right after bootloader flash init;
with the fix, consecutive software resets and a full OTA install
cycle boot cleanly.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Signed-off-by: Linus Rüttimann <linus@noxblanc.com>
Add a devicetree property to configure the WM8904 input PGA
source channel.
The selected channel is used when configuring the analog input path.
For the 32-pin QFN package, only input channels 1 and 2 are valid
because the IN3L/IN3R pins are not exposed. The driver currently
supports single-ended input mode only
Signed-off-by: Mario Paja <mariopaja@hotmail.com>
Fixes#113852
Updating the top value on the RPi Pico timer was causing a hardware
glitch that resulted in unusual PWM behavior and frequency spikes.
This patch removes the pwm_init() call and instead uses
pwm_set_wrap() to directly update the hardware slice on the fly.
Signed-off-by: Sudharsan Bakthavatchalam <appubaktha@gmail.com>
The MCXW IEEE 802.15.4 driver is now compiled only when CONFIG_NET_L2
is enabled. This allows a vendor-specific radio.c implementation to be
used without requiring networking stack support.
Signed-off-by: Cristian Bulacu <cristian.bulacu@nxp.com>
Header file include/zephyr/sys_clock.h is deprecated and will be removed
someday. Update the whole file tree to include zephyr/sys/clock.h
straight instead of zephyr/sys_clock.h.
This change was made running the sed shell command below:
$ sed -i 's/zephyr\/sys_clock\.h/zephyr\/sys\/clock\.h/' \
`grep -rsl "zephyr/sys_clock\.h" drivers/`
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Header file include/zephyr/sys_clock.h is deprecated and will be removed
someday. Update the whole file tree to include zephyr/sys/clock.h
straight instead of zephyr/sys_clock.h.
This change was made running the sed shell command below:
$ sed -i 's/zephyr\/sys_clock\.h/zephyr\/sys\/clock\.h/' \
`grep -rsl "zephyr/sys_clock\.h" drivers/watchdog`
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Header file include/zephyr/sys_clock.h is deprecated and will be removed
someday. Update the whole file tree to include zephyr/sys/clock.h
straight instead of zephyr/sys_clock.h.
This change was made running the sed shell command below:
$ sed -i 's/zephyr\/sys_clock\.h/zephyr\/sys\/clock\.h/' \
`grep -rsl "zephyr/sys_clock\.h" drivers/timer`
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
We updated the XEC clock control driver to support MEC174x/5x
and move away from hard to maintain CMSIS register structures.
Addition device tree properties were added for tuning the driver's
XTAL configuration sequence. Note: MEC15xx does not have the
clock monitor hardware for checking XTAL health and no way to
fallback if the XTAL fails.
Many MEC15xx/MEC172x legacy Zephyr drivers are using XEC specific
clock control driver PCR sleep and reset APIs. Until all old
drivers are converted to use the same functionality from the MEC SoC
layer we must keep these APIs. We converted them to call the SoC
layer. Once all drivers have been converted we can removed these
custom APIs from the clock control driver.
The domain clock-cells parameter was renamed to clkid matching usage
in the DW I2C driver and many other clock control drivers.
We changed domain to clkid in the only two drivers remaining that
use it, interrupt-controller and crypto.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Refactor elapsed() to thread the SysTick->VAL snapshot out via an
optional pointer parameter instead of requiring an independent,
racy re-read or duplicating the wrap-detection logic.
An earlier fix for a VAL re-read race in timeout calculation unrolled
elapsed() inside sys_clock_set_timeout(). That unrolling duplicated
the complex wrap-detection logic across two places in the driver,
creating a maintenance hazard.
Resolve this by refactoring elapsed() to accept a uint32_t *val_out
parameter. When provided, it exports the exact val2 snapshot used
to calculate elapsed cycles. In sys_clock_set_timeout(), calling
elapsed(&val1) safely captures this snapshot to seed the drift
calculation, eliminating the timing gap with perfect precision and
no code duplication.
Signed-off-by: Surya Prakash T <suryat@aerlync.com>
This commit add Zerocopy operation for Renesas RA Ethernet driver
This also add buffer allocation into nocache region when CPU cache
is used to prevent incoherrency
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Signed-off-by: Nhat Ta <nhat-minh.ta.yn@bp.renesas.com>
This commit seperates pinctrl blocks for mdio node and ethernet node,
also add clock source for ethernet node.
Signed-off-by: Nhat Ta <nhat-minh.ta.yn@bp.renesas.com>
Use #include <> instead of #include "" to include a header file which path
is not relative to the directory path of the file emitting the #include
directive.
This change was made running scripts/check_quoted_includes.py script
proposed in https://github.com/zephyrproject-rtos/zephyr/pull/112135
with Linux shell commands like the one below and manually selecting the
applicable changes: only those located in drivers/ since soc/, boards/,
samples/ and tests/ content related to Espressif is addressed in
pull request https://github.com/zephyrproject-rtos/zephyr/pull/112190.
$ ./scripts/check_quoted_includes.py -w \
`./scripts/get_maintainer.py list "Espressif Platforms"`
Also update drivers/clock_control/clock_control_esp32_priv.h that was
not listed by './scripts/get_maintainer.py list "Espressif Platforms"'.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
The RTWDOG driver previously rejected WDT_OPT_PAUSE_IN_SLEEP with
-ENOTSUP, even though the hardware supports stopping the counter
in low-power modes via workMode.enableWait and workMode.enableStop.
Map WDT_OPT_PAUSE_IN_SLEEP to both enableWait and enableStop fields.
Assisted-by: Claude:opus-4.6
Signed-off-by: Jason Yu <zejiang.yu@nxp.com>
Add support for STM32H5 series to the stm32_hash driver.
Support is added through the STM32 HASH HAL v2 to remain generic.
Signed-off-by: Joel Guittet <jguittet@witekio.com>
To avoid the assumption that ZVFS_O_RDONLY/ZVFS_O_WRONLY match
O_RDONLY/O_WRONLY, let's just have this code be compiled with the host
libC always.
The code is also a bit more readable without all the nsi_host prefixes.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Presently the Offloaded raw TX API names are tied to the nRF70 platform.
So make the API names platform agnostic.
Signed-off-by: Kapil Bhatt <kapil.bhatt@nordicsemi.no>
Adds a hwinfo driver for the NXP LPC55xx Power Management
Controller (PMC).
Instantiates the pmc node on the LPC55S0x/S1x/S2x/S3x/S6x SoCs.
The driver implements hwinfo_get_reset_cause(),
hwinfo_clear_reset_cause() and hwinfo_get_supported_reset_cause().
Tested on LPCXpresso55S06/16/28/36/69
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
The driver asserted !status on the TRNG SDK calls and always
returned 0. In release builds __ASSERT_NO_MSG is a no-op, so
HW failures were silently swallowed and callers received
success with a possibly zero-filled buffer, poisoning the
xoshiro128 seed and pinning sys_rand_get() to 0.
Return -EIO on any status_t != kStatus_Success in both the
get_entropy and init paths, and propagate the init return
value from the PM TURN_ON action.
Signed-off-by: Ofir Shemesh <ofirshemesh777@gmail.com>
Drop the buffer and buffer_size pointer from the data struct and use the
ones in cfg directly, guess this was originally done to avoid using the
data dev pointer in data, but now it's there anyway so we may as well
use it to find back the cfg pointer and use the buffer and buffer_size
from there directly, save few bytes of sram.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The dual-bank error check read SR2 but tested the bank1 ECC error
flags, so bank2 ECC errors were reported based on bank1 bits. Use
the bank2 flags like the rest of the bank2 block.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
PM2STS.GPF (host-command BUSY) is set in the PMC2 IBF ISR and cleared
on the response path. If a sysjump happens in between, the response
never runs and GPF is left set. The new image re-enables the PMC2
interrupt but doesn't clear the BUSY bit, so the host sees a
permanently BUSY interface and every subsequent host command times
out.
Clear PM2STS.GPF in pmc2_it8xxx2_init() before enabling the IBF
interrupt, matching the equivalent fix in the Nuvoton NPCX driver
(host_hcmd_init() in drivers/espi/host_subs_npcx.c clears HIPMST.F0
for the same reason)
Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.corp-partner.google.com>
The RRAM driver was allowing unaligned operations for erase
and write because the underlying PDL driver would correct the
operation doing read-modify-write. Rather than relying on the
lower level implementation to correct the alignements and due
to the fact that the flash apis specifically state that alignment
must be checked, added the check and returned error for
unaligned operations.
Signed-off-by: Laura Carlesso <laura.carlesso@infineon.com>
A plain LPTMR counter that is not the system-timer companion can also
serve as a wakeup source - for example an application arming an alarm
before entering a deep low-power state - but whether it should wake the
SoC is a run-time decision, not a fixed role.
In addition to the companion path, arm the wakeup controller when the
instance has been enabled as a wakeup source at run time
(pm_device_wakeup_enable(), PM_DEVICE_FLAG_WS_ENABLED); the device
declares the capability in devicetree (wakeup-source) and the
application enables it. Register a pm_device so the device can carry the
flag; the action callback has no device power state to manage, so it
accepts suspend/resume and returns -ENOTSUP for anything else. The
registration and the flag check are a no-op unless CONFIG_PM_DEVICE is
enabled, so the companion path stays free of any PM_DEVICE dependency.
Disarming still keys off the static "is a wakeup source" condition and
deliberately does not re-check WS_ENABLED: the run-time flag can be
cleared between arming the alarm and its firing or cancellation, and a
disarm gated on WS_ENABLED would then be skipped, leaving a stale entry
armed in the controller. Because the static condition is a superset of
the arm condition, whatever armed the WUU is always disarmed, and
disarming an instance that never armed is an idempotent no-op.
Build-tested tests/subsys/pm/power_mgmt_soc on frdm_mcxn947.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
When the LPTMR is the system-timer low-power companion, the main system
timer is stopped in deep low-power states and the LPTMR alarm is what
wakes the core. On SoCs that gate the alarm interrupt behind a wakeup
controller (the NXP WUU) the alarm only wakes the SoC once the LPTMR is
armed as a wakeup source, which the driver never did.
Arm the wakeup controller in set_alarm() and disarm it in
cancel_alarm() and the ISR when the LPTMR is a wakeup source -
devicetree both declares it one (wakeup-source) and routes it to a
controller (wakeup-ctrls) - and it is the chosen system-timer companion
(zephyr,system-timer-companion), whose alarm is intrinsically a wake
event. Keying the companion off the devicetree chosen keeps it
independent of the system-timer implementation and needs no device-PM
state; it also covers an application that drives the companion instance
directly (e.g. a system-off wake timer).
The controller is armed and disarmed under the alarm spinlock so a
concurrent set_alarm()/cancel_alarm() pair cannot leave it armed with no
pending alarm (or vice versa); the WUC calls only write registers, so
they are safe under the spinlock and in the ISR. Arming happens before
the alarm is committed and a failure propagates as the set_alarm()
return value rather than a log: on the companion path the console may
already be suspended when this runs, and if the arm failed the SoC would
sleep without waking to flush a deferred message, so only the return
value can act before the sleep. The ISR ignores the disarm result for
the same reason; disarming a devicetree-defined source does not fail.
The companion arms only when it has a deadline to wake for, which falls
out of the alarm lifecycle with no extra check:
- no finite timeout (K_TICKS_FOREVER): the PM core does not hand the
deadline to the companion, set_alarm() is never called and the WUU
stays unarmed, so the SoC waits for another wakeup source;
- finite timeout: the companion is given an alarm, set_alarm() arms
the WUU so the alarm wakes the core.
Disarming keys off the static "is a wakeup source" condition, not on
whether it armed: for the companion this condition never changes, so
arm and disarm always agree and no stale WUU entry is left behind.
Build-tested tests/subsys/pm/power_mgmt_soc and the s2ram / system_off
samples on frdm_mcxn947.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Add a power domain driver for the BCM283X SoC family, enabling VideoCore
firmware-based power management via the mailbox property channel.
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
cadence_nand_read_page() allocates main and spare buffers before
submitting the read-page command. Free both buffers on every exit path so
repeated reads do not leak host memory.
Signed-off-by: Old Ding <ai.neo.ae86@gmail.com>
lpspi_end_xfer() only clears TCR CONT/CONTC when SPI_HOLD_ON_CS is
absent from the transfer's config, so that consecutive
spi_transceive() calls within a HOLD_ON_CS transaction keep native
(non-GPIO) CS asserted between transfers, as intended.
However, once the caller finishes the whole transaction and calls
spi_release(), those bits were never cleared, leaving native CS
asserted indefinitely - spi_context_unlock_unconditionally() already
force-releases GPIO-based CS via _spi_context_cs_control(ctx, false,
true), but has no way to know about the LPSPI-specific TCR bits for
native CS.
Clear TCR CONT/CONTC directly in spi_lpspi_release() so that
spi_release() actually deasserts native CS as its API contract
implies, matching the existing GPIO CS behavior.
Confirmed on real hardware (FRDM-MCXN947, LPSPI1 native PCS0): CS
previously stayed low indefinitely after the first HOLD_ON_CS
transaction (as used by the Arduino SPI API, which always sets
SPI_HOLD_ON_CS to support multiple transfer() calls per transaction);
with this fix CS correctly returns high after each endTransaction().
Signed-off-by: Tedd OKANO <okano.akifumi@gmail.com>
There is no 'config UART' base definition in the tree; the only
definition was an accidental bare declaration in the
cy8cproto_062_4343w board Kconfig.defconfig, so every
'select UART' resolved against a phantom bool that gates nothing.
- bluetooth: hci: BT_AIROC: drop the select. BT_H4 already selects
BT_UART, which selects SERIAL and UART_INTERRUPT_DRIVEN, so the
H4 transport is fully covered.
- sensor: explorir_m, fcx_mldx5, s3km1110: drop the select. These
drivers already have 'depends on UART_INTERRUPT_DRIVEN', which
requires SERIAL; replacing the select with 'select SERIAL' would
create a Kconfig dependency loop through UART_INTERRUPT_DRIVEN.
- input: ch9350l: drop the select for the same reason (it depends
on SERIAL_SUPPORT_INTERRUPT and selects UART_INTERRUPT_DRIVEN).
- stepper: adi_tmc: STEPPER_ADI_TMC_UART: replace with
'select SERIAL', matching the sibling STEPPER_ADI_TMCM_RS485
symbol, so enabling the UART bus variant actually enables the
serial drivers.
Found by a full-tree Kconfig audit cross-referencing every defined
symbol against its uses.
Assisted-by: Claude:claude-fable-5
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Change the boot-time UART clock divider from /3 to /4 (BCLK 80 MHz ->
20 MHz). The BL61x CAN controller is clocked from the UART peripheral
clock (halved by the SJA1000 internal bit-timing divider), and the
previous 80/3 MHz setting cannot be divided down to any standard CAN
bitrate exactly, causing CAN driver init to fail with -ENOTSUP. A
20 MHz UART clock yields a 10 MHz CAN core clock, which divides evenly
into all standard bitrates.
The UART driver computes its baud divisor from the live divider, so
console operation is unaffected.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Add a classic CAN 2.0 controller driver for the Bouffalo Lab BL61x
(BL616/BL618) SoCs. The ISO11898 peripheral is an NXP SJA1000 compatible
PeliCAN core with 8-bit registers on a 32-bit word stride, so it is
implemented as a thin front-end over the shared CAN_SJA1000 driver.
The controller is clocked from the UART peripheral clock domain (halved
for the SJA1000 internal bit-timing divider) and its TX/RX signals reach
GPIO pads through the UART signal multiplexer, configured via pinctrl.
Signed-off-by: William Markezana <william.markezana@gmail.com>
counter_config_info.freq is uint64_t when COUNTER_64BITS_FREQ is
selected, but counter_mcux_gpt logs it with %u and the ITE it51xxx,
ITE it8xxx2 and Xilinx AXI timer drivers with %d. Any build that
compiles one of these drivers with COUNTER_64BITS_FREQ enabled fails
under -Werror=format=.
Log the frequency with %llu and an explicit cast, which is correct
for both the 32-bit and the 64-bit layout of the field.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Fix up ADC drivers to consistently return -ENOMEM when validation of a
sequence buffer size fails.
Signed-off-by: Pete Johanson <pete.johanson@analog.com>
Adjust the MAX32 and MCUX LPADC drivers to use the new common sequence
buffer validation utility.
Signed-off-by: Pete Johanson <pete.johanson@analog.com>
The configdefault for NET_BUF_ALIGNMENT references DCACHE_LINE_SIZE
unconditionally. On platforms where CACHE_MANAGEMENT is enabled but
CACHE_TYPE is not DCACHE (e.g., EXTERNAL_CACHE for instruction-only
caches), the DCACHE_LINE_SIZE symbol is hidden inside `if DCACHE`
and resolves to 0. Kconfig stores int 0 as an empty string, which
breaks GEN_ABSOLUTE_SYM_KCONFIG and produces an assembler error:
"missing expression".
Add an `if DCACHE` guard and use SDHC_BUFFER_ALIGNMENT for
platforms without DCACHE, which reflects the actual USDHC ADMA2
DMA transfer alignment requirement.
Signed-off-by: Qiankun Li <qiankun.li@nxp.com>
The Kconfig options related to USB common code should be gated by the
STM32_USB_COMMON option. Otherwise, they can appear in Kconfig of builds
where USB is not enabled at all (notably, the options related to logging
configuration were always leaked)
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Keep the timeout calculation in 64-bit arithmetic through the hardware
range validation so that oversized timeouts are rejected instead of being
truncated.
Signed-off-by: Kevin Wang <kevinwang821020@gmail.com>
vs1838b_init() used data_input.port on a pointer, which does not
compile when the driver is built. Use data_input->port.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Add Ethernet driver for the Broadcom GENET MAC controller
found on the BCM2711 SoC, targeting the rpi_4b board.
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
Add MDIO driver for the Broadcom GENET MDIO controller,
used to access the PHY attached to the BCM2711 GENET MAC.
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
Add support for the GNSS receiver integrated in the
Ericsson F5521gw (HP HS2340) WWAN module.
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
Enable Automatic pad/CRC stripping (APCS) for
packets that have a ethertype/lenght <= 1500.
The other option (CSTF) only strips the
FCS for a ethertype greater than 0x0600 (1536).
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
