STM32F7xx series shares several DMA configurations with
the other platforms. These changes aim to enable platform
specific DMA configuration and align them to other platforms.
Signed-off-by: Mario Paja <mariopaja@hotmail.com>
1.Add "mux-1-dc-0-div" and "mux-2-dc-0-div" property
in mc_cgm device tree for STM clock divider setting
and set these properties in frdm_mcxe31b.dts
2.Enable STM peripheral clock in mc_cgm_clock_control_on
function
3.Support to get STM frequency from mc_cgm_get_subsys_rate
function
4.Configure STM clock in mc_cgm_init function
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
If the framebuffer size is same as the full screen, full refresh
is applied. Otherwise, partial refresh is applied.
Signed-off-by: Winteri Wang <dongjie.wang@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Signed-off-by: Ruoshan Shi <ruoshan.shi@nxp.com>
Added waveshare dsi panel driver. It is on I2C bus.
Signed-off-by: Winteri Wang <dongjie.wang@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Signed-off-by: Ruoshan Shi <ruoshan.shi@nxp.com>
Added mcux_lcdifv3 driver and enabled runtime mmio configuration.
Signed-off-by: Winteri Wang <dongjie.wang@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Signed-off-by: Ruoshan Shi <ruoshan.shi@nxp.com>
Setup most clocks with common_clock_set_freq().
PLL and mux are preset.
Signed-off-by: Winteri Wang <dongjie.wang@nxp.com>
Signed-off-by: Ruoshan Shi <ruoshan.shi@nxp.com>
The LPTIM timer driver previously had hardcoded assumptions about
using LPTIM1 or LPTIM3, which prevented it from working with other
LPTIM instances like LPTIM2, LPTIM4, LPTIM5, and LPTIM6.
This change makes the driver work with any LPTIM instance by:
1. Adding lptim_enable_autonomous_mode() function that dynamically
detects which LPTIM instance is in use and enables autonomous
mode for instances that support it (LPTIM1, LPTIM3, LPTIM4).
LPTIM2, LPTIM5, LPTIM6 do not support autonomous mode.
2. Adding lptim_freeze_during_debug() function that handles debug
freeze configuration for all LPTIM instances across different
APB buses:
- LPTIM1: APB1_GRP1, APB3_GRP1, or APB7_GRP1
- LPTIM2: APB1_GRP1, APB1_GRP2, APB3_GRP1, or APB4_GRP1
- LPTIM3: APB1_GRP2, APB3_GRP1, or APB4_GRP1
- LPTIM4: APB3_GRP1 or APB4_GRP1
- LPTIM5: APB3_GRP1
- LPTIM6: APB3_GRP1
Both functions use DT_REG_ADDR() to compare the base address of the
configured LPTIM instance at compile time, ensuring zero runtime
overhead.
Tested on STM32U5A5 with all four LPTIM instances (LPTIM1-4).
Signed-off-by: Kamil Krzyżanowski <kamnxt@kamnxt.com>
The driver internally uses semaphores which are only available if
CONFIG_MULTITHREADING is enabled in the build.
Signed-off-by: Valerio Setti <vsetti@baylibre.com>
Enable Link-Up and Link-Down interrupts. On the interrupt handling
the monitor work is scheduled to update the link status and calling
corresponding callback routine.
Signed-off-by: Tony Han <tony.han@microchip.com>
Add support for KSZ9131 (Gigabit Ethernet Transceiver with RGMII Support).
As first starter, 100MBit/s mode is tested.
https://www.microchip.com/en-us/product/ksz9131
Signed-off-by: Tony Han <tony.han@microchip.com>
Some variants of the PCA953x family support pull-up / pull-down
resistors through registers 0x43 and 0x44 (mostly the TCAL9538 variant).
We already support input latching and interrupt masking (which is also
only present on a few variants), so let's also add support for pull-up
and pull-down resistors.
The feature can be enabled with the has-pud property in the device tree.
Signed-off-by: Marco Widmer <marco.widmer@bytesatwork.ch>
Add initial support for the AD4170-4, AD4190-4, and AD4195-4 24-bit
ADCs, including reference selection, programmable gain amplifier, ADC
conversion modes, configurable analog inputs, filter settings, and both
bipolar and unipolar operation. Supports internal and external buffered
references, and operation from a 4.75-5.25V analog supply and a
1.7-5.25V digital supply.
Signed-off-by: Kim Seer Paller <kimseer.paller@analog.com>
The Xilinx Zynq 7000 I2C controller has the following bugs:
- completion indication is not given to the driver at the end of
a read/receive transfer with HOLD bit set.
- Invalid read transaction are generated on the bus when HW timeout
condition occurs with HOLD bit set.
- If the delay between address register write and
control register write in cdns_i2c_mrecv function is more, the xfer size
register rolls over and controller is stuck.
As a result of the above, this patch disallows message transfers with
a repeated start condition following a read operation. Also disables
interrupts between the address register write and control register write
during message reception, to prevent transfer size register rollover.
Signed-off-by: Simon Maurer <mail@maurer.systems>
Add rough estimate of a worth case H264 output size.
The video_estimate_fmt_size would need more information
such as quality, profile in order to give a better
estimate for each formats so for the time being just
stick to 16bpp based size, same as for JPEG.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Addition of a helper function which takes care of dequeue
from a source video device and queue into a sink video device.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Section 4.3.7.3.6 of the I3C v1.2 specification states that a value of
0 for the max ibi size indicates an unlimited payload size. Set it to
the max it can be configured for.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
Now that the ADC prescaler are set within the driver using the clock
system, remove the specific setting of the prescaler from the clock driver.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Some series like F1, F3, N6 and U3 use an ADC prescaler defined in the RCC.
Instead of adding specific properties in the RCC driver, use the secondary
clock system to configure the prescaler.
The ADC driver now configures the clocks depending on their presence and
their name. Three clocks can be defined:
- the register clock (mandatory for all series)
- the kernel clock (depends on series)
- the prescaler value (depends on series)
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add support for audio_auxpll clock source as an alternative to audiopll
in the i2s_nrf_tdm driver. This enables TDM functionality on platforms
that use the auxiliary PLL for audio clocking.
- Add audio_auxpll node detection and configuration
- Update clock management to support both audiopll and audio_auxpll
- Add build assertions for supported frequency configurations
Signed-off-by: Erdem Simsek <erdem.simsek@nordicsemi.no>
Use of uart_nrfx_uarte2 driver was deprecated before 4.1 release
and now can be removed.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
All the clocks names on SiWx91x follow the pattern "SIWX91X_CLK_xxx".
SIWX91X_ADC_CLK was an exception.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Add depends on SOC_SERIES_STM32N6X to
PTP_CLOCK_STM32_HAL in order to use PTP on the STM32N6 series.
Signed-off-by: Julien Racki <julien.racki-ext@st.com>
Use LL_USART_DisableDMAReq_RX to disable UART RX DMA requests.
This should be called before entering shutdown mode.
Force to use UART_STM32U5_ERRATA_DMAT_LOWPOWER
when POWEROFF is selected. This ensure the system to shut down
properly instead of hanging due to DMA staying active.
Signed-off-by: Khaoula Bidani <khaoula.bidani-ext@st.com>
Signed-off-by: Julien Racki <julien.racki-ext@st.com>
It is possible for usbd_disable() to be called when the core is
hibernated. When done so, the USB stack will attempt to deactivate all
the endpoints. Because the core is hibernated, register reads are
really undefined. This can lead to udc_dwc2_ep_deactivate() not calling
udc_dwc2_ep_disable() which will leave struct udc_ep_config busy flag
set.
When endpoint 0x00 busy flag is left to true, the driver won't allocate
buffer to receive SETUP data which is mandatory in Buffer DMA mode. This
leads to essentially dead device after reconnect, because the device
will not respond to any control transfers.
Solve the issue by modifying backup register value instead of real one
when endpoint is deactivated while core is hibernated.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
For all STM32 drivers and SoC, replace the MODIFY_REG macro (defined in
the STM32 HAL) by stm32_reg_modify_bits defined in Zephyr.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
For all STM32 drivers and SoC, replace the READ_REG macro and the
LL_xxx_ReadReg functions (defined in the STM32 HAL) by
stm32_reg_read defined in Zephyr.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
For all STM32 drivers and SoC, replace the WRITE_REG macro and the
LL_xxx_WriteReg functions (defined in the STM32 HAL) by
stm32_reg_write defined in Zephyr.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
For all STM32 drivers and SoC, replace the READ_BIT macro (defined in
the STM32 HAL) by stm32_reg_read_bits.
Fixes some cases where the return value was tested like a boolean
despite not being one.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
