drivers: dma: fix the WCH DMA transfer width
The driver treats the `source_data_size` and `dest_data_size` as a width in bits and converts 8 bits to 1, 16 bits to 2, and 32 bits to 3. This should be a width in bytes with 1 byte mapping to 0, 2 bytes to 1, and 4 bytes to 3. Note that this preserves the current behaviour of silently accepting invalid transfer bit widths. Signed-off-by: Michael Hope <michaelh@juju.nz>
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c37abf115d
1 changed files with 20 additions and 8 deletions
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@ -89,6 +89,22 @@ static int dma_wch_init(const struct device *dev)
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return 0;
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}
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/* Coverts a transfer width in bytes to the corresponding bitfield */
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static uint16_t dma_wch_width_index(uint32_t bytes)
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{
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switch (bytes) {
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case 1:
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return 0;
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case 2:
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return 1;
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case 4:
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return 2;
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default:
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/* Return a bad but safe value rather than validate */
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return 0;
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}
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}
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static int dma_wch_config(const struct device *dev, uint32_t ch, struct dma_config *dma_cfg)
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{
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const struct dma_wch_config *config = dev->config;
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@ -146,10 +162,8 @@ static int dma_wch_config(const struct device *dev, uint32_t ch, struct dma_conf
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cfgr |= dma_cfg->channel_priority * DMA_CFGR1_PL_0;
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if (dma_cfg->channel_direction == MEMORY_TO_PERIPHERAL) {
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cfgr |= dma_width_index(dma_cfg->source_data_size / BITS_PER_BYTE) *
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DMA_CFGR1_MSIZE_0;
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cfgr |= dma_width_index(dma_cfg->dest_data_size / BITS_PER_BYTE) *
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DMA_CFGR1_PSIZE_0;
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cfgr |= dma_wch_width_index(dma_cfg->source_data_size) * DMA_CFGR1_MSIZE_0;
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cfgr |= dma_wch_width_index(dma_cfg->dest_data_size) * DMA_CFGR1_PSIZE_0;
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cfgr |= (dma_cfg->head_block->dest_addr_adj == DMA_ADDR_ADJ_INCREMENT)
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? DMA_CFGR1_PINC
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@ -158,10 +172,8 @@ static int dma_wch_config(const struct device *dev, uint32_t ch, struct dma_conf
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? DMA_CFGR1_MINC
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: 0;
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} else {
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cfgr |= dma_width_index(dma_cfg->source_data_size / BITS_PER_BYTE) *
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DMA_CFGR1_PSIZE_0;
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cfgr |= dma_width_index(dma_cfg->dest_data_size / BITS_PER_BYTE) *
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DMA_CFGR1_MSIZE_0;
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cfgr |= dma_wch_width_index(dma_cfg->source_data_size) * DMA_CFGR1_PSIZE_0;
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cfgr |= dma_wch_width_index(dma_cfg->dest_data_size) * DMA_CFGR1_MSIZE_0;
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cfgr |= (dma_cfg->head_block->dest_addr_adj == DMA_ADDR_ADJ_INCREMENT)
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? DMA_CFGR1_MINC
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