drivers: clock_control: Add STM32U3XX clock support
add clock support for STM32U3X SoC series. Signed-off-by: Khaoula Bidani <khaoula.bidani-ext@st.com>
This commit is contained in:
Khaoula Bidani
Daniel DeGrasse
parent
5673dc162f
commit
6ac4b20e2b
2 changed files with 652 additions and 0 deletions
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@ -75,6 +75,8 @@ elseif(CONFIG_SOC_SERIES_STM32H5X)
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zephyr_library_sources(clock_stm32_ll_h5.c)
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elseif(CONFIG_SOC_SERIES_STM32N6X)
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zephyr_library_sources(clock_stm32_ll_n6.c)
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elseif(CONFIG_SOC_SERIES_STM32U3X)
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zephyr_library_sources(clock_stm32_ll_u3.c)
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elseif(CONFIG_SOC_SERIES_STM32U5X)
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zephyr_library_sources(clock_stm32_ll_u5.c)
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elseif(CONFIG_SOC_SERIES_STM32WB0X)
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650
drivers/clock_control/clock_stm32_ll_u3.c
Normal file
650
drivers/clock_control/clock_stm32_ll_u3.c
Normal file
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@ -0,0 +1,650 @@
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/*
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* Copyright (c) 2025 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <soc.h>
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#include <stm32_ll_bus.h>
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#include <stm32_ll_pwr.h>
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#include <stm32_ll_rcc.h>
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#include <stm32_ll_utils.h>
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#include <stm32_ll_system.h>
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#include <zephyr/arch/cpu.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/clock_control/stm32_clock_control.h>
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#include <zephyr/sys/util.h>
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/* Macros to fill up prescaler values */
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#define ahb_prescaler(v) CONCAT(LL_RCC_HCLK_SYSCLK_DIV_, v)
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#define apb1_prescaler(v) CONCAT(LL_RCC_APB1_HCLK_DIV_, v)
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#define apb2_prescaler(v) CONCAT(LL_RCC_APB2_HCLK_DIV_, v)
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#define apb3_prescaler(v) CONCAT(LL_RCC_APB3_HCLK_DIV_, v)
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static uint32_t get_msis_frequency(void)
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{
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uint32_t frequency = MSIRC1_VALUE;
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if (LL_RCC_MSIS_GetClockSource() == LL_RCC_MSIS_CLOCK_SOURCE_RC0) {
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frequency = MSIRC0_VALUE;
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}
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switch (LL_RCC_MSIS_GetClockDivision()) {
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case LL_RCC_MSIS_CLOCK_SOURCE_RC_DIV_2:
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return frequency / 2U;
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case LL_RCC_MSIS_CLOCK_SOURCE_RC_DIV_4:
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return frequency / 4U;
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case LL_RCC_MSIS_CLOCK_SOURCE_RC_DIV_8:
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return frequency / 8U;
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case LL_RCC_MSIS_CLOCK_SOURCE_RC_DIV_1:
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return frequency;
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default:
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return 0;
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}
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}
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static uint32_t get_msik_frequency(void)
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{
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uint32_t frequency = MSIRC1_VALUE;
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if (LL_RCC_MSIK_GetClockSource() == LL_RCC_MSIK_CLOCK_SOURCE_RC0) {
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frequency = MSIRC0_VALUE;
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}
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switch (LL_RCC_MSIK_GetClockDivision()) {
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case LL_RCC_MSIK_CLOCK_SOURCE_RC_DIV_2:
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return frequency / 2U;
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case LL_RCC_MSIK_CLOCK_SOURCE_RC_DIV_4:
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return frequency / 4U;
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case LL_RCC_MSIK_CLOCK_SOURCE_RC_DIV_8:
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return frequency / 8U;
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case LL_RCC_MSIK_CLOCK_SOURCE_RC_DIV_1:
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return frequency;
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default:
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return 0;
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}
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}
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static uint32_t get_startup_frequency(void)
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{
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switch (LL_RCC_GetSysClkSource()) {
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case LL_RCC_SYS_CLKSOURCE_STATUS_MSIS:
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return get_msis_frequency();
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case LL_RCC_SYS_CLKSOURCE_STATUS_HSI16:
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return STM32_HSI_FREQ;
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case LL_RCC_SYS_CLKSOURCE_STATUS_HSE:
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return STM32_HSE_FREQ;
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default:
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__ASSERT(0, "Unexpected startup freq");
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return 0;
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}
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}
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static uint32_t get_sysclk_frequency(void)
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{
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#if defined(STM32_SYSCLK_SRC_MSIS)
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return get_msis_frequency();
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#elif defined(STM32_SYSCLK_SRC_HSE)
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return STM32_HSE_FREQ;
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#elif defined(STM32_SYSCLK_SRC_HSI)
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return STM32_HSI_FREQ;
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#else
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__ASSERT(0, "No SYSCLK Source configured");
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return 0;
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#endif
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}
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/** @brief Verifies clock is part of active clock configuration */
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static int enabled_clock(uint32_t src_clk)
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{
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if ((src_clk == STM32_SRC_SYSCLK) ||
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(src_clk == STM32_SRC_HCLK) ||
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(src_clk == STM32_SRC_PCLK1) ||
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(src_clk == STM32_SRC_PCLK2) ||
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(src_clk == STM32_SRC_PCLK3) ||
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((src_clk == STM32_SRC_HSE) && IS_ENABLED(STM32_HSE_ENABLED)) ||
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((src_clk == STM32_SRC_HSI16) && IS_ENABLED(STM32_HSI_ENABLED)) ||
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((src_clk == STM32_SRC_HSI48) && IS_ENABLED(STM32_HSI48_ENABLED)) ||
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((src_clk == STM32_SRC_LSE) && IS_ENABLED(STM32_LSE_ENABLED)) ||
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((src_clk == STM32_SRC_LSI) && IS_ENABLED(STM32_LSI_ENABLED)) ||
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((src_clk == STM32_SRC_MSIS) && IS_ENABLED(STM32_MSIS_ENABLED)) ||
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((src_clk == STM32_SRC_MSIK) && IS_ENABLED(STM32_MSIK_ENABLED))) {
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return 0;
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}
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return -ENOTSUP;
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}
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static int stm32_clock_control_on(const struct device *dev, clock_control_subsys_t sub_system)
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{
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struct stm32_pclken *pclken = (struct stm32_pclken *)sub_system;
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volatile int temp;
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ARG_UNUSED(dev);
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if (!IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX)) {
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/* Attempt to toggle a wrong periph clock bit */
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return -ENOTSUP;
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}
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sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, pclken->enr);
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/* Delay after enabling the clock, to allow it to become active */
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temp = sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus);
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UNUSED(temp);
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return 0;
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}
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static int stm32_clock_control_off(const struct device *dev, clock_control_subsys_t sub_system)
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{
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struct stm32_pclken *pclken = (struct stm32_pclken *)sub_system;
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ARG_UNUSED(dev);
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if (!IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX)) {
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/* Attempt to toggle a wrong periph clock bit */
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return -ENOTSUP;
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}
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sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, pclken->enr);
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return 0;
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}
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static int stm32_clock_control_configure(const struct device *dev,
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clock_control_subsys_t sub_system,
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void *data)
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{
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struct stm32_pclken *pclken = (struct stm32_pclken *)sub_system;
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int err;
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ARG_UNUSED(dev);
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ARG_UNUSED(data);
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err = enabled_clock(pclken->bus);
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if (err < 0) {
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/* Attempt to configure a src clock not available or not valid */
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return err;
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}
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sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr),
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STM32_DT_CLKSEL_MASK_GET(pclken->enr) <<
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STM32_DT_CLKSEL_SHIFT_GET(pclken->enr));
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sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr),
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STM32_DT_CLKSEL_VAL_GET(pclken->enr) <<
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STM32_DT_CLKSEL_SHIFT_GET(pclken->enr));
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return 0;
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}
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static int stm32_clock_control_get_subsys_rate(const struct device *dev,
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clock_control_subsys_t sys,
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uint32_t *rate)
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{
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struct stm32_pclken *pclken = (struct stm32_pclken *)sys;
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/*
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* Get AHB Clock (= SystemCoreClock = SYSCLK/prescaler)
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* SystemCoreClock is preferred to CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
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* since it will be updated after clock configuration and hence
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* more likely to contain actual clock speed
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*/
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uint32_t ahb_clock = SystemCoreClock;
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uint32_t apb1_clock = ahb_clock / STM32_APB1_PRESCALER;
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uint32_t apb2_clock = ahb_clock / STM32_APB2_PRESCALER;
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uint32_t apb3_clock = ahb_clock / STM32_APB3_PRESCALER;
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ARG_UNUSED(dev);
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switch (pclken->bus) {
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case STM32_CLOCK_BUS_AHB1:
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case STM32_CLOCK_BUS_AHB1_2:
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case STM32_CLOCK_BUS_AHB2:
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case STM32_CLOCK_BUS_AHB2_2:
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case STM32_SRC_HCLK:
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*rate = ahb_clock;
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break;
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case STM32_CLOCK_BUS_APB1:
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case STM32_CLOCK_BUS_APB1_2:
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case STM32_SRC_PCLK1:
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*rate = apb1_clock;
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break;
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case STM32_CLOCK_BUS_APB2:
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case STM32_SRC_PCLK2:
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*rate = apb2_clock;
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break;
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case STM32_CLOCK_BUS_APB3:
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case STM32_SRC_PCLK3:
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*rate = apb3_clock;
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break;
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case STM32_SRC_SYSCLK:
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*rate = get_sysclk_frequency();
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break;
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#if defined(STM32_HSI_ENABLED)
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case STM32_SRC_HSI16:
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*rate = STM32_HSI_FREQ;
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break;
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#endif /* STM32_HSI_ENABLED */
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#if defined(STM32_MSIS_ENABLED)
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case STM32_SRC_MSIS:
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*rate = get_msis_frequency();
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break;
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#endif /* STM32_MSIS_ENABLED */
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#if defined(STM32_MSIK_ENABLED)
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case STM32_SRC_MSIK:
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*rate = get_msik_frequency();
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break;
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#endif /* STM32_MSIK_ENABLED */
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#if defined(STM32_HSE_ENABLED)
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case STM32_SRC_HSE:
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*rate = STM32_HSE_FREQ;
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break;
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#endif /* STM32_HSE_ENABLED */
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#if defined(STM32_LSE_ENABLED)
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case STM32_SRC_LSE:
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*rate = STM32_LSE_FREQ;
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break;
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#endif /* STM32_LSE_ENABLED */
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#if defined(STM32_LSI_ENABLED)
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case STM32_SRC_LSI:
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*rate = STM32_LSI_FREQ;
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break;
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#endif /* STM32_LSI_ENABLED */
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#if defined(STM32_HSI48_ENABLED)
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case STM32_SRC_HSI48:
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*rate = STM32_HSI48_FREQ;
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break;
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#endif /* STM32_HSI48_ENABLED */
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default:
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return -ENOTSUP;
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}
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if (pclken->div) {
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*rate /= pclken->div + 1;
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}
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return 0;
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}
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static enum clock_control_status stm32_clock_control_get_status(const struct device *dev,
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clock_control_subsys_t sub_system)
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{
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struct stm32_pclken *pclken = (struct stm32_pclken *)sub_system;
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ARG_UNUSED(dev);
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if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX)) {
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/* Gated clocks */
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if ((sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus) & pclken->enr)
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== pclken->enr) {
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return CLOCK_CONTROL_STATUS_ON;
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} else {
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return CLOCK_CONTROL_STATUS_OFF;
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}
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} else {
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/* Domain clock sources */
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if (enabled_clock(pclken->bus) == 0) {
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return CLOCK_CONTROL_STATUS_ON;
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} else {
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return CLOCK_CONTROL_STATUS_OFF;
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}
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}
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}
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static DEVICE_API(clock_control, stm32_clock_control_api) = {
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.on = stm32_clock_control_on,
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.off = stm32_clock_control_off,
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.get_rate = stm32_clock_control_get_subsys_rate,
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.get_status = stm32_clock_control_get_status,
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.configure = stm32_clock_control_configure,
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};
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static void set_regu_voltage(uint32_t hclk_freq)
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{
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if (hclk_freq < MHZ(48)) {
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LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE2);
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} else {
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LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1);
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}
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}
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static void enable_epod_booster(void)
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{
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LL_RCC_SetEPODBoosterClkSource(LL_RCC_EPODBOOSTCLKSRCE_MSIS);
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LL_RCC_SetEPODBoosterClkPrescaler(LL_RCC_EPODBOOSTCLKPRESCAL_1);
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LL_PWR_EnableEPODBooster();
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while (LL_PWR_IsActiveFlag_BOOST() == 0) {
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}
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}
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static void configure_clock_with_calibration(int range)
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{
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LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_MSIS);
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/* Wait till System clock is ready */
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while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_MSIS) {
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}
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LL_RCC_SetAHBPrescaler(LL_RCC_HCLK_SYSCLK_DIV_1);
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LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_HCLK_DIV_1);
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LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_HCLK_DIV_1);
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LL_RCC_SetAPB3Prescaler(LL_RCC_APB3_HCLK_DIV_1);
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BUILD_ASSERT(STM32_LSE_ENABLED || !IS_ENABLED(STM32_MSIK_ENABLED),
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"MSIK requires LSE clock to be enabled for auto-calibration");
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BUILD_ASSERT(STM32_LSE_ENABLED || !IS_ENABLED(STM32_MSIS_ENABLED),
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"MSIS requires LSE clock to be enabled for auto-calibration");
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if (IN_RANGE(range, 0, 3)) {
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/*
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* LSE or HSE must be enabled and ready before selecting
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* this oscillator as MSIRC0 input clock for Range [0 3]
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*/
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if (LL_RCC_LSE_IsEnabled() != 0U && LL_RCC_LSE_IsReady() != 0U) {
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LL_RCC_MSI_RC0_SetPLLInputClk(LL_RCC_MSIPLL0SEL_LSE);
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} else if (LL_RCC_HSE_IsEnabled() != 0U && LL_RCC_HSE_IsReady() != 0U) {
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LL_RCC_MSI_RC0_SetPLLInputClk(LL_RCC_MSIPLL0SEL_HSE_OR_HSEDIV2);
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}
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LL_RCC_MSI_RC0_PLLmode_Enable();
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while (LL_RCC_MSI_RC0_PLLmode_IsEnabled() == 0U) {
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}
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} else {
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/*
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* LSE or HSE must be enabled and ready before selecting
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* this oscillator as MSIRC1 input clock for Range [4 7]
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*/
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if (LL_RCC_LSE_IsEnabled() != 0U && LL_RCC_LSE_IsReady() != 0U) {
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LL_RCC_MSI_RC1_SetPLLInputClk(LL_RCC_MSIPLL1SEL_LSE);
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} else if (LL_RCC_HSE_IsEnabled() != 0U && LL_RCC_HSE_IsReady() != 0U) {
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LL_RCC_MSI_RC1_SetPLLInputClk(LL_RCC_MSIPLL1SEL_HSE_OR_HSEDIV2);
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}
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LL_RCC_MSI_RC1_PLLmode_Enable();
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while (LL_RCC_MSI_RC1_PLLmode_IsEnabled() == 0U) {
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}
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}
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}
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static void set_up_fixed_clock_sources(void)
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{
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if (IS_ENABLED(STM32_HSE_ENABLED)) {
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/* Check if need to enable HSE bypass feature or not */
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if (IS_ENABLED(STM32_HSE_BYPASS)) {
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LL_RCC_HSE_EnableBypass();
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} else {
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LL_RCC_HSE_DisableBypass();
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}
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/* Enable HSE */
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LL_RCC_HSE_Enable();
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while (LL_RCC_HSE_IsReady() == 0) {
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/* Wait for HSE ready */
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}
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}
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if (IS_ENABLED(STM32_HSI_ENABLED)) {
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/* Enable HSI if not enabled */
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if (LL_RCC_HSI_IsReady() == 0) {
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/* Enable HSI */
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LL_RCC_HSI_Enable();
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while (LL_RCC_HSI_IsReady() == 0) {
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/* Wait for HSI ready */
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}
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}
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}
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if (IS_ENABLED(STM32_LSE_ENABLED)) {
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/* N.B.: PWR clock has been enabled by SoC init hook */
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if (LL_PWR_IsEnabledBkUpAccess() == 0U) {
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/* Enable write access to Backup domain */
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LL_PWR_EnableBkUpAccess();
|
||||
while (LL_PWR_IsEnabledBkUpAccess() == 0U) {
|
||||
/* Wait for Backup domain access */
|
||||
}
|
||||
}
|
||||
|
||||
/* Configure driving capability */
|
||||
LL_RCC_LSE_SetDriveCapability(STM32_LSE_DRIVING << RCC_BDCR_LSEDRV_Pos);
|
||||
|
||||
if (IS_ENABLED(STM32_LSE_BYPASS)) {
|
||||
/* Configure LSE bypass */
|
||||
LL_RCC_LSE_EnableBypass();
|
||||
}
|
||||
|
||||
/* Enable LSE Oscillator */
|
||||
LL_RCC_LSE_Enable();
|
||||
/* Wait for LSE ready */
|
||||
while (LL_RCC_LSE_IsReady() == 0U) {
|
||||
}
|
||||
|
||||
/* Enable LSESYS additionally */
|
||||
LL_RCC_LSE_EnablePropagation();
|
||||
/* Enforce BackUp domain access is disabled after clock initialization */
|
||||
while (LL_RCC_LSE_IsPropagationReady() == 0U) {
|
||||
}
|
||||
LL_PWR_DisableBkUpAccess();
|
||||
}
|
||||
|
||||
if (IS_ENABLED(STM32_MSIS_ENABLED)) {
|
||||
/* Set MSIS Range */
|
||||
LL_FLASH_SetLatency(LL_FLASH_LATENCY_2);
|
||||
while (LL_FLASH_GetLatency() != LL_FLASH_LATENCY_2) {
|
||||
}
|
||||
|
||||
if (IN_RANGE(STM32_MSIS_RANGE, 0, 3)) {
|
||||
LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1);
|
||||
} else {
|
||||
LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE2);
|
||||
}
|
||||
|
||||
enable_epod_booster();
|
||||
|
||||
if (IN_RANGE(STM32_MSIS_RANGE, 0, 3)) {
|
||||
/* Range 0-3 uses RC0 as the clock source */
|
||||
LL_RCC_MSIS_SetClockSource(LL_RCC_MSIS_CLOCK_SOURCE_RC0);
|
||||
switch (STM32_MSIS_RANGE) {
|
||||
case 0:
|
||||
LL_RCC_MSIS_SetClockDivision(LL_RCC_MSIS_CLOCK_SOURCE_RC_DIV_1);
|
||||
break;
|
||||
case 1:
|
||||
LL_RCC_MSIS_SetClockDivision(LL_RCC_MSIS_CLOCK_SOURCE_RC_DIV_2);
|
||||
break;
|
||||
case 2:
|
||||
LL_RCC_MSIS_SetClockDivision(LL_RCC_MSIS_CLOCK_SOURCE_RC_DIV_4);
|
||||
break;
|
||||
case 3:
|
||||
LL_RCC_MSIS_SetClockDivision(LL_RCC_MSIS_CLOCK_SOURCE_RC_DIV_8);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
/* Range 4-7 uses RC1 as the clock source */
|
||||
LL_RCC_MSIS_SetClockSource(LL_RCC_MSIS_CLOCK_SOURCE_RC1);
|
||||
switch (STM32_MSIS_RANGE) {
|
||||
case 4:
|
||||
LL_RCC_MSIS_SetClockDivision(LL_RCC_MSIS_CLOCK_SOURCE_RC_DIV_1);
|
||||
break;
|
||||
case 5:
|
||||
LL_RCC_MSIS_SetClockDivision(LL_RCC_MSIS_CLOCK_SOURCE_RC_DIV_2);
|
||||
break;
|
||||
case 6:
|
||||
LL_RCC_MSIS_SetClockDivision(LL_RCC_MSIS_CLOCK_SOURCE_RC_DIV_4);
|
||||
break;
|
||||
case 7:
|
||||
LL_RCC_MSIS_SetClockDivision(LL_RCC_MSIS_CLOCK_SOURCE_RC_DIV_8);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
}
|
||||
LL_RCC_MSI_SetMSIxClockRange();
|
||||
/*
|
||||
* For stm32u3 LSE or HSE must be enabled and ready before
|
||||
* selecting this oscillator as MSIRC0/MSIRC1 input clock.
|
||||
*/
|
||||
/* Enable MSIS */
|
||||
LL_RCC_MSIS_Enable();
|
||||
while (LL_RCC_MSIS_IsReady() == 0U) {
|
||||
}
|
||||
|
||||
configure_clock_with_calibration(STM32_MSIS_RANGE);
|
||||
}
|
||||
|
||||
if (IS_ENABLED(STM32_MSIK_ENABLED)) {
|
||||
/* Set MSIK Range */
|
||||
LL_FLASH_SetLatency(LL_FLASH_LATENCY_2);
|
||||
while (LL_FLASH_GetLatency() != LL_FLASH_LATENCY_2) {
|
||||
}
|
||||
|
||||
if (IN_RANGE(STM32_MSIK_RANGE, 0, 3)) {
|
||||
LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1);
|
||||
} else {
|
||||
LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE2);
|
||||
}
|
||||
|
||||
enable_epod_booster();
|
||||
|
||||
if (IN_RANGE(STM32_MSIK_RANGE, 0, 3)) {
|
||||
/* Range 0-3 uses RC0 as the clock source */
|
||||
LL_RCC_MSIK_SetClockSource(LL_RCC_MSIK_CLOCK_SOURCE_RC0);
|
||||
switch (STM32_MSIK_RANGE) {
|
||||
case 0:
|
||||
LL_RCC_MSIK_SetClockDivision(LL_RCC_MSIK_CLOCK_SOURCE_RC_DIV_1);
|
||||
break;
|
||||
case 1:
|
||||
LL_RCC_MSIK_SetClockDivision(LL_RCC_MSIK_CLOCK_SOURCE_RC_DIV_2);
|
||||
break;
|
||||
case 2:
|
||||
LL_RCC_MSIK_SetClockDivision(LL_RCC_MSIK_CLOCK_SOURCE_RC_DIV_4);
|
||||
break;
|
||||
case 3:
|
||||
LL_RCC_MSIK_SetClockDivision(LL_RCC_MSIK_CLOCK_SOURCE_RC_DIV_8);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
/* Range 4-7 uses RC1 as the clock source */
|
||||
LL_RCC_MSIK_SetClockSource(LL_RCC_MSIK_CLOCK_SOURCE_RC1);
|
||||
switch (STM32_MSIK_RANGE) {
|
||||
case 4:
|
||||
LL_RCC_MSIK_SetClockDivision(LL_RCC_MSIK_CLOCK_SOURCE_RC_DIV_1);
|
||||
break;
|
||||
case 5:
|
||||
LL_RCC_MSIK_SetClockDivision(LL_RCC_MSIK_CLOCK_SOURCE_RC_DIV_2);
|
||||
break;
|
||||
case 6:
|
||||
LL_RCC_MSIK_SetClockDivision(LL_RCC_MSIK_CLOCK_SOURCE_RC_DIV_4);
|
||||
break;
|
||||
case 7:
|
||||
LL_RCC_MSIK_SetClockDivision(LL_RCC_MSIK_CLOCK_SOURCE_RC_DIV_8);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
}
|
||||
LL_RCC_MSI_SetMSIxClockRange();
|
||||
/*
|
||||
* For stm32u3 LSE or HSE must be enabled and ready before
|
||||
* selecting this oscillator as MSIRC0/MSIRC1 input clock.
|
||||
*/
|
||||
LL_RCC_MSIK_Enable();
|
||||
while (LL_RCC_MSIK_IsReady() == 0U) {
|
||||
}
|
||||
|
||||
configure_clock_with_calibration(STM32_MSIK_RANGE);
|
||||
}
|
||||
|
||||
if (IS_ENABLED(STM32_LSI_ENABLED)) {
|
||||
if (LL_PWR_IsEnabledBkUpAccess() == 0U) {
|
||||
/* Enable write access to Backup domain */
|
||||
LL_PWR_EnableBkUpAccess();
|
||||
while (LL_PWR_IsEnabledBkUpAccess() == 0U) {
|
||||
/* Wait for Backup domain access */
|
||||
}
|
||||
}
|
||||
|
||||
/* Enable LSI oscillator */
|
||||
LL_RCC_LSI_Enable();
|
||||
while (LL_RCC_LSI_IsReady() == 0) {
|
||||
}
|
||||
|
||||
LL_PWR_DisableBkUpAccess();
|
||||
}
|
||||
|
||||
if (IS_ENABLED(STM32_HSI48_ENABLED)) {
|
||||
LL_RCC_HSI48_Enable();
|
||||
while (LL_RCC_HSI48_IsReady() == 0) {
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
int stm32_clock_control_init(const struct device *dev)
|
||||
{
|
||||
uint32_t old_hclk_freq;
|
||||
|
||||
ARG_UNUSED(dev);
|
||||
|
||||
/* Current hclk value */
|
||||
old_hclk_freq = __LL_RCC_CALC_HCLK_FREQ(get_startup_frequency(), LL_RCC_GetAHBPrescaler());
|
||||
|
||||
/* Set voltage regulator to comply with targeted system frequency */
|
||||
set_regu_voltage(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
|
||||
|
||||
/* Set flash latency */
|
||||
/* If freq increases, set flash latency before any clock setting */
|
||||
if (old_hclk_freq < CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC) {
|
||||
LL_SetFlashLatency(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
|
||||
}
|
||||
|
||||
/* Set up individual enabled clocks */
|
||||
set_up_fixed_clock_sources();
|
||||
|
||||
/* Set peripheral buses prescalers */
|
||||
LL_RCC_SetAHBPrescaler(ahb_prescaler(STM32_AHB_PRESCALER));
|
||||
LL_RCC_SetAPB1Prescaler(apb1_prescaler(STM32_APB1_PRESCALER));
|
||||
LL_RCC_SetAPB2Prescaler(apb2_prescaler(STM32_APB2_PRESCALER));
|
||||
LL_RCC_SetAPB3Prescaler(apb3_prescaler(STM32_APB3_PRESCALER));
|
||||
|
||||
#ifdef STM32_SYSCLK_SRC_HSE
|
||||
/* Set HSE as SYSCLCK source */
|
||||
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSE);
|
||||
while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSE) {
|
||||
}
|
||||
#elif defined(STM32_SYSCLK_SRC_MSIS)
|
||||
/* Set MSIS as SYSCLCK source */
|
||||
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_MSIS);
|
||||
while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_MSIS) {
|
||||
}
|
||||
#elif defined(STM32_SYSCLK_SRC_HSI)
|
||||
/* Set HSI as SYSCLCK source */
|
||||
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI16);
|
||||
while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI16) {
|
||||
}
|
||||
#else
|
||||
return -ENOTSUP;
|
||||
#endif
|
||||
|
||||
/* Set FLASH latency */
|
||||
/* If freq not increased, set flash latency after all clock setting */
|
||||
if (old_hclk_freq >= CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC) {
|
||||
LL_SetFlashLatency(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
|
||||
}
|
||||
|
||||
/* Update CMSIS variable */
|
||||
SystemCoreClock = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief RCC device, note that priority is intentionally set to 1 so
|
||||
* that the device init runs just after SOC init
|
||||
*/
|
||||
DEVICE_DT_DEFINE(DT_NODELABEL(rcc),
|
||||
stm32_clock_control_init,
|
||||
NULL,
|
||||
NULL, NULL,
|
||||
PRE_KERNEL_1,
|
||||
CONFIG_CLOCK_CONTROL_INIT_PRIORITY,
|
||||
&stm32_clock_control_api);
|
||||
Loading…
Add table
Add a link
Reference in a new issue