Recent HAL update moved GDMA sleep-retention definitions from
hal/gdma_periph.h into the esp_driver_dma component. Include gdma_priv.h
and use the new gdma_retention_desc_t / gdma_retention_infos names in
place of the removed gdma_chx_reg_ctx_link_t / gdma_chx_regs_retention.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Replace explicit == true/false comparisons with idiomatic boolean
expressions in pwm_siwx91x_set_cycles().
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
This patch adds PM runtime management for the PWM peripheral. It allows
to block CPU from entering the sleep state when PWM is active.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
This patch ensure that clock_control_get_rate function returns the
correct clock rate for the PWM peripheral. PWM is clocked from M4
processor clock.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
Use the MCXL WWDT clock gate and clock frequency helper when
handling MCUX_WWDT0_CLK.
MCXL uses kCLOCK_GateWWDT0 and CLOCK_GetWwdtClkFreq(), unlike some
other LPC-style platforms that use kCLOCK_Wwdt0 and CLOCK_GetWdtClkFreq().
Signed-off-by: Samuel Slesar <samuel.slesar@nxp.com>
Add PM support for HCI ESP32 driver. Update sleep retention
config for BLE power management.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Add the ability to run cameras in a logical
snapshot mode instead of always running
in video mode. In particular, the camera
starts when you ask for an image to be dequeued
and stops when it receives an image.
There are two ways to setup to run in this mode:
a) Tell it to do so in the overlay by giving the DCMI object
the property: snapshot-mode
b) At run time: I added a video control: VIDEO_CID_SNAPSHOT_MODE
Which can have the values
0 - normal - continuous video mode
1 - snapshot - snapshot mode enabled.
As mentioned in the snapshot modes, the HAL DMA is stopped after each
image and restarted when the user asks for another image. I added a
timeout default to 1 second, that handles the case where sometimes
the HAL is silently not successful in retrieving an image.
Signed-off-by: Kurt Eckhardt <kurte@rockisland.com>
When HAL_DCM_Stop return an error code, their failure does not
appear to be a real failure, but instead it is more like it
simply did not have to do anything. As such changed from reporting
it from LOG_WRN to LOG_DBG
Signed-off-by: Kurt Eckhardt <kurte@rockisland.com>
So it is only built when needed, and we avoid a compiler warning:
bmp581.c:59:19: error: unused function 'bmp581_pm_busy_check'
The issue was there since c68a25e4d5
but only became apparent in CI when its test was added in
f0802b645b
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
TX path: build a dma_block_config chain from net_pkt->frags and pass it
directly to dma_config(), eliminating net_pkt_read() into a static
buffer.
RX path: reserve one networking-stack net_buf per RX DMA descriptor via
net_pkt_get_reserve_rx_data(); on completion link the buf into a net_pkt
via net_pkt_frag_add() and pass it to net_recv_data() without memcpy.
Signed-off-by: Venkatesh Odela <venkatesh.odela@amd.com>
Two issues fixed for multi-fragment scatter-gather TX support:
- Completion callback was fired per descriptor; now fires only on the
EOF descriptor so the ethernet driver unrefs net_pkt once per packet.
- Ring reset (memset, index reset, CURDESC write) is skipped when the
DMA is not halted to avoid corrupting an active ring.
Signed-off-by: Venkatesh Odela <venkatesh.odela@amd.com>
Replace the fixed I2C_TRANSFER_TIMEOUT constant with a per-instance
k_timeout_t field stored in the driver config struct. The field is
k_timeout_t transfer_timeout, initialized at compile time using
I2C_DT_INST_TRANSFER_TIMEOUT() which resolves the timeout with the
following priority:
1. zephyr,transfer-timeout-ms DT property on the controller node
2. CONFIG_I2C_TRANSFER_TIMEOUT_MS (Kconfig default)
3. K_FOREVER when the resolved value is 0
All k_sem_take() and sys_timepoint_calc() call sites in v1 and v2
use cfg->transfer_timeout directly -- no helper function needed.
Boards that omit the zephyr,transfer-timeout-ms DT property see no
behavioural change; falls back to CONFIG_I2C_TRANSFER_TIMEOUT_MS.
Signed-off-by: BhuvanChandra DV <bhuvanchandra.dv@rapyuta-robotics.com>
channel_max holds the channel count, so accepting a channel equal
to it read one past the irq_sources array and let callers index
the callback arrays out of bounds.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
The async-prescaler default referenced _HSE_ASYNC_PRESCALER, a
truncated spelling of RTC_HSE_ASYNC_PRESCALER that is defined
nowhere, breaking the build for HSE-clocked RTC configurations
without the async-prescaler property.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
The channel_info pointer was formed before the channel == -1 check,
creating an out-of-bounds pointer for every unmapped channel. Move
the lookup after the guard.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
The I2C_SPEED_FAST_PLUS case fell through into the unsupported
I2C_SPEED_HIGH case and returned -EIO. Add the missing break.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
DT_INST_NODE_HAS_PROP was spelled with hyphens in the sda_hold_tx
initializer, so the i2c-sda-hold-time-ns property was silently
ignored.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
DT_INST_NODE_HAS_PROP() reports whether a property is defined, not
the value of a boolean property. Binding-defined boolean properties
remain defined with value zero when absent, so the existing guards
still compile the SIRC paths on MCXW72.
Use DT_INST_PROP() for every sirc-supported guard. This excludes the
SIRC SDK calls on MCXW72 while preserving them on MCXW70 and MCXW71.
Verified with the three MCXW72 OpenThread configurations that failed
in Twister and with cpp.main.minimal on MCXW71.
Assisted-by: Codex:gpt-5
Signed-off-by: Philipp Steiner <philipp.steiner1987@gmail.com>
For ADCs that use a common register for sampling times, improve the error
message when the common registers are already set and can't accept a new
value.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Implement counter capture callbacks for MCUX QTMR timer channels. Each
Zephyr counter device maps to one QTMR channel, so the API accepts
channel 0 and uses the DT secondary-source property as the capture
input.
Reject capture in modes that already consume the secondary source and
keep alarm and capture ownership exclusive on the channel. Add reset
support so generic counter capture tests can prepare the timer state.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
split the checksum Kconfigs into a user
changable Kconfig and a hidden one, that
will have the combined status, which we
then use in the driver. That way we don't
include the checksum offloading stuff,
when we don't need it.
Signed-off-by: Fin Maaß <info@finmaass.de>
as net_pkt_frag_ref, will not only unref
the current net buf but also all net bufs
after it, we are now keeping the reference of the
net_pkt.
This will also make it easier to add ptp support later,
because there we need the net_pkt at that point.
the ptp code btw also uses a k_fifo for it.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
rename REG_READ/WRITE to DWMAC_REG_READ/WRITE,
so we don't have conflicts, like we got on the esp32.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Add a spinlock-protected `enabled` flag to the driver data struct to
eliminate the race between wdt_nrf_gswdt_disable() and
wdt_nrf_gswdt_feed(). The spinlock is held across both the state check
and mbox_send_dt() in the feed path, and across the flag update in the
setup and disable paths, ensuring a consistent view of the enabled
state. Sending feed when wdt was not enabled would cause watchdog
to start counting down the timeout.
Signed-off-by: Łukasz Stępnicki <lukasz.stepnicki@nordicsemi.no>
Wi-Fi driver for ST67W611M1 coprocessor.
It communicates with an SPI interface and depends on Zephyr's own
TCP/IP stack.
Communication with host is a mix of AT commands (scan, connect,...)
and raw L2 layer data frames.
Signed-off-by: Eliott Speyser <eliott.speyser@st.com>
Make AF_PACKET SO_TIMESTAMPING reporting depend only on
net_pkt_is_rx_timestamping(). This removes the timestamp-value heuristic
and makes the RX timestamp marker the single source of truth for whether
packet timestamp control data is valid.
Update in-tree Ethernet drivers that store RX timestamps to set the marker
before handing packets to the stack, and document the migration requirement
for out-of-tree drivers. Keep test coverage for the unmarked-packet case so
unmarked timestamps are not reported to socket applications.
Signed-off-by: Philipp Steiner <philipp.steiner1987@gmail.com>
The STM32 HAL keeps the last RX timestamp in its RX descriptor list. If a
later packet has no RX timestamp context descriptor,
HAL_ETH_PTP_GetRxTimestamp() can return the previously cached value and
make Zephyr mark the packet as timestamped with stale data.
Poison the HAL RX timestamp cache before HAL_ETH_ReadData() and only accept
the timestamp if the HAL refreshes it with a non-sentinel value for the
packet currently being processed. This bases timestamp validity on
descriptor state instead of PHC age, which can falsely reject valid
timestamps when RX handling is delayed under heavy traffic.
PTP timestamping can consume an additional RX context descriptor on
STM32H5, so make the RX descriptor count configurable there and default it
to 8 when the STM32 PTP clock is enabled. Also select no-cache memory for
STM32 Ethernet whenever the architecture supports it.
Signed-off-by: Philipp Steiner <philipp.steiner1987@gmail.com>
We don't want to reinitialise the clock control when
we boot the second core - so this commit introduces a
means to skip initialisation (i.e. assume it is already
initialised). This hidden Kconfig symbol will be set
when running from CPU1 when AMP on the rp2350 is
implemented.
Co-authored-by: Dmitrii Sharshakov <d3dx12.xx@gmail.com>
Signed-off-by: Dan Collins <dan@collinsnz.com>
Signed-off-by: Dmitrii Sharshakov <d3dx12.xx@gmail.com>
Signed-off-by: Andrew Fantino <fantino@qti.qualcomm.com>
XIP in Zephyr is a software configuration concept (CONFIG_XIP). The MSPI
feature gated by MSPI_XIP only memory-maps the device into the SoC
address space; the mapped region can be used for plain data access as
well as code execution. Rename the feature to MEMMAP to reflect what it
actually does:
- CONFIG_MSPI_XIP -> CONFIG_MSPI_MEMMAP
- CONFIG_FLASH_MSPI_XIP_READ -> CONFIG_FLASH_MSPI_MEMMAP_READ
- struct mspi_xip_cfg -> struct mspi_memmap_cfg
- enum mspi_xip_permit / MSPI_XIP_READ_* -> mspi_memmap_permit /
MSPI_MEMMAP_READ_*
- mspi_xip_config() -> mspi_memmap_config(), driver API entry
xip_config -> memmap_config
- MSPI_XIP_CONFIG_DT{,_INST,_NO_CHECK} -> MSPI_MEMMAP_CONFIG_DT{,...}
- MSPI_XIP_CFG_STRUCT_DECLARE / MSPI_XIP_BASE_ADDR_{DECLARE,INIT} ->
MSPI_MEMMAP_*
- devicetree property xip-config -> memmap-config
Vendor HAL symbols (am_hal_mspi_xip_*) and DesignWare register names,
where XIP is the hardware documentation terminology, are unchanged.
The MSPI API is experimental, so no deprecated aliases are provided;
a migration guide entry is added in a separate commit. Add missing
Doxygen comments on new API symbols. Add missing SPDX header to the
nrf54h20dk code_relocation_nocopy overlay touched by this rename.
Fixes#104657
Signed-off-by: Richard Wheatley <richard.wheatley@ambiq.com>
Move most of the shared sources from drivers/video/ into subsys/video/.
The content left in drivers/video/ is now only used by drivers, or
drivers themselves.
Signed-off-by: Josuah Demangeon <me@josuah.net>
Move all the content of <zephyr/drivers/video.h> to a separate include
file in <zephyr/video/video.h> except driver entry points, all with a
video_drivers_... prefix.
Video control IDs are now in <zephyr/video/controls.h> and included
from both <zephyr/drivers/video.h> and <zephyr/video/video.h>.
Video format FourCCs are now in <zephyr/video/formats.h> and included
from both <zephyr/drivers/video.h> and <zephyr/video/video.h>.
As a side effect, introduce a video subsystem in MAINTAINERS.yml
Signed-off-by: Josuah Demangeon <me@josuah.net>
Pair RX_INT on async RX disable/error paths. irq_rx_enable takes the
lock during async RX, but async_rx_disable does not call
irq_rx_disable, so the lock was left held after transfers.
Also restore UHCI on PM resume when peripherals are powered down in
light sleep. UHCI has no sleep-retention link (unlike UART/GDMA) and
comes back reset with its UART port detached.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Do not release the TX_INT_STREAM policy lock on TXFIFO_EMPTY; that
interrupt only means the TX FIFO has space. Keep the lock until
irq_tx_disable. Also take an RX_INT lock across irq_rx_enable/disable
so light sleep cannot run while IRQ-driven RX is armed.
Rename tx_ongoing to pm_lock_bits now that the mask covers RX as well.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
I2C_STM32_DOMAIN_CLOCK_SUPPORT was always evaluating to 0 in this
driver since DT_DRV_COMPAT isn't defined yet at the point it's used.
This meant the domain clock (pclken[1]) was silently ignored even on
boards whose devicetree defines a second clock.
As suggested by @erwango in the issue discussion, instead of trying
to fix the compile-time macro, this commit removes it entirely.
cfg->pclk_len is already set from DT_INST_NUM_CLOCKS(),
so it tells us at runtime, per instance, whether a second clock exists.
A few other STM32 drivers (i2c, i3c) already do it this way
Fixes#112469
Signed-off-by: Akansh Sinha <akansh.sinha.dev@gmail.com>
counter_get_frequency() is allowed to be called from a counter alarm or
top-value callback, which runs in the counter ISR. The Infineon TCPWM
counter driver implemented get_freq() by querying the peripheral clock
tree on every call via the PDL (Cy_SysClk_PeriPclkGetFrequency ->
Cy_SysClk_ClkHfGetFrequency).
On non-secure builds (TrustZone-M with TF-M) that PDL clock query is
serviced by the secure world through a PSA / secure-request round-trip.
Such calls are not permitted from interrupt context, so invoking
counter_ticks_to_us() / counter_get_frequency() from an alarm callback
made the secure request fail and the PDL assertion fault the core,
hanging the application. In thread context the same query works, and
secure builds read the clock registers directly, so the failure was
specific to the non-secure interrupt path.
The counter input clock is fixed once the peripheral divider is assigned
at init. Cache the frequency during device init (thread context) and
return the cached value from get_freq(). This makes
counter_get_frequency() safe to call from the counter ISR and also
avoids a clock-tree walk on every call.
Run the driver init at POST_KERNEL rather than PRE_KERNEL_1: on the CM55
the same clock query is relayed to the secure world over IPC and blocks
on a semaphore, which is not available before the kernel is up.
POST_KERNEL populates the cache once the kernel and the relay are ready,
and still before any application arms an alarm, so the cached value is
always valid when get_freq() runs from an ISR. Also fail init with -EIO
if the frequency reads back as 0.
Assisted-by: AI (GitHub Copilot)
Signed-off-by: Bill Waters <bill.waters@infineon.com>
To reset channel preselection register (PCSEL), low-level function
LL_ADC_SetChannelPreselection has been used. This function does not clear
any bit as it uses bitwise OR and can only set the bit. Replace this with
stm32_reg_write() to clear whole register with 0.
Signed-off-by: Marin Jurjević <marinjurjevic@outlook.com>
Channel preselection condition uses bitwise operation on raw
register value to check if channel needs setup. Use BIT(channel_id)
macro to extract relevant bit instead of channel.
Signed-off-by: Marin Jurjević <marinjurjevic@outlook.com>
Instead of the vendor-specific `stm32_lp_tick_source` nodelabel, update
the STM32 LPTIM systimer driver to use the `zephyr,system-timer` chosen
as singleton instance selection.
Remove support for the old mechanism entirely, triggering instead
a build error during Kconfig parsing (to avoid unnecessary compilation).
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
On some STM32 series, the VREFBUF's voltage scale can only be changed
while the regulator is disabled. Update the driver to support such
series by consuming the new "st,has-active-scale-change" property and
performing the regulator disable/enable sequence when changing voltage
scale on series without the property.
On series where the VREFBUF supports changing voltage scale while
enabled, the driver behavior should remain unchanged.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
The DMA main soft-reset bit is self-clearing and clears the block
enable while it is in progress. The previous sequence wrote the
enable bit immediately after the reset request (separated only by a
dummy I/O-delay write), so the enable could be dropped if the reset
had not yet finished. Poll the self-clearing SRST bit until it reads
back zero before setting the enable bit.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Add a Kconfig option, DMA_MCHP_XEC_DMAC_MAX_CHANNELS, defaulting to the
dmac node's dma-channels devicetree property,
Updated PCR and GIRQ properties of DMA node to use new macros
Also removed the XEC_DMA_DEBUG logic.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
Replace the CMSIS-style packed-struct register overlays
with register offset constants accessed via the Zephyr
sys_read32/sys_write32/sys_set_bit/sys_clear_bit helpers.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
The TDP2004 is a four-channel linear repeater or redriver designed
to support DisplayPort 2.1 up to 20Gbps and AC coupled HDMI2.1 source
up to 12Gbps.
Signed-off-by: Julien Panis <jpanis@baylibre.com>
