off_t is a POSIX type used for sizes of files. Zephyr uses it for the
position of objects within flash storage.
It assumes that off_t is equivalent to 'long' when printing offset values
as well as being the same size as a pointer when converting offsets to
addresses for in-memory flash regions.
Neither of these assumptions hold when off_t is 64-bits on 32-bit targets.
When used as a pointer offset, cast values to ptrdiff_t. To print them
use the 't' length specifier.
When used as a memory address, cast values to uintptr_t, including before
casting to a pointer. To print them, cast to long and use a 'l' length
specifier.
Signed-off-by: Keith Packard <keithp@keithp.com>
Remove dependency on DL_MCAN_* driverlib APIs and the associated
USE_MSPM0_DL_MCAN Kconfig select. Replace with direct sys_write32/
sys_read32 calls using MCANSS register offsets verified from hw_mcan.h.
CANCLK source selection (SYSCTL GENCLKCFG) is now handled by the clock
control driver. The CAN driver calls clock_control_on() before
peripheral initialization and configures only MCANSS-internal registers
(CLKDIV, CLKEN, RSTCTL, PWREN, STAT, ICLR, IMASK, IIDX, EOI).
Signed-off-by: Aman Lachhiramka <a-lachhiramka@ti.com>
Select CANCLK source (HFCLK or SYSPLL) in SYSCTL GENCLKCFG during
clock driver initialization, based on the canclk clocks phandle in DT.
This moves the system-level clock mux configuration out of peripheral
drivers and into the clock controller where it belongs.
Signed-off-by: Aman Lachhiramka <a-lachhiramka@ti.com>
Hardware TX security on EFR32 failed for sleepy OpenThread devices.
sli_crypto_ccm_zigbee() produces a bad MIC when the encrypted payload
is empty (MAC Data Request). Build that CCM* tag from AES-ECB instead.
Include Header IEs in the CCM* AAD so IEs such as CSL stay in the
clear.
Ignore a leftover net_pkt timestamp unless the TX is scheduled, so CSL
phase is not frozen on the long-lived OpenThread packet.
Signed-off-by: sree sreerajatha <sree.sreerajatha@silabs.com>
Add the platform glue that brings up the Synopsys DesignWare MAC found
on the RK3588, along with the rockchip,rk3588-gmac binding.
Bus init asserts the CRU reset line, programs the RGMII interface select,
clock direction and TX/RX delays through the system and PHP GRF syscon
regions, then deasserts reset. Because the RGMII transmit clock is
divided down in the PHP GRF instead of being driven by the MAC, the
divider is reprogrammed from the platform link speed change hook.
DMA descriptors use the linker nocache region. The driver depends on
64BIT and derives the GMAC instance id from the register address rather
than the devicetree instance number.
Signed-off-by: Yanzhao Cui <cuiyanzhao@kylinos.cn>
Some platforms feed the MAC from a clock whose divider depends on the
negotiated link speed, so that clock has to be reprogrammed every time
the PHY reports a new speed. There is currently no way for the platform
glue to learn about a speed change.
Add a dwmac_platform_link_speed_changed() hook, called by the QoS core
from the PHY link state callback right after MAC_CONF has been updated.
The default implementation is empty and weak, so platforms that do not
need it are unaffected.
Signed-off-by: Yanzhao Cui <cuiyanzhao@kylinos.cn>
Add a reset controller driver for the RK3588 Clock and Reset Unit,
together with its devicetree binding. The CRU exposes the peripheral
soft reset lines through write-enable protected registers; the driver
implements the assert, deassert and toggle operations on top of them so
peripherals such as the GMAC controllers can be reset from devicetree.
The driver maps the parent CRU MMIO region and uses the soft reset
registers through offsets from that base.
Signed-off-by: Yanzhao Cui <cuiyanzhao@kylinos.cn>
Add a clock controller driver for the RK3588 Clock and Reset Unit,
together with its devicetree bindings. The driver gates and ungates the
peripheral clocks selected by the clock IDs from the rk3588-cru
dt-bindings header and reports nominal rates for the GMAC clocks so the
MAC can derive its CSR setting without a fixed snps,clk-csr property.
The driver maps the parent CRU MMIO region and uses the clock gate
registers through offsets from that base.
Signed-off-by: Yanzhao Cui <cuiyanzhao@kylinos.cn>
i2c_sc18im_init() writes the BRG0/BRG1 registers to update the bridge
default 9600 power-on baud rate, and then reconfigures the MCU's own
UART to the desired `target-speed` after a fixed `k_msleep(1)`.
That 1ms delay is too short.
uart_poll_out() blocks on TXE (the byte has reached the shift register)
and returns before the byte has actually finished on the wire.
The write command's trailing 'P' can therefore still be transmitting
when i2c_sc18im_init() calls uart_configure().
One byte at 9600 8N1 takes 10/9600 = 1.0417 ms, longer than the 1 ms,
and sc18im takes several micro-seconds to update it's baudrate and get
ready to listen again (this amount of time is undocumented, but few
tests showed that a minimum delay of 1900 micro-seconds is mendatory
(1041 for tx and the rest for the sc18im to reconfigure)).
This commit now makes the mcu wait 2ms to be sure the sc18im has fully
received and reconfigured it's UART receiver to the desired baudrate.
Signed-off-by: Alex Fabre <alex.fabre@rtone.fr>
The Zephyr I2C API passes a 7-bit address to a controller's transfer()
callback, and every controller shifts it left (by one) to build the
address byte that goes on the bus.
The SC18IM704 bridge datasheet frames a transfer as:
'S' <SlaveAddress + R/W> <NrBytes> [Data...] 'P'
where the address byte carries the 7-bit address in bits 7:1 and the
direction in bit 0.
Signed-off-by: Alex Fabre <alex.fabre@rtone.fr>
While processing ISR messages in the worker thread, acquire and hold the
UDC device lock to prevent races with the UDC API entrypoints which also
mutate the device state, leading to corruption.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Reject message queues whose message size differs from
sizeof(struct can_frame), before the callback is installed. The check
sits in the implementation rather than in the system call handler so
that supervisor callers, which bypass the handler, are covered as well.
Assert the same invariant in the callback to catch a message queue
re-initialized after the filter was installed.
Signed-off-by: Flavio Ceolin <flavio@hubble.com>
Following 42bbe8044a, display_capabilities
struct is memset to 0 at API level, so remove all memsets of it from
drivers.
Signed-off-by: Abderrahmane JARMOUNI <git@jarmouni.me>
i3c_stm32_clear_err() already releases bus_mutex. The DAA error
path subsequently jumps to the common exit path, which releases
bus_mutex a second time.
Return directly from the DAA error path after restoring the TXFNF
interrupt, avoiding an invalid second k_mutex_unlock().
Signed-off-by: Duc Viet Le <levietduc0712@gmail.com>
The LED and GPIO PCA953x drivers both register a log module named
pca953x, so a build enabling both fails to link with a multiple
definition of log_const_pca953x. Rename the LED module to led_pca953x,
matching the led_ prefix other LED drivers use for chips that a GPIO
driver also serves.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:opus-5
The driver rejects peripheral mode with SPI_OP_MODE_SLAVE, which is
marked __DEPRECATED_MACRO and so makes the build fail under -Werror.
Use SPI_OP_MODE_PERIPHERAL instead and reword the log message to match
the controller/peripheral terminology the other SPI drivers use.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:opus-5
CTRL[DOZEN] decides whether the converter keeps running once the system
enters a low-power mode. The driver never touched it, so the setting came
from the MCUX SDK default, which is not the register reset value and was
not visible in device tree.
Expose it as stop-in-low-power-mode. Absent -- the default -- matches the
CTRL reset value: DOZEN is 0, so the converter keeps running in the
low-power modes where it stays functional, and hardware trigger detection,
an active conversion and the compare-based wakeup all survive. That does
require the functional clock ADCK to keep running, which the clock
configuration must arrange. Setting the property stops the converter for
the duration of any low-power mode instead.
Note the SDK field is inverted with respect to the register field:
enableInDozeMode clears DOZEN.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
PM_DEVICE_ACTION_SUSPEND runs LPADC_Enable(false), so a sequence started
against a suspended device never raises the watermark interrupt and never
completes. The read path did not look at the PM state, so it armed the
sequence anyway and only the acquisition timeout eventually cleaned it up
-- one full timeout per read, and before that timeout existed the caller
blocked forever.
Check the PM state before taking the ADC context lock and return -EBUSY if
the device is not ACTIVE. Verified on frdm_mcxn236 with both plain
CONFIG_PM_DEVICE and CONFIG_PM_DEVICE_RUNTIME: a read against the
suspended converter now returns -EBUSY immediately and the device is
unaffected, so the following resume and read still succeed.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
adc_context.h defaults ADC_CONTEXT_WAIT_FOR_COMPLETION_TIMEOUT to
K_FOREVER, so any conversion sequence that can never complete blocks the
calling thread permanently. That is reachable: the completion semaphore is
given from the watermark interrupt, and a converter disabled behind the
driver's back never raises it. adc_read() then never returns and takes the
caller down with it, with no error to report.
Bound the wait with a new CONFIG_ADC_MCUX_LPADC_ACQUISITION_TIMEOUT_MS
(default 1000). On expiry return -EAGAIN and abort the sequence: stop DMA
if it is in use, then cycle the converter disabled/enabled to clear the
command state machine and reset the FIFOs, so a result that arrives too
late cannot be stored into a buffer the caller has already reclaimed.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
LPADC_PM_DEVICE_DEFINE and LPADC_PM_DEVICE_GET are object-like macros, so
the n in their replacement lists is a literal n rather than the parameter
of the LPADC_MCUX_INIT(n) they expand inside -- macro parameter
substitution happens before nested macro expansion. Every instance
therefore emitted the same symbol, and the build failed with a
redefinition error for
__pm_device_dts_ord_DT_N_INST_n_nxp_lpc_lpadc_ORD.
A single enabled instance goes unnoticed because LPADC_PM_DEVICE_GET has
the same bug and so refers to the same misnamed object, but two enabled
instances break the build outright. boards/nxp/frdm_mcxaxx6 enables both
lpadc0 and lpadc1, so frdm_mcxa266, frdm_mcxa346 and frdm_mcxa366 cannot
be built with CONFIG_PM_DEVICE=y at all.
Parameterize both macros. frdm_mcxa266 now builds both instances and
emits two distinct __pm_device_dts_ord_* objects.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Do not schedule transfers while a bus reset or resume operation is in
progress. Starting a transfer during these operations can produce a
J-state error with some full-speed devices.
Keep scheduling disabled until the controller reports that the active
bus operation has completed.
Signed-off-by: Benjamin Jurewicz <bjurewicz@internships.antmicro.com>
The new dma_stm32_zcfg_to_halcfg() relies heavily on default STM32
configuration. Document it in order not to loose the DMA consumer
drivers into wrong configuration.
Signed-off-by: Raphaël Gallais-Pou <raphael.gallais-pou@foss.st.com>
Use the private STM32 DMA helper in HAL-managed DMA setup paths instead
of open-coding common DMA_InitTypeDef fields in each consumer.
Keep peripheral-specific settings such as request lines, instances,
channel attributes, bursts, and port allocation local to each driver.
This reduces duplicated HAL DMA setup in flash, MSPI, SAI, SDMMC, and
DCMI STM32 drivers.
Assisted-by: Copilot:gpt-5.5
Signed-off-by: Raphaël Gallais-Pou <raphael.gallais-pou@foss.st.com>
Add STM32U5 conversion from Zephyr dma_config into STM32 HAL DMA init
fields.
Translate direction, priority, burst length, address increment, data
width, and cyclic mode settings while preserving U5-specific linked-list
behavior.
This lets HAL-managed users use the common STM32 DMA helper on STM32U5
without open-coding the common init fields.
Assisted-by: Copilot:gpt-5.5
Signed-off-by: Raphaël Gallais-Pou <raphael.gallais-pou@foss.st.com>
Add BDMA-side conversion from Zephyr dma_config into STM32 HAL DMA init
fields for configurations that do not build the classic STM32 DMA v1/v2
helper.
Map direction, priority, address increment, data width, and mode values
so HAL-managed users can share the same DMA setup path on BDMA-only SoCs.
Assisted-by: Copilot:gpt-5.5
Signed-off-by: Raphaël Gallais-Pou <raphael.gallais-pou@foss.st.com>
Add a private STM32 DMA helper that converts Zephyr dma_config settings
into common STM32 HAL DMA_InitTypeDef fields.
int dma_stm32_zcfg_to_halcfg(const struct dma_config *zephyr_config,
DMA_InitTypeDef *hal_config);
Keep the helper as one exported implementation in the existing STM32 DMA
source and keep HAL-family differences local to the conversion flow.
Also build the helper for STM32U5 or BDMA-only configurations where the
classic DMA driver body is not enabled.
Assisted-by: Copilot:gpt-5.5
Signed-off-by: Raphaël Gallais-Pou <raphael.gallais-pou@foss.st.com>
Implement the PWM capture API for the NXP eMIOS driver using the
Single Action Input Capture (SAIC) mode.
Three capture API functions are implemented:
- configure_capture: switches the channel to SAIC mode using
both-edge triggering (EDSEL=1). Bit 31 of the A register
(RISING_FALLING_EDGE_MASK) identifies which edge fired, so a
single interrupt path handles all capture type combinations.
This mode uses internal counter with range [0, 0xFFFF] to
maximize the measurement window.
- enable_capture / disable_capture: gate the channel and counter
bus prescalers and the channel FEN interrupt bit.
The ISR (pwm_nxp_emios_isr) reads GFLAG to service all pending
channels efficiently. Per-channel state machine (3 states):
- state 0: wait for first active edge
- state 1: wait for opposite edge (pulse) or next active edge
(period-only)
- state 2: wait for second active edge to close period+pulse
Wrap-around is handled by pwm_nxp_emios_elapsed() by masking
32-bit unsigned subtraction to 16 bits without a conditional
branch.
Signed-off-by: William Tang <william.tang@nxp.com>
Add a new PWM driver for the NXP Enhanced Modular I/O Subsystem
(eMIOS) peripheral, targeting MCX E-series devices.
The driver supports the following PWM output modes:
- OPWFMB: output PWM with Frequency-Modulated Buffered mode,
using the channel's internal counter.
- OPWMB: output PWM with Modulus counter Buffered mode, using
a shared counter bus (A/B/C/D/F) as the period reference.
- OPWMCB (trailing/leading edge): center-aligned PWM with dead
time insertion, using a shared counter bus (A/B/C/D/F) as the
period reference.
The standard pwm_driver_api is implemented:
- set_cycles: dispatches to the per-mode handler based on the
DT-configured mode for each channel.
- get_cycles_per_sec: returns emios_clk / (global_prescaler *
channel_prescaler).
PWM_POLARITY_NORMAL and PWM_POLARITY_INVERTED are both supported.
Phase-shift (OPWMB leading edge offset) is taken from DT.
Signed-off-by: William Tang <william.tang@nxp.com>
Add MC_CGM clock gate entries and frequency query support for the
NXP eMIOS peripheral:
- Add LISTIFY-based gate entries for all eMIOS instances, guarded
by CONFIG_PWM_NXP_EMIOS and FSL_FEATURE_SOC_EMIOS_COUNT, so
clock gating follows the same pattern used by ADC and FlexCAN.
- Add a MCUX_EMIOS0/1/2_CLK case in mc_cgm_get_subsys_rate() that
returns CLOCK_GetCoreClkFreq(). The eMIOS SDK provides per-
instance gate IDs (kCLOCK_Emios0/1/2) but only a single shared
clock query enum (kCLOCK_EmiosClk), so frequency lookup cannot
use LISTIFY and is handled via switch-case instead. This is
documented in the comment block above mc_cgm_rate_map[].
Required by the eMIOS PWM driver to obtain the input clock
frequency at init time.
Also update emios clocks phandle array in mcxe31x common DTSI.
Signed-off-by: William Tang <william.tang@nxp.com>
Add support for NXP JPEG decoder hardware module. This driver provides
memory-to-memory (M2M) video transformation capability to decode JPEG
compressed images into raw pixel formats.
Key features:
- Supports JPEG input format (VIDEO_PIX_FMT_JPEG)
- Resolution support: 64x64 to 8192x8192 pixels (16-pixel step)
- Automatic format detection from JPEG header parsing
- No color space conversion (output format matches JPEG encoding)
- Interrupt-driven operation with input/output buffer queues
- Configurable output buffer pitch for flexible memory layouts
Signed-off-by: Kate Wang <yumeng.wang@nxp.com>
MEMC_MCUX_XSPI was gated on DT_HAS_NXP_XSPI_PSRAM_ENABLED, but
FLASH_MCUX_XSPI selects it based only on DT_HAS_NXP_XSPI_NOR_ENABLED,
causing a Kconfig error on boards with XSPI NOR flash but no XSPI
PSRAM device. Move it to its own DT_HAS_NXP_XSPI_ENABLED block,
matching the existing MEMC_MCUX_FLEXSPI pattern.
Signed-off-by: Ruijia Wang <ruijia.wang@nxp.com>
The STM32C5 integrates the same DesignWare Ethernet MAC QoS IP core as
the H5 and H7 series, in version 5.40 with a 32-bit AHB master and MII
and RMII support, so the glue only has to select the PHY interface for
it.
The HAL based driver stays the default, unless PTP is enabled.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
The MDIO driver derives the MDC divider from the MAC CSR clock, which
the glue took as the first entry of the devicetree clocks array. That
holds for every STM32 series supported so far, but ties the driver to
the order of a property whose entries are named.
Look the gate up by its "stm-eth" name instead, the way the PTP clock
index already does. Every in-tree ethernet node names it, so a series
that does not gets a build error rather than a silently wrong rate.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
Add the PM_STATE_SUSPEND_TO_RAM case to pm_state_set, entering via
arch_pm_s2ram_suspend with rp2350_s2ram_off as the callback: power down
the domains via POWMAN (keeping XIP cache and SRAM bank0/1 on) and
execute WFI. On resume, pm_state_exit_post_ops clears the debug-power
override set right before the power-down (it must be cleared on the
resume path, since a real wake resumes into arch_pm_s2ram_suspend()'s
caller rather than returning from rp2350_s2ram_off(), so clearing it
there would never run) and reconfigures the clocks.
SysTick is powered down along with the rest of the switched core, so
hook the RP2350 up to the generic system-timer low-power companion
interface (CONFIG_SYSTEM_TIMER_LPM_COMPANION_HOOKS) instead of
reimplementing timer restart locally: z_sys_clock_lpm_enter() arms a
POWMAN alarm for the requested timeout and z_sys_clock_lpm_exit()
reports the elapsed time from the POWMAN timer, both added to
rp2350_powman.c. Selecting CONFIG_SYSTEM_TIMER_RESET_BY_LPM makes the
cortex_m_systick driver reprogram SysTick from scratch on exit, so no
SoC-specific restart hook is needed.
Clock restoration is delegated to clock_control_rpi_pico_reconfigure(),
factored out of the rpi_pico clock_control driver's init function rather
than reimplementing a fixed XOSC/PLL_SYS/clk_ref/sys/peri sequence in
power.c: this restores every devicetree-declared clock at the board's
actual configured rates, not just a hardcoded subset, and keeps a single
source of truth between cold boot and S2RAM resume.
Signed-off-by: Gabriel Germano <gabriel.lucasgermano@gmail.com>
Add DMAC support to SCI B I2C driver for RA MCU:
- Add CONFIG_I2C_RENESAS_RA_SCI_B_DMAC configuration option
- Add rx-dtc, tx-dtc device tree properties
- Support both DTC/DMAC transfer with shared transfer infrastructure
- Add tx-dtc and rx-dtc properties to device tree binding
- Add DMAC configurations, interrupt and callback declarations
Signed-off-by: Khai Cao <khai.cao.xk@renesas.com>
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
- Add CONFIG_SPI_RENESAS_RA_SCI_B_DMAC configuration option
- Add device tree properties for DTC (rx-dtc, tx-dtc)
- Support both DTC/DMAC transfer with shared transfer infrastructure
- Add tx-dtc and rx-dtc properties to device tree binding
- Add DMAC configurations, interrupt and callback declarations
Signed-off-by: Khai Cao <khai.cao.xk@renesas.com>
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
- Add CONFIG_SPI_B_DMAC configuration option
- Support both DTC/DMAC transfer with shared transfer infrastructure
- Add DMAC configurations, interrupt and callback declarations
Signed-off-by: Khai Cao <khai.cao.xk@renesas.com>
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
Add DMA Controller (DMAC) support for asynchronous UART TX/RX on
Renesas RA SCI-B.
Key changes:
- Add UART_RA8_SCI_B_UART_DMAC and UART_RA8_SCI_B_UART_DTC Kconfig
option to gate DTC/DMA support
- Add tx-dtc and rx-dtc DT binding properties for DTC transfer
- Support both DTC/DMAC transfer with shared transfer infrastructure
- Add DMAC transfer configuration, interrupt and callback declarations
Signed-off-by: Khai Cao <khai.cao.xk@renesas.com>
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
Update comments, log messages, Kconfig prose, and driver-local
identifiers to use the controller/target terminology ratified by
coding guideline A.2 and already used by the Zephyr I2C API.
Identifiers mirroring the Broadcom datasheet
(e.g. S_CMD_STATUS_MASTER_ABORT, MASTER_WR_STATUS) are kept unchanged.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:fable-5
The eSPI virtual UART channel cannot receive host traffic once the fast
clock (FMCLK) to the eSPI_SIF module stops, so the chip drops incoming
data as soon as it enters Sleep or Deep Sleep. Setting the
ESPI_FMCLK_ENSLP field of ENSLP_CTL keeps that clock running in those
states.
Add the fast-clk-to-espi-sleep-support property to describe the series
that implement the field, set it on npcx4, and gate the register write
on the new CLOCK_CONTROL_NPCX_ESPI_FMCLK_IN_SLEEP option, which is only
selectable when the property is present and both ESPI_PERIPHERAL_UART
and PM are enabled.
Assisted-by: Copilot:claude-opus-5
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Log when the Tx FIFO cannot accept a byte, and when the controller
is registered as a master.
Signed-off-by: Syed Muhammad Murtaza <syedx.muhammad.murtaza@altera.com>
Do not store a new speed configuration until the requested rate is
validated, so a failed configure leaves the previous settings in place.
Signed-off-by: Syed Muhammad Murtaza <syedx.muhammad.murtaza@altera.com>
Return an error from the non-blocking read helper instead of a
truncated byte, and only pass valid FIFO data to the target callback.
Signed-off-by: Syed Muhammad Murtaza <syedx.muhammad.murtaza@altera.com>
Allow the MCUX KPP driver to work with clock providers that do not
expose a named clock cell, such as fixed-clock.
Existing users with a named clock cell keep the previous behavior.
Fixed-clock providers use a zero clock subsystem.
Signed-off-by: Samuel Slesar <samuel.slesar@nxp.com>
Implement the reg_domain management op so the country code can be
read and set through the Wi-Fi management API and the wifi
reg_domain shell command.
Zephyr names the worldwide domain "00" while the Espressif
regulatory table uses "01", so the code is translated in both
directions. The third octet of the country string selects the
operating environment and is set to ' ' to accept a plain alpha-2
code. A forced domain is mapped to disabling 802.11d so the
configured country is not overridden by the surrounding APs.
On get, the 2.4 GHz channels are reported first and the 5 GHz ones
after them, as the other dual-band drivers do. The 5 GHz set comes
from the country channel mask, where an all-zero mask means every
channel the regulatory rules allow. Channel 14 is flagged passive
only and the 5 GHz channels 52 to 144 are flagged as DFS. The list
is clamped to MAX_REG_CHAN_NUM because callers report the filled
count back in num_channels rather than passing the buffer capacity
in it, and a NULL chan_info returns the channel count alone.
Assisted-by: Claude:opus-5
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Even if the driver does not support the frame timeout configuration,
if the HW peripheral does, we need to set it to disabled.
Otherwise the value is just random garbage which corrupts the
whole uart configuration as it will be OR'ed with the rest.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
The STM32N6 integrates the DesignWare Ethernet MAC QoS IP core in
version 5.20, with MII, RMII and RGMII support and a 64-bit AXI4 master
instead of the 32-bit AHB master of the other series.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
The bus mode register was left at its reset value, so the AHB master
issued undefined length bursts and did not align them. Utilize fixed
length bursts with address aligned beats instead.
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
