The original code process causes the following two issues:
1. The first sample is always 0 because the `ctx` sequence in `data` is
assigned the input sequence until the `adc_context_start_read`. As a
result, the `while (channels) { ... }` loop is not executed, and
`adc_enable_measurement` is not called.
2. Since the `ctx` sequence in `data` is assigned in
`adc_context_start_read`, which occurs after the `while (channels) {
... }` loop, the ADC samples the previously set channel.
Signed-off-by: Yunshao Chiang <Yunshao.Chiang@ite.com.tw>
As clarified by the subsystem maintainers, wait should be treated as a
boolean, not a duration.
Signed-off-by: Dmitrii Sharshakov <d3dx12.xx@gmail.com>
The kso_ignore_mask DTS property was not being fully applied in the
ITE IT8xxx2 keyboard driver:
1. The driver performed direct writes to the KBS_KSOH2 register,
which controls KSO[17:16]. This did not account for the
kso_ignore_mask and could overwrite bits in the register that
are used for other GPIO functions.
2. The driver would attempt to initialize the GPIOs for KSO16 and
KSO17 based solely on the col-size property. It ignored the
kso_ignore_mask, which could lead to reconfiguring a pin that
is intended for another purpose.
Signed-off-by: Wai-Hong Tam <waihong@google.com>
When setting CONFIG_MCUX_ELCDIF_FB_NUM=0 we can't assign the active pointer
to any framebuffer.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Some of the logging was not very useful and missing info, some were the
wrong level. Such as routine drops of packets, this happens sometimes
and is not ideal but not going to cause things to fall apart, so demote
those messages. RX buffer underrun for example is pretty unavoidable
with enough traffic going on the local network.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Extract the RX underrun handle code to a separate function.
Named the function like "dma_rx_resume" to make it clear what the
function is really supposed to do.
Demote the error about not being a first descriptor to a warning.
Because most likely we already got an error about something else which
caused us to drop the packet in the first place. The rest of the frames
are expected to be dropped. And make the string shorter.
Also remove the debug message because the control bits do not tell us
any more information than we don't know already. They only tell us that
we own the descriptor (known since we are processing the frame), that it
is not a first descriptor (known since that is the reason we would drop
it at this point, as indicated by the warning).
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Instead of looping through only the amount of descriptors there are,
maybe it is possible to get some more things received in one work item
than even the max number of descriptors if RX is processed fast enough,
instead of waiting for work to be scheduled again.
So change to go around the ring until we actually hit a DMA owned
descriptor.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Don't enable interrupt until after init because there can be a interrupt
mistakenly happen during the init process which can cause various
problems.
Along similar lines, avoid issue for sporadic TX interrupt with no
packet in tx done handler.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
There was a deadlock occurring, exposed by http server sample because of
situations like this caused by tx done work being blocked in deadlock:
1) The TX would be started by some thread and the driver TX sem would be
taken.
2) The http server socket would get scheduled on the system workqueue to
send something, claim the network TX interface mutex,
and be blocked taking the semaphore.
3) The RX traffic class handler would get blocked trying to claim the
network interface TX mutex, while trying to send an ACK in the TCP
callback. This means the RX packets would not be processed.
4) Lots of RX unable to allocate packets errors would happen, and all RX
would be dropped. This was the main symptom of the deadlock, which
made it look like a memory leak but actually had nothing to do with
the RX code nor any memory leak.
5) The TX DMA would finish and schedule the TX DMA done work onto the
system work queue, behind the http server socket which is blocked on
the waiting for the driver TX semaphore.
6) If the TX DMA done work would have ran, that's what gives the TX
driver semaphore. So this is the reason for the deadlock of all these
different threads and work items, the misqueue in the system
workqueue.
Fix by just calling the TX DMA done code directly from the ISR, it
should be ISR safe, and really not a lot of code to execute, just
freeing some net buffers and the packet and updating the stats.
An optimization can be made later if needed, but for now,
solving the deadlock is a more urgent priority.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
- Adds CONFIG_FLASH_PAGE_LAYOUT check to the flash_mcux_flexspi
drivers.
- Saves some memory if FLASH_PAGE_LAYOUT is disabled.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
The IO_CONTROL_1 register is 3 bytes long according to the datasheet.
This fixes the register not being written to correctly.
Signed-off-by: Luna Pes <zephyr@orangemurker.com>
Shell functions targeting regulator parents used the auto-completion of
regulator devices instead.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Allowed use of counter bit width lower than hardware 24.
In that case, PPI connection is established to trigger
clear task once maximum value is reached.
Signed-off-by: Michał Stasiak <michal.stasiak@nordicsemi.no>
This provides default ethosu_flush_dcache and ethosu_invalidate_dcache
overrides. User application can disable it through Kconfig option if it
needs to provide its own.
Signed-off-by: Chun-Chieh Li <ccli8@nuvoton.com>
The CPOL and CPHA mode handling logic in the SPI configuration was
corrected to ensure proper evaluation of the SPI mode bits.
Evaluate CPOL and CPHA bits using value of cpol_mode and cpha_mode:
`(SPI_MODE_GET(config->operation) & SPI_MODE_CPOL) != 0` and
`(SPI_MODE_GET(config->operation) & SPI_MODE_CPHA) != 0`.
This fix ensures that the SPI configuration is robust and adheres to
expected behavior when setting CPOL and CPHA modes.
Signed-off-by: Xiaolu Sun <xiaolu.sun@intel.com>
Implements HCI close support for the silabs efr32 HCI driver.
Calling `bt_disable()` now works as expected, which is particularly
important for multiprotocol applications.
Signed-off-by: James Smith <james@loopj.com>
- Setting IODEV_SQE to NULL to subsequent triggers are rejected.
- Channel all error-resolutions through handle_result_on_error().
Signed-off-by: Luis Ubieda <luisf@croxel.com>
Update the bit offset of bit VCC_STS in the BKUP_STS register.
Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Currently, the STM32 TIM counter driver will always register itself as ISR
for interrupts[0] of the timer node. This works fine for timers which have
a single "global" interrupt but not for others (e.g., Advanced Timer) which
have separate IRQ lines for various events.
Borrow the pattern from PWM driver: use the "cc" interrupt if it exists on
timer node, otherwise use the "global" interrupt. If neither of those are
found, a build error is raised to ensure silent failures cannot occur.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Restore setting the ppp link-local address either to CONFIG_PPP_MAC_ADDR or
to a random value 00:00:5e:00:53:XX instead of leaving it uninitialized.
Recently the memory handling for the link-layer addresses was changed from
an approach of copying pointers to managing the memory as a member of the
`net_linkaddr` struct (ref ac3cb9dac0).
The piece of code this patch touches however, relied on the use of the
pointers to function properly.
With the recent change, the MAC address was copied to the new member
location before it was even set (either from Kconfig or selected randomly).
As a result, the link-layer address was kept initialized to zero, which
resulted in a IPv6 address of fe80::ff:fe00:0 which is exactly the
link-local EUI-64 representation of the MAC address 00:00:00:00:00:00
(without flipping the "universal/local" bit).
Signed-off-by: Marc Lasch <marc.lasch@husqvarnagroup.com>
- Shift ifx_cat1 clock_control driver to using pdl instead of hal calls
- add soc.c file containing call to SystemInit()
- Update board's dts files
- add binding for peri divs
- update system_clocks.dtsi for psc3
- add new peri clock_control driver
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
Rework the driver so that it can cover multiple variants. Add variant DT
bindings. Change the compatible name for the mimxrt685s/cm33 DT.
This needed to be done because the hardware initialisation routines
(power, clocks, ...) are different from mimxrt685s/hifi4 to
mimxrt798s/hifi4. The same is expected for the /hifi1 domain.
Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>
To follow with error-handling of multi-shot items, they won't be marked
as cancelled. Instead, we expect them to stop being submitted, hence we
dispose the handle upon finishing every shot.
Signed-off-by: Luis Ubieda <luisf@croxel.com>
To follow with error-handling of multi-shot items, they won't be marked
as cancelled. Instead, we expect them to stop being submitted, hence we
dispose the handle upon finishing every shot.
Signed-off-by: Luis Ubieda <luisf@croxel.com>
Run-time errors can still be considered asserts if checkif is
configured as such, otherwise, prevent crashing.
Signed-off-by: Luis Ubieda <luisf@croxel.com>
Considering the app may have cancelled all the requests as an error
handling strategy, this driver needs to support recovering from such
case.
Signed-off-by: Luis Ubieda <luisf@croxel.com>
Whenever the data-ready callback is invoked, there's a common pattern
that needs to take place:
- Stop measurement timer (to stop on-coming samples), which could be
restored by the application re-submitting the request.
- Set iodev_sqe to NULL, so new requests can come in.
- Report the error on the SQE.
This has been refactored in handle_error_on_result() and now it's
invoked throughout the code.
Signed-off-by: Luis Ubieda <luisf@croxel.com>
The existing build-time asserts not only needs to cover dual-frequency
mode does no exceed high-speed settings, it needs to allow not using
dual-frequency mode settings at all, which is what this patch does.
Signed-off-by: Luis Ubieda <luisf@croxel.com>
With few APs we have seen unexplained disconnections and sending
keepalive often solves the problem, so, to fix interoperability reduce
the keepalive period to 30s.
Signed-off-by: Chaitanya Tata <Chaitanya.Tata@nordicsemi.no>
This change enables GMAC_MULTIPLE_TX_PACKETS to allow multiple TX packets
to be pushed to the DMA engine, improving transmit performance. Previously,
older Zephyr versions (pre-v2.6.0) lacked thread-safe handling in net_pkt
and net_buf, making multiple TX enqueuing unreliable. Issue #32564
("net_buf reference count not protected") was fixed in v2.6.0, providing
proper thread safety. The changes have been tested on SAME54 Curiosity
Ultra with EVB-LAN8670-RMII and KSZ8061 PHY daughter card, and the
expected performance of 9.5Mbps at 10Mbps PHY link speed was observed.
Signed-off-by: Parthiban Veerasooran <parthiban.veerasooran@microchip.com>
Fix clock config logic of wm8962 and wm8904 drivers, so that both can be
properly configured for master (generating BCK and WS) and slave
(receiving those) operation.
Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>
Zephyr is swapping the definitions of RGB565 and BGR565. Swap the return
values provided by this driver for supported pixel formats to account
for this.
Signed-off-by: Daniel DeGrasse <ddegrasse@tenstorrent.com>
This reverts the workaround made in the commit:
772fbfe9cc
as the proper fix has now been merged upstream.
Signed-off-by: Phi Bang Nguyen <phibang.nguyen@nxp.com>
Some systems (IE cores with bootloaders) may not disable the DW SPI
peripheral at boot time. Make sure the peripheral is disabled before we
try to configure it.
Signed-off-by: Daniel DeGrasse <ddegrasse@tenstorrent.com>
The designware controller has an *interesting* implementation of the CS
signal- CS will be de-asserted whenever the TX FIFO is empty, so slower
cores may see CS de-assert prematurely if they cannot keep pace with
their SPI peripheral. To help reduce odds of de-assertion, implement the
following changes:
- don't write SER bit until directly before we enable interrupts, so
that transfers don't start early
- prefix the TX FIFO before writing SER, so the FIFO can drain a bit
before have to service an interrupt
Signed-off-by: Daniel DeGrasse <ddegrasse@tenstorrent.com>
The SSI DW peripheral supports an RX_SAMPLE_DLY register in some
instances- this register controls the number of clock cycles from the
default sample time before the RX input is actually sampled. This can be
used to improve reliability when operating the SSI at a higher clock
speed.
Add an implementation of the mspi_timing_cfg api, and header to define
the identifier so that users can configure this parameter
Signed-off-by: Daniel DeGrasse <ddegrasse@tenstorrent.com>
Bitmask offsets for the MSPI_DW peripheral are incorrect for the
4.03a databook for the DW APB SSI. Add a "v2" compatible to handle these
changed offsets. The compatible does not define new binding properties,
just modifies the register offsets.
Additionally, handle writing the DFS32 mask for v2 of this compatible,
as newer IP supports a dataframe size up to 32 bits.
Signed-off-by: Daniel DeGrasse <ddegrasse@tenstorrent.com>
Multilevel interrupts require that the irq number be read with DT_IRQN,
so update the driver to use this macro.
Signed-off-by: Daniel DeGrasse <ddegrasse@tenstorrent.com>
