Commit graph

25,525 commits

Author SHA1 Message Date
Pete Johanson
1ec463e1a8 drivers: hwinfo: Memoize the USN fetched on MAX32
To avoid issues with multiple calls to fetch the USN returning garbage
data, memoize the returned USN value and re-use it on subsequent calls.

Signed-off-by: Pete Johanson <pete.johanson@analog.com>
2025-10-09 09:37:21 +02:00
Mario Paja
e892deba9e drivers: i2s: stm32 sai add support for stm32l5xx series
STM32L5xx series shares several DMA configurations with
the other platforms. These changes aim to enable platform
specific DMA configuration and align them to other platforms.

Signed-off-by: Mario Paja <mariopaja@hotmail.com>
2025-10-09 09:36:37 +02:00
Quang Le
f85ceddea6 drivers: clock control: Add Clock Control support for RZ/A3UL, V2L
Add Clock Control driver support for Renesas RZ/A3UL, V2L

Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
2025-10-09 09:36:24 +02:00
Shan Pen
ffb91a2b45 drivers: sdmmc_stm32: Fix bus width initialization sequence
Fix SDMMC initialization by starting with 1-bit bus mode and
properly configuring wide bus operation after HAL
initialization.

The SDMMC protocol requires initialization to start in
1-bit mode before switching to wider bus widths.
Previously, the driver attempted to initialize directly
with the target bus width, which could cause later read/write
failures.

Changes:
- Initialize with SDMMC_BUS_WIDE_1B instead of target bus width
- Add HAL_SD_ConfigWideBusOperation() call if needed after
successful init
- Add error logging for wide bus configuration failures

Fixes potential SDMMC read/write failures issues on STM32 platforms.

Signed-off-by: Shan Pen <bricle031@gmail.com>
2025-10-09 09:36:10 +02:00
Camille BAUD
d6d21ec3ec drivers: display: Introduce st730x display controller
Introduces epaper-like high resolution st730x serie controllers. b&w only

Signed-off-by: Camille BAUD <mail@massdriver.space>
2025-10-08 18:28:28 -07:00
Marc Espuña
5b595e33eb drivers: display: uc8151d: Add UC8151D display controller support
Add support for the UltraChip UC8151D e-paper display (EPD) controller.
The UC8151D is part of the UC81xx family of display controllers commonly
used in e-ink displays.

This implementation extends the existing UC81xx driver infrastructure by
adding device tree bindings, Kconfig options, and the necessary driver
code to support the UC8151D variant.

Signed-off-by: Marc Espuña <mespuna@cactusiot.com>
2025-10-08 15:08:57 -04:00
Marcio Ribeiro
e8c6695f08 drivers: adc: esp32: split adc_esp32.c between 2 files
Splits driver source code between adc_esp32.c and adc_esp32_dma.c to
improve maintenance

Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
2025-10-08 17:47:42 +03:00
Marcio Ribeiro
a96e18de97 drivers: adc: esp32: enable adc dma on non gdma socs
Enables adc dma on:
- esp32
- esp32-s2

Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
2025-10-08 17:47:42 +03:00
Michał Bainczyk
aa5b47634f drivers: timer: nrf_grtc_timer: use a function for cc enable check
Instead of checking register values directly, use a function from
nrfx that does this.

Signed-off-by: Michał Bainczyk <michal.bainczyk@nordicsemi.no>
2025-10-08 17:47:32 +03:00
Sašo Domadenik
2ac238cce0 drivers: sensor: ds18b20: Fix temperature calculation for ds18s20
The millionths value is calculated incorrectly.
The sensor has a precision of 0.5 which is 500000 millionths, but
there is an extra zero in the code. This fix removes the extra zero.

Signed-off-by: Sašo Domadenik <saso.doma@gmail.com>
2025-10-08 17:47:10 +03:00
Declan Snyder
f56f1967e0 drivers: uart_mcux_lpuart: Handle multiple uart case
Handle the case where there are multiple different kinds of UART on one
platform, the other UART driver select SERIAL_SUPPORT_ASYNC but LPUART
did not, causing build error in LPUART driver. Shield LPUART driver from
this case by introducing driver config to indicate that in fact LPUART
is the one enabling ASYNC.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2025-10-08 17:47:00 +03:00
Benjamin Cabé
3168f0645e drivers: rtc: rv3032: fix clang error label followed by a declaration
Declare variable at the beginning of the function since having it
declared in the default case makes clang unhappy (can't declare a
variable after a label).

Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
2025-10-08 17:46:24 +03:00
Jacky Lee
83afba85d1 driver: Reuse andes_cache driver for compatible MCUs
Fixed a wrong function declare of 'nds_l2_cache_init'.
Replace `SOC_FAMILY_ANDES_V5` with `DT_HAS_ANDESTECH_ANDESCORE_V5_ENABLED`
condition to enable it to be used by compatible MCUs

Signed-off-by: Jacky Lee <jacky.lee@egistec.com>
2025-10-08 12:15:44 +02:00
Andre Heinemans
8760db3016 drivers: flash: flexspi_mx25um51345g: fix erase chip lut entry
The DDR LUT entry for ERASE_CHIP was configured with an incorrect
kFLEXSPI_Command, resulting in the erase operation not being executed.

Signed-off-by: Andre Heinemans <andre.heinemans@nxp.com>
2025-10-08 12:04:52 +02:00
Andre Heinemans
6a714d55d9 drivers: flash: flexspi_mx25um51345g: get max speed from dts
The maximum speed should be configured individually for each board
since it depends on the layout and the controller's flexspi capabilities.

Signed-off-by: Andre Heinemans <andre.heinemans@nxp.com>
2025-10-08 12:04:52 +02:00
Andre Heinemans
e774d82cbe drivers: flash: flexspi_mx25um51345g: fix DDR dummy cycles
In the DDR LUT, the dummy cycles were not defined for READ_STATUS_REG
and had a wrong value for READ.
The default amount of dummy cycles on this chip are 20 (0x14).
This means the LUT should contain the value of 0x28 (0x14*2) for DDR
at these entries.

Signed-off-by: Andre Heinemans <andre.heinemans@nxp.com>
2025-10-08 12:04:52 +02:00
Dipak Shetty
5a018375e3 drivers: rtc: microcrystal rv3032 driver introduced
Added new driver for Micro Crystal RV-3032-C7 Real-Time
Clock Module.

Signed-off-by: Dipak Shetty <shetty.dipak@gmx.com>
2025-10-08 10:09:21 +02:00
Adam BERLINGER
b5c7a67e77 drivers: i3c: stm32: Fix issue with DAA command
The TXFNF needs to be disabled for additional I3C targets
during the DAA process. Otherwise the TX interrupt might be triggered
before receiving full PID for target.

Signed-off-by: Adam BERLINGER <adam.berlinger@st.com>
2025-10-08 10:09:12 +02:00
Karsten Koenig
24353a8938 drivers: misc: nordic_vpr_launcher: Init order
Make sure the nordic_vpr_launcher gets started after the coresight
driver if that is present.

Signed-off-by: Karsten Koenig <karsten.koenig@nordicsemi.no>
2025-10-08 10:09:02 +02:00
Karsten Koenig
6066a42748 drivers: debub: coresight: Added coresight_nrf
Added driver and bindings for the coresight nrf submodule.
add integrated it for the nrf54h20.
The coresight subsystem is a combination of ARM Coresight peripherals
that get configured together to achieve a simplified configuration based
on a desired operating mode.

This also replaces the previous handling in the nrf54h20 soc.c which was
powering the subsystem up but not configuring it.

Signed-off-by: Karsten Koenig <karsten.koenig@nordicsemi.no>
2025-10-08 10:09:02 +02:00
Karsten Koenig
85363f9e53 drivers: pinctrl_nrf: Add coresight tpiu pins
Pinctrl needs to set the needed drive and direction of the pins. Also
this later allows automatically setting the clock bit for the traceclk
pin.

Signed-off-by: Karsten Koenig <karsten.koenig@nordicsemi.no>
2025-10-08 10:09:02 +02:00
Karsten Koenig
d833556ee5 drivers: debug: Moved nrf_etr from misc
Moved the nrf_etr driver from the drive/misc folder into the recently
established driver/debug folder where it is a better fit. Moved the
associated files such as bindings and headers accordingly as well.

Signed-off-by: Karsten Koenig <karsten.koenig@nordicsemi.no>
2025-10-08 10:09:02 +02:00
Bill Waters
e9a6799736 drivers: i2c: minor update to Infineon driver
- update to the new name of the function used from
  the serial driver

Signed-off-by: Bill Waters <bill.waters@infineon.com>
2025-10-08 08:45:48 +02:00
Torbjørn Biering Tvermosegaard
863a7668b3 drivers: adc: ad599x: Fix async logic error and driver breakdown
The general ADC documentation states, that it is possible to use the
adc_read_async function with third parameter (k_poll_signal *async) set to
NULL, in which case the callback is called when all channels have been
converted. This change fixes this issue as it now also checks if a callback
has been set.

Signed-off-by: Torbjørn Biering Tvermosegaard <tbt@foss.dk>
2025-10-08 08:45:08 +02:00
Zhaoxiang Jin
c78e45a31a drivers: counter/lptmr: Enable lptmr get_freq feature
Enable lptmr get_freq feature.

Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
2025-10-07 23:02:45 -04:00
Ryan McClelland
06f9155dcf drivers: i3c: dw: fix bus free timing for pure bus
For a i3c pure bus, the bus free timing shall be set to tcas
which is 38.4ns according to table 49 of the MIPI I3C v1.2
specification.

For a i3c mixed bus, the bus free timing shall be set to the scl
low time. Based on the i2cs' lvrs, it can determine if any devices
only support fast mode and won't do fast mode plus to determine
which tLOW setting it should use for bus free.

Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
2025-10-07 23:00:47 -04:00
Khanh Nguyen
65bf8f9461 drivers: video: ctrls: correct assertion in video_cluster_ctrl
The function asserted `!sz && !ctrls`, which is the inverse of the
intended precondition. This caused assertion failures on valid inputs.

Update the check to `sz && ctrls` so it fails only when size is zero
or the control pointer is NULL.

Signed-off-by: Khanh Nguyen <khanh.nguyen.wz@bp.renesas.com>
2025-10-07 23:00:05 -04:00
Khanh Nguyen
6f431a423b drivers: video: ov5640: support DVP bus-width and data-shift from DTS
Add support in the OV5640 driver to configure the bus-width and
data-shift properties from devicetree when operating in DVP
(parallel) mode.

This allows the number of parallel data lines and the bit shift
to be set directly via DTS, ensuring correct configuration across
different hardware designs.

Signed-off-by: Khanh Nguyen <khanh.nguyen.wz@bp.renesas.com>
2025-10-07 23:00:05 -04:00
Khanh Nguyen
804f893e89 drivers: video: ov5640: Use CCI API helpers for register access
Replace the custom I2C read/write functions in the OV5640 driver
with the common Video CCI API helpers.

- Introduce OV5640_REG8/REG16 macros for register addressing
- Convert struct ov5640_reg to struct video_reg16
- Replace ov5640_{read,write,modify}_reg() with CCI API helpers
- Replace ov5640_write_multi_regs() with video_write_cci_multiregs16()

This aligns the OV5640 driver with other video sensor drivers
that already rely on the CCI helpers.

Signed-off-by: Khanh Nguyen <khanh.nguyen.wz@bp.renesas.com>
2025-10-07 23:00:05 -04:00
Anisetti Avinash Krishna
709f453673 drivers: gpio: Enable support for latest GINF method
Enable support for latest GINF method which requires 3 paramters
for each GPIO group and enables gpio support for intel_ptl_h
platform.

Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
2025-10-07 22:59:32 -04:00
Jakub Zymelka
e5ecbd2112 drivers comparator: nordic: Align drivers to changed analog input types
External analog input types changed from `string` to `int`.

Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
2025-10-07 22:58:20 -04:00
Quang Le
77c1aed630 drivers: clock control: Add Clock Control support for RZ/N2L, T2M
Add Clock Control driver support for Renesas RZ/N2L, T2M

Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
2025-10-07 22:58:03 -04:00
Camille BAUD
a9b9416b28 drivers: display: Introduce SSD1357
It is almost identical to SSD1351

Signed-off-by: Camille BAUD <mail@massdriver.space>
2025-10-07 22:57:39 -04:00
Martin Jäger
866dff0eb0 drivers: flash: stm32g0: Implement set|get_rdp_level API
Allows to set readout protection bits for this series at runtime.

Signed-off-by: Martin Jäger <martin@libre.solar>
2025-10-07 22:56:52 -04:00
Martin Jäger
faf661e907 drivers: flash: stm32g0: Implement option_bytes_write|read API
Implementation based on STM32G4 series.

This is a preparation to enable reading and writing the RDP bits.

Signed-off-by: Martin Jäger <martin@libre.solar>
2025-10-07 22:56:52 -04:00
Hui Bai
50ac559152 drivers: wifi: Add WLAN wakeup for MIMXRT1060-EVK
Added wlan wakeup pin in IW610 overlay file. This WLAN wakeup
support is for IW610 and MIMXRT1060-EVK acts as host. Add wakeup
pin configuration when doing device related initialization.

Signed-off-by: Hui Bai <hui.bai@nxp.com>
2025-10-07 22:55:21 -04:00
Anas Nashif
bf82f7ffac copyrights: fix copyright line
Add space before (c) to allow correct parsing by linters.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2025-10-07 22:53:45 -04:00
Armando Visconti
ea072d31ff drivers/sensor/: lis2dux12/lsm6dsv16x: use helpers
Make use of rtio_read_regs_async() and rtio_flush_completion_queue()
helpers in lis2dux12 and lsm6dsv16x sensor drivers.

Signed-off-by: Armando Visconti <armando.visconti@st.com>
2025-10-07 17:43:32 +03:00
Raffael Rostagno
1d2f012fbe drivers: counter: rtc: esp32: Add LP TIMER support
Add support to LP TIMER peripheral, for ESP32-C6 and ESP32-H2
RTC counter support.

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
2025-10-07 12:47:45 +02:00
Raffael Rostagno
01d430826e drivers: counter: rtc: esp32: Fix cancel alarm condition
Disable RTC interrupts when cancelling alarm, and clear callback
data, to make sure no ISR/callback is serviced after alarm is
cancelled. Also, check programmed ticks in ISR to make sure
alarm triggered is not an outdated/cancelled event.

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
2025-10-07 12:47:45 +02:00
Raffael Rostagno
16632333a2 drivers: counter: rtc: esp32: Fix overflow case
Fix alarm setting when timer has overflown beyond 32-bit boundary.
Timer is 48-bit, so it requires high word to be programmed along
the 32-bit word managed by the driver.

Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
2025-10-07 12:47:45 +02:00
Seppo Takalo
5fa605af17 drivers: modem: cellular: nRF91: Remove periodic chat script
Remove periodic chat script as the AT+CEREG=1 notifications are already
enabled.

Signed-off-by: Seppo Takalo <seppo.takalo@nordicsemi.no>
2025-10-07 12:47:19 +02:00
Fabian Blatz
bae6e3563b drivers: rtc: Add nxp,pcf85063a driver
Adds a driver implementation for the pcf85063a I2C rtc.

Signed-off-by: Fabian Blatz <fabianblatz@gmail.com>
2025-10-07 12:47:07 +02:00
Davi Herculano
d1493b60d6 driver: i2s: fix nxp i2s fifo combine values
MCUX defined RX fifo combine names and the
references need to be adjusted in the i2s driver.

Signed-off-by: Davi Herculano <davi.herculano@adam-audio.de>
2025-10-07 11:01:01 +02:00
Elmo Lan
c0a421c329 drivers: i2c_dw: Avoid spamming NACK error messages
NACK message now log with LOG_ERR_RATELIMIT
instead of LOG_ERR to reduce log noise.

When scanning I2C device,
receiving a NACK is expected behavior and not necessarily an error.
Logging it at LOG_ERR causes unnecessary clutter in the logs.

Therefore, the log level is change to LOG_ERR_RATELIMIT for NACK cases.

Signed-off-by: Elmo Lan <elmo_lan@realtek.com>
2025-10-07 10:59:52 +02:00
Jordan Yates
adecb09978 modem: select UART_USE_RUNTIME_CONFIGURE
Override any defaults for `UART_USE_RUNTIME_CONFIGURE` when using
`CONFIG_MODEM_CELLULAR`, as the baudrate update feature depends on it.

Signed-off-by: Jordan Yates <jordan@embeint.com>
2025-10-07 10:59:18 +02:00
Charles Hardin
2bfd76425a net: ip: account for the size in the inet_ntop code path
The code was writing to the dst without a verification check on
size which is not appropriate. The guard on the arguements should
be enforced and so just ensure the size is larger then the
definition of the strings from POSIX and return an error in those
cases.

Signed-off-by: Charles Hardin <ckhardin@gmail.com>
2025-10-07 10:59:08 +02:00
Alexander Kozhinov
7eb3b41e7d drivers: comparator: implement stm32 comparator driver
implement the driver for the stm32 comparator peripheral

Signed-off-by: Alexander Kozhinov <ak.alexander.kozhinov@gmail.com>
2025-10-07 10:58:31 +02:00
Jiafei Pan
8e0486d291 drivers: watchdog: wdog32: add imx9352 support
On i.MX 93 platform, no need to clear interrupt flags, otherwise it
will not trigger reset.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Signed-off-by: Joe Zhou <zhongcai.zhou@nxp.com>
2025-10-06 20:17:50 -04:00
Jiafei Pan
9f6a74506f drivers: watchdog: wdog32: add MMIO mapping support
Added MMIO mapping support in order to support on Cortex-A Core.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
2025-10-06 20:17:50 -04:00