Introduce a PECI transport driver that operates over the eSPI bus,
enabling platforms without a native PECI controller to communicate
with the host CPU via an embedded controller.
This driver:
- Implements the PECI transaction layer on top of eSPI OOB channel
- Serializes PECI transactions to ensure protocol correctness
- Integrates with the existing PECI core infrastructure
- Allows PECI consumers (e.g. DTT, thermal, power management) to remain
transport-agnostic
A corresponding devicetree binding enables PECI-over-eSPI by defining
a PECI child node under the eSPI controller node.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
set BUF21 mode after enabling regulator, to ensure the buffered
output is available for the LPADC's VREFI reference.
This fixes an issue where the LPADC would produce inaccurate
conversion results due to BUF21 being left disabled.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Add an invert-direction boolean DT property that negates the axis value
reported by the event worker. This handles boards where the physical
encoder orientation produces a direction opposite to what the quadrature
state machine reports without swapping the A/B GPIO wires.
Signed-off-by: Andrew Yong <me@ndoo.sg>
Fix the test on the number of arguments in the erase command
to get the optional size argument that was mistakenly increased by
cb2382d25b ("drivers: flash: flash_shell.c: Requires device on
destructive ops") and made the argument never considered.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
as the ethernet api already includes
struct net_if as a argument for its
functions also add it to struct wifi_mgmt_ops.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Introduce CONFIG_RISCV_S_MODE to select Supervisor-mode execution.
Add depends on !RISCV_S_MODE to RISCV_PMP since PMP CSRs are
inaccessible from S-mode.
Add an M-mode SBI shim (reset.S + sbi.S) that configures exception
delegation, PMP, and counter access before dropping to S-mode via mret.
The shim handles SBI_SET_TIMER ecalls from S-mode and forwards MTIP to
STIP so the supervisor timer driver works without a full SBI firmware.
Introduce privilege-level abstractions in isr.S (RV_CAUSE, RV_EPC,
RV_STATUS, RV_TVAL, etc.) and update all runtime code that previously
accessed M-mode-only CSRs (mcause, mtval, mstatus, mie, mip) to use the
S-mode equivalents when CONFIG_RISCV_S_MODE is set.
ARCH_EXCEPT in kernel context uses ebreak (cause=3, Breakpoint) instead
of a direct z_riscv_fatal_error() call. In S-mode, ecall (cause=9) is
kept in M-mode for SBI and never reaches the S-mode exception handler;
a direct call with NULL esf caused the stack unwinder to crash into an
infinite fault loop. ebreak is delegated to S-mode by our medeleg
configuration; isr.S treats ebreak with t0=RV_ECALL_RUNTIME_EXCEPT the
same way M-mode treats ecall-based ARCH_EXCEPT.
Signed-off-by: Alexios Lyrakis <alexios.lyrakis@gmail.com>
-Add inband independent reset support for IW612, IW416 and IW610
-Add kconfig option to enable/disable IR support
Signed-off-by: Vinit Mehta <vinit.mehta@nxp.com>
Add function to read the state of the monitored external power at startup.
Needed when controller can startup with monitored external power rails
beeing powered or not. The actual read of the state is not done during
init but deferred to a later stage after all child devices of this power
domain are also initialized and are able to receive a PM action callback.
A Kconfig switch CONFIG_POWER_DOMAIN_GPIO_MONITOR_INITIAL_READ is
introduced to optionally turn on this feature.
Signed-off-by: Thomas Decker <decker@jb-lighting.de>
The new hardware supports fifo mode for all i2c channels. This commit
adds support for fifo mode across all i2c channels.
Additionally, the compilation fails when the `I2C_IT51XXX_FIFO_MODE`
option is disabled because the isr function is behind this option.
This change also resolves this issue.
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
Explicitly casting a `const void *` to an end data type is unnecessary,
introduces the opportunity to mis-cast the `const` qualifier and goes
against the direction decided in:
https://github.com/zephyrproject-rtos/zephyr/issues/37616
Signed-off-by: Jordan Yates <jordan@embeint.com>
Explicitly casting a `const void *` to an end data type is unnecessary,
introduces the opportunity to mis-cast the `const` qualifier and goes
against the direction decided in:
https://github.com/zephyrproject-rtos/zephyr/issues/37616
Signed-off-by: Jordan Yates <jordan@embeint.com>
- Add DMA support for SPI on RZ/N2L, T2M since the previously supported
had not support DMA.
- Add initial support SPI driver for board RZ/T2L.
Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
- Introduce support for the DesignWare I2C specific core clock frequency
optimization feature (IC_CLK_FREQ_OPTIMIZATION).
- This feature reduces the internal latency cycles required to generate
the SCL high and low periods, allowing the controller to achieve target
bus speeds with a lower input clock (ic_clk) frequency.
- The driver now supports both standard calculation (optimization=0) and
the new optimized mode, selectable via Kconfig. This ensures
compatibility with existing hardware while enabling the optimization
on platforms that support it.
Signed-off-by: Shreehari HK <shreehari.hk@alifsemi.com>
- Replace hardcoded magic numbers for SCL High and Low Count register
minimum values with descriptive macros.
- The DesignWare I2C controller requires specific minimum values
(Section 2.14.1 of DW Spec) for IC_*_SCL_HCNT and IC_*_SCL_LCNT
registers based on the spike length (SPKLEN) configuration.
Specifically:
- HCNT must be at least IC_*_SPKLEN + 6
- LCNT must be at least IC_*_SPKLEN + 8
- Using macros improves readability and maintainability by documenting
the source of these constraints and ensuring consistency across the
driver.
Signed-off-by: Shreehari HK <shreehari.hk@alifsemi.com>
Previously, the spike length suppression was only configured in the
master mode. This resulted in the slave mode
missing this configuration.
Move the spike length setting to the common initialization function
to ensure it is applied for both master and slave modes.
Signed-off-by: Shreehari HK <shreehari.hk@alifsemi.com>
This patch applies a software reset command under the condition that no
gpio reset pin is assigned and the new introduced boolean softreset-on
had been set for the device in the device tree or overlay.
Signed-off-by: Chris Ruehl <chris@gtsys.com.hk>
Check that the controller and PHY clock devices are ready, then
enable the clocks with clock_control_on() before calling
clock_control_set_rate().
This lets the EHCI driver bring up RT7xx USB clocks from the
devicetree clock description.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Add RT7xx USB controller and PHY clock IDs to the MCUX SYSCON
bindings and handle them in the shared clock control driver.
This allows RT7xx USB clocks to be enabled through the common
clock control API.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
The comment is correct, the code was wrong. Each chunk can be 64 bytes of
data, but they also have 4 byte headers. So to be able to read 255 chunks
with 64 bytes of data each, The buffer has to be 255 * 68.
Signed-off-by: Michael Zimmermann <michael.zimmermann@sevenlab.de>
WPA3 (aka SAE) uses different fields for password and password length,
pass the proper ones to whd_wifi_join depending on usr_result.security.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Add sys_clock_is_locked(), the analog of z_spin_is_locked() for the
timer lock exposed via sys_clock_lock(). Use it to assert lock
ownership in sys_clock_set_timeout() and sys_clock_elapsed() of the
six timer drivers that were migrated to sys_clock_lock() and
consequently no longer acquire anything internally in those callbacks
(arm_arch_timer, riscv_machine_timer, xtensa_sys_timer, hpet,
apic_tsc, intel_adsp_timer).
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
The straightforward way to convert cycles to nanoseconds with
x * y / z
will easily overflow the multiplication in the numerator. Rewriting the
operation as
y * (x / z + (x % z) / z)
or NSEC_PER_SEC * (quot + (rem / cycles_per_sec)) improves the situation
and allows useful sensor timestamps for a bit longer before overflows are a
concern.
The API in sys/time_units.h handles exactly this type of numerical
manipulation for time units which might overflow. The predefined macros
only handle conversions between the various Z_HZ_* macros so a wrapper for
z_tmcvt_64 is required for the external clock case.
Signed-off-by: Henrik Lindblom <henrik.lindblom@vaisala.com>
Add PWM driver support for Realtek Bee series SoCs,
including RTL87x2G and RTL8752H.
This driver supports:
- Pulse width modulation output
- Period and pulse width configuration
- Polarity inversion
Signed-off-by: Yuzhuo Liu <yuzhuo_liu@realsil.com.cn>
add reset controller support to the NXP LPSPI driver and
use reset controller APIs if available.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
add reset controller support for the mcux lpi2c driver and
use reset controller APIs if available.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Add optional devicetree reset support to the i.MX USDHC
driver and deassert the reset line before controller
initialization.
Keep existing behavior unchanged when no reset is described.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
add reset controller support for NXP SEMA42 hardware
spinlock driver, and use reset controller APIs if available.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
RT700 numbers PRSTCTL registers in a global namespace across
multiple RSTCTL instances, while the existing driver assumes
per-instance local offsets.
Add an optional offset-base devicetree property and normalize
reset IDs before accessing the controller registers. When the
property is not present, keep the existing behavior unchanged.
This keeps the driver backward compatible for current users while
allowing RT700 reset specifiers to follow the SDK/manual numbering.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Add support for the i2c .recover_bus api in Infineon's i2c_pdl
driver. This uses the functions defined in i2c_bitbang.c to cause a
release of an improperly held sda line.
Additionally, changes are made to the driver's relevant Kconfig
and i2c binding .yaml files. This adds definitions for the sda and scl
bins for recovery purposes. The .recover_bus api is set to depend on the
"scl_gpios" and "sda_gpios" variables being set up in devicetree.
Assisted-by: GitHub Copilot:claude-sonnet-4.6
Signed-off-by: McAtee Maxwell <maxwell.mcatee@infineon.com>
In #90652 we removed phy related config from eth api,
unfortunatly ETHERNET_CONFIG_TYPE_T1S_PARAM was forgotten
to be removed.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
When the transmit FIFO is full and poll_out checks for availability,
it will read the register value only once and block forever. Make
the uart_aesc_regs struct volatile to read the FIFO availability
during each check.
Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
Even though compat "st,stm32f1-flash-controller" is also used by stm32f0,
stm32f3, stm32l0 and stm32l1 series, these series don't share exactly
the same members of FLASH_TypeDef and OB_TypeDef structures.
For example, the CR member is available on F1 but not on the L0 series.
There is also issue with missing variables or naming conventions :
- FLASH_OBR_RDPRT (F1) vs FLASH_OBR_RDPRT1 (F0)
- RDP_KEY present in F1 series and not in others.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
Add support for STM32WB0 series to the STM32 HWINFO driver, using the SoC's
`UID64` as source for both UID and EUI64.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
The modem_cmd_handler_config struct doesn't have any return value.
The modem_cmd_send_data_nolock function returns 0 if ok, < 0 otherwise.
This behavior is expected to have been implemented in the called write
function.
Signed-off-by: Eliott Speyser <eliott.speyser@st.com>
Instead of performing series check, use the new common Kconfig option
CONFIG_HAS_STM32_UNCACHED_ACCESS_ONLY_OTP in drivers which access the
internal NVM's OTP/read-only area.
While at it, use the public `sys_cache_xxx()` API in flash_stm32 instead
of the internal `cache_xxx()` API.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
