current the dir-pin is getting set each and every time perform_step
is called, this is inefficient, since the direction pin shall be set
only once, when a motion command(move_by/move_to/run) is called.
Signed-off-by: Jilay Pandya <jilay.pandya@outlook.com>
The SNVS RTC can act as a wakeup source, re-use pm.yaml properties and
remove the Kconfig symbol.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
There are multiple bugs related to continuous/circular mode.
Continuous/circular mode is where the DMA runs continuously
until the stop API is called, instead of auto-stopping on
completion on a single transfer. After a stop, the DMA
can then be reconfigured/restarted.
1. Fix bug where stop didn't actually stop. This can cause memory
corruption if the user thought the DMA stopped and repurposed
the dest memory, but in fact the DMA is still writing to it.
The bug was due the incorrect usage of the DMA controller busy
state. The DMA controller is busy only when a transfer is
actively in progress, but the driver needed to stop even if
the transfer is not active but is only enabled (and may become
active on a subsequent trigger event). Change so that data->busy
doesn't use the DMA controller busy state but tracks the enable
state. Also, to make it doubly safe, make stop function always stop
regardless of data->busy state because it is alway safe/correct
to do so.
2. Fix race condition where a stop request from another ISR might race
with a DMA completion interrupt, and the DMA completion callback
gets invoked after the DMA has already been stopped. The fix
is to unregister the callback with the sdk DMA driver, so the
ISR still runs and clear the interrupt without invoking the
callback. There is potentially still a race if the interrupt
is restarted before the ISR fires, so the callback might be
called too early. However, the Zephyr DMA driver doesn't
have the channel level details that the SDK driver does and
it cannot clear just the channel interrupt.
Also a couple of general fixes/improvements:
a. Use interrupt B for end of transfer (single transfer or end
of block list). Use interrupt A for interrupts of a block
in the middle of a transfer or for continuous/circular transfers.
This fixes the dma callback so it can properly report
DMA_STATUS_BLOCK vs DMA_STATUS_COMPLETE.
b. Reorder some fields in struct channel_data to pack a little
better in memory
Signed-off-by: Mike J. Chen <mjchen@google.com>
The dma driver was determining src_inc and dst_inc from the
config of the first block buffer and ignoring the config
flags for any additional buffers in the chain, which could
lead to incorrect transfers (e.g. in a multiple rx buffer
case, if the first buffer was to receive to NULL,
but the subsequent buffers were not NULL, the bug
would manifest as all transfers being made with
dst_inc of 0). Change the driver to setup
each dma descriptor according to the addr_adj flag
of each block_buffer.
Add check that peripheral transfers have addr_adj set to
NO_CHANGE instead of assuming it, to help catch errors.
Also now check for invalid addr_adj request of
decrement, which this controller doesn't support.
Signed-off-by: Mike J. Chen <mjchen@google.com>
The spi_mcux_flexcomm driver uses a special last DMA blk_cfg
to trigger a release of the SPI chip select. This transfer
is always a 4-byte transfer, regardless of the width specified
during dma_configure().
The way the spi_mcux_flexcomm driver communicated this special
transfer was kind of a hack, where the dma_mcux_lpc driver would
assume that when a blk_cfg with source_addr_adj and dest_addr_adj
both set to NO_CHANGE was for this SPI_TX special case.
However, this is an unsafe hack since it is perfectly valid
to have dma use cases for both src/dest_addr_adj to be NO_CHANGE
that is not for SPI_TX. One example is when transmitting a
fixed/repeating value to a periperhal address (e.g. send 100
bytes of the same value from a single memory address over SPI).
This CL introduces a dma_mcux_lpc specific dma channel_direction
which the two drivers now use to cleary request this special
transfer case.
Signed-off-by: Mike J. Chen <mjchen@google.com>
In spi_mcux_transfer_next_packet(), if the next
transfer start fails, add calls to
spi_context_cs_control() to release cs and
spi_context_complete() with error code -EIO.
Signed-off-by: Mike J. Chen <mjchen@google.com>
The current driver implementation would block even when the async
API was invoked, so it wasn't really async.
This CL also fully chains the DMA transfer using multiple dma blocks
and makes the number of dma blocks available a config value. The
increase in number of dma blocks is needed so that a spi_buf_set
that has many entries can be converted into chained dma transfers
with the last transfer in a separate block that will set the EOT flag.
Also make some improvements:
1) When doing single cnt transfer, don't use the SDK driver but
use a new fucntion spi_mcux_transfer_single_word().
It's much more efficient and does not use an ISR
like the SDK function does just to send one word.
2) Fix calls to spi_context_update_tx/rx() so that the
correct word size is passed in, instead of previously
being hardcoded to 1. This only matters when word size
is two. Evaluate the word_size_bytes and word_size_bits
once and store the values in data instead of computing
it multiple times in various parts of the driver
3) When CONFIG_SPI_MCUX_FLEXCOMM_DMA is defined, we
do not use the IRQ handler, so add #ifdefs to compile
that code out. This reduces code size.
Signed-off-by: Mike J. Chen <mjchen@google.com>
This reverts commit a3530d6a43.
This change incorrect if chip-select is via a GPIO pin,
released by spi_context_cs_control(), and not the controller
default chip-select pin that can be released using a final
FIFOWR.
When GPIO is used for chip-select control, the chip-select could
be released too soon because the transfer callback is invoked
when the last byte is put into the TX FIFO but that byte might
not yet have clocked out yet on the SPI pins. The rx part of
the transfer is really what completes the transfer so ignoring
it is incorrect.
We could try to special case and use ignore only when
spi_context_cs_control() does nothing, but since it is a very
small optimization, it doesn't seem worth the extra
complexity.
Signed-off-by: Mike J. Chen <mjchen@google.com>
Added scmi_cpu_pd_lpm_set api for nxp imx scmi interface
This api set the lpm setting for some peripherals applied
when cpu enter a low power mode, such as keep iMX95 wakeup mix
power on when M7 core enter suspend mode, scmi agent record and
deal with this request
Signed-off-by: Yongxu Wang <yongxu.wang@nxp.com>
SCMI processor interrupts from agent are enabled by default during the
`setup_chan` initialization phase. This is suitable for interrupt-driven
communication, where the agent triggers an interrupt to notify the platform
after completing a message transaction.
However, when using the polling model, interrupts are not required and may
cause unintended behavior or performance issues in PM.
To ensure correct operation under polling mode, the interrupt should
be explicitly disabled after channel setup.
Signed-off-by: Yongxu Wang <yongxu.wang@nxp.com>
SCMI supports both polling and interrupt modes for message completion.
Previously, the scmi_send_message() API used a 'pre_kernel' flag to
determine which mode to use_polling during the pre-kernel phase and
interrupts post-kernel.
This approach tightly coupled the decision logic with kernel state,
limiting flexibility. In particular, certain power management (PM)
related SCMI APIs require polling mode even in post-kernel context
to avoid unintended CPU wakeups caused by interrupts.
This patch replaces the 'pre_kernel' with a more generic
'use_polling' parameter, allowing callers to explicitly specify
the desired behavior. Typical usage can still rely on k_is_pre_kernel()
to determine polling mode in higher level api, while PM related
calls can directly enforce polling regardless of kernel state.
Signed-off-by: Yongxu Wang <yongxu.wang@nxp.com>
support interrupts for rx_ready, so we can use the
time we are waiting for other stuff.
implement async spi transfers.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
This property allows a user to specify the operation of a
pin in sleep mode.
By default, pins are configured to be output low in sleep mode.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
the commit adds sys_mm_drv_map_page_safe and sys_mm_drv_map_region_safe
functions, wrappers for sys_mm_drv_map_region and sys_mm_drv_map_region,
with additional check if a mapped region fits into given memory range
Using of those prevents collisions and/or hijacking of virtual memory
Signed-off-by: Marcin Szkudlinski <marcin.szkudlinski@intel.com>
this marker is an address of the very first byte not used by the linker,
with alignment to cacheline
Signed-off-by: Marcin Szkudlinski <marcin.szkudlinski@intel.com>
this commit removes creation of virtual memory regions from
Zephyr, allowing the application to create required regions
It is up the application to use virtual memory as needed,
zephyr however is keeping the table and ensures no memory
addresses overlaps
Signed-off-by: Marcin Szkudlinski <marcin.szkudlinski@intel.com>
Use channel 0 for RTC wrapping. Skip that channel when processing
channels.
Fix algorithm that prevents setting CC=0 when custom wrapping is used.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Currently the build assert checks the number of I2C instances as
the available I2C target mode, which is incorrect.
This patch updates the build assert to check the I2C port_num instead,
since IT51xxx only supports I2C target mode on ports 0 to 2.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Update the initializers to support platforms with multiple instances
of the DesignWare interrupt aggregator. Also ensure that the initialize
function calls irq_enable(). The calculation of the _sw_isr_table entry
also now takes CONFIG_GEN_IRQ_START_VECTOR into account.
Signed-off-by: Aaron Fong <afong@tenstorrent.com>
Some NXP SoCs have dedicated interrupts for controller and target roles.
The i2c_mcux_lpi2c driver connects only one interrupt.
Add connection of the second interrupt, if enabled, to support SoCs with
split role interrupts.
Signed-off-by: Michal Smola <michal.smola@nxp.com>
- Adds JEDEC-ID check to the flash_mcux_flexspi driver
if it is defined in DTS.
- Avoids applying DTS settings to a different flash module.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
We need to add CONFIG_DMA_MAX_DESCRIPTOR=16 for a lot of tests, then
this default value of this parameter need to be higher. It allows to
delete some overlay files.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
The LDMA driver currently has a 1:1 mapping between hardware LDMA
descriptors and struct dma_block_config. This patch allows multiple
hardware descriptors to be allocated for a single struct dma_block_config
if the block size exceeds the transfer capacity of a single hardware
LDMA descriptor. This is beneficial for other peripheral drivers: it is
no longer necessary to split the payload by the transfer capacity of a
single hardware LDMA descriptor.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
Introduce the ACE 4.0 architecture, along with support for the NVL and
NVL-S platforms within the Intel ADSP framework in the Zephyr project.
This update includes:
- Addition of ACE 4.0 architecture configurations in Kconfig and
Kconfig.intel_adsp.
- Inclusion of device tree source files for NVL and NVL-S platforms,
defining CPU, memory, and peripheral configurations.
- Updates to driver files to support ACE 4.0 specific features,
including DMIC and SSP configurations.
- Introduction of new header files for ACE 4.0, detailing boot,
interrupt, IPC, power, and shim functionalities.
- Modifications to the CMakeLists.txt to include ACE 4.0 MMU support.
- Addition of default configurations for NVL and NVL-S platforms in
Kconfig.defconfig.ace40.
The NVL and NVL-S platforms are part of the Nova Lake series, targeting
advanced audio processing capabilities. ACE 4.0 introduces enhanced DSP
capabilities and advanced power management features, improving audio
stream handling and synchronization compared to ACE 3.0.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
When the kso[17:16] lines are enabled and `CONFIG_ASSERT` is
configured, the following error occurs: "Input cannot be
enabled for 'Open Drain', 'Open Source' modes without Output."
To address this, this commit configures kso16 and kso17 as
gpio output before applying the pinctrl settings.
Tested with: no abnormal keyscan occurs during
initialization
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
To reduce power consumption, the SPI clock is gated when no spi
transaction is in progress. With this mechanism, current
consumption is reduced by approximately 0.1mA when cpu idle.
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
This commit removes gpio-based cs support as it8xxx2 spi
only supports transactions using the dedicated cs pin.
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
added Real-Time Clock driver support for Texas Instruments
MSPM0 Family, currently this driver supports rtc time keeping
and calendar alarms functionality
Signed-off-by: Karthikeyan Krishnasamy <karthikeyan@linumiz.com>
Use HAL functions, which also wait for reset to complete.
Remove unused register size and active-low DT props.
Signed-off-by: Dmitrii Sharshakov <d3dx12.xx@gmail.com>
Add a Kconfig option for setting the maximum acceptable deviation in sample
point location (permille).
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Fix the case where multiple I2S channels are used at
the same time by using the fifo combine feature.
Signed-off-by: Davi Herculano <herculanodavi@gmail.com>
