Add PIXEL_FORMAT_XRGB_8888 and the corresponding panel format.
Add support for this format in display_sdl driver as well.
Signed-off-by: Phi Bang Nguyen <phibang.nguyen@nxp.com>
syscon does not support clock get rate function for lpuart
for MCXL family.
Enable lpuart clock get rate function for MCXL family.
Signed-off-by: Michal Smola <michal.smola@nxp.com>
MCXL family has only PORT1, 2 and 3 controlled by syscon.
Do not enable clock for PORT0 in syscon driver.
Signed-off-by: Michal Smola <michal.smola@nxp.com>
The async mode ISR silently cleared RX error flags (overrun, parity,
framing, noise) without notifying the application. This violates the
Zephyr async UART API which requires a UART_RX_STOPPED event followed
by UART_RX_BUF_RELEASED and UART_RX_DISABLED.
Enable RX error interrupts alongside the idle-line interrupt, and
handle them in the ISR by reporting UART_RX_STOPPED with the
appropriate reason bitmask, then calling rx_disable() for the full
API-mandated teardown sequence.
Also set rx_dma_params.buf to NULL in rx_disable() after releasing
buffers, so stale pointers are not left behind.
Signed-off-by: Ofir Shemesh <ofirshemesh777@gmail.com>
Clear rx_dma_params.buf to NULL in mcux_lpuart_rx_disable() after
releasing all buffers. Without this, the stale pointer remains set
after RX teardown, which can cause subsequent checks against buf
to incorrectly assume RX is still active.
Signed-off-by: Ofir Shemesh <ofirshemesh777@gmail.com>
The PSOC4 flash driver accepted unaligned write offsets and sizes,
using a read-modify-write path to handle sub-row writes. This
violated the flash API contract, as the driver advertises
write_block_size=256 via devicetree.
Additionally, the Infineon HAL function Cy_Flash_WriteRow() requires
row-aligned addresses and exactly CY_FLASH_SIZEOF_ROW bytes of data.
The R-M-W path was passing unaligned addresses to the HAL, which
would reject them, but the driver was not checking the return value
and silently reported success after failed writes.
Add write alignment validation for both offset and size. Remove the
dead read-modify-write code path. Add missing error checking on
Cy_Flash_WriteRow() return value in the write loop, consistent with
the erase function.
Handle caller-provided data buffers that are not 4-byte aligned by
staging each row through a local aligned buffer before calling
Cy_Flash_WriteRow(), which requires a uint32_t-aligned source
pointer. When the source is already aligned, it is passed directly
with no copy overhead.
Signed-off-by: Braeden Lane <Braeden.Lane@infineon.com>
remove redundant net_pkt_set_iface() it is already set in
net_recv_data() and net_pkt_rx_alloc_with_buffer().
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
The previous 40 KB default heap was at the edge for the Wi-Fi driver,
which can lead to allocation failures. Increase to 50 KB to provide
adequate memory for Wi-Fi operation.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Extend the ESP32 Wi-Fi driver to support ESP32-C5, the first
Espressif SoC with dual-band Wi-Fi 6 (2.4 GHz and 5 GHz).
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Extend the ESP32 LEDC PWM driver to support ESP32-C5. Clear the
gamma RAM fade function on SoCs that have it to prevent stale
fade parameters from affecting duty cycle output.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Extend the ESP32 GDMA driver to support ESP32-C5. Add the C5 SoC to
the AHB GDMA configuration and define the per-channel interrupt
source mappings.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add ESP32-C5 support to the RTC counter driver. The C5 uses a
different LP timer interrupt status register field
(soc_wakeup_int_st) compared to other SoCs (alarm), requiring a
SoC-specific macro for the interrupt status check.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Extend UART and USB serial drivers to support ESP32-C5. Add UHCI0
compatibility macro since the ESP32-C5 HAL exports the UHCI
peripheral as UHCI instead of UHCI0.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add CLIC interrupt controller support for ESP32-C5. Set the SHV
(selective hardware vectoring) bit for each allocated interrupt
so the CLIC dispatches through the mtvt vector table.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Extend the ESP32 GPIO driver to support ESP32-C5 by adding the
SoC series to the register struct compatibility defines.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Disable the interrupt before reconfiguring its type to prevent
spurious triggers and edge detector asymmetry. Without this, the
first gpio_pin_interrupt_configure(GPIO_INT_EDGE_BOTH) can leave
the edge detector in an inconsistent state causing a persistent
timing offset between rising and falling edge detection.
Also skip the enable call when the requested mode is disable,
avoiding a redundant enable immediately after setting the type to
GPIO_INTR_DISABLE.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Introduce a system timer driver that uses the MAX32 Wake-up Timer as the
system tick source. This enables the MAX32 SoC family to use the WUT for
kernel timing operations.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
Add an HCI driver for the BL702 on-chip BLE controller. The controller
is a precompiled binary blob communicating via vendor on-chip HCI
functions (bt_onchiphci_send/bt_onchiphci_interface_init).
The driver:
- Translates between Zephyr HCI net_buf and the vendor's internal
packet structures for both TX (commands, ACL data) and RX (events,
ACL data)
- Uses a dedicated RX thread with FIFO+semaphore to dequeue messages
from the controller callback (which may run in ISR context)
- Reads the BLE MAC address from eFuse during initialization
- Supports multiple controller binary variants via Kconfig choice
(peripheral-only, multi-role, observer, etc.)
- Provides proper open/close lifecycle with RX queue draining
Also adds the DT binding (bflb,bl70x-bt-hci) and a bt-hci node in
the BL70X SoC dtsi (disabled by default).
Signed-off-by: William Markezana <william.markezana@gmail.com>
# Conflicts:
# drivers/bluetooth/hci/CMakeLists.txt
Add driver for the QST QMI8658A 6-axis inertial measurement unit
with accelerometer and gyroscope. Supports I2C bus, configurable
full-scale range and ODR via devicetree, temperature readout, and
optional data-ready interrupt trigger on INT2.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Adds runtime device power management support to MAX32 Wake-up Timer
driver. The suspend routine is intentionally left unimplemented to
allow the Wake-up Timer to continue counting while the device is in
sleep mode.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
MSIS and MSIK requires either LSE at 32.768kHz or HSE at 16MHz or 32MHz
to enable their PLL mode for auto-calibration.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Correct assertion on MSIS/MSIK PLL mode configuration regarding
dependency on LSE clock rate and MSIS/MSIK source clock.
While at it, replace the runtime assertion with a build time assertion
and move all the MSIS/MSIK configuration assertion outside
set_up_fixed_clock_sources() local function.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Change STM32_LSE_ENABLED, STM32_MSIS_ENABLED and STM32_MSIK_ENABLED
macros to not be defined when the related clock is not enable in Zephyr
scope. This is their expected state where used in the implementation
(e.g., relying on #ifdef) but at a few places regarding STM32_LSE_ENABLED
that are also fixed by this change. While at it, replace two runtime
assertions with build time assertions.
This change makes these macros more consistent with the other
main clock enable state macros (STM32_LSI_ENABLED, STM32_HSI_ENABLED,
STM32_HSE_ENABLED, etc...).
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Fix two bugs in the timer counter driver that prevent tests
from passing.
-EBUSY should be returned from set_top_value() if there are
active alarms, not if the counter has been started.
The ISR should only process interrupts that are currently enabled,
not all pending flags.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
start rx and link status thread in iface init,
as only then the iface pointer in the data
struct is set.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
start rx and link status thread in iface init,
as only then the iface pointer in the data
struct is set.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
start rx and link status thread in iface init,
as only then the iface pointer in the data
struct is set.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
start rx and link status thread in iface init,
as only then the iface pointer in the data
struct is set.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Pass the function argument `dev` to the async callback instead of
`data->uart_dev`. The pointers are identical, but `dev` is already
available in this context, so it's clearer to use it directly.
Signed-off-by: Miguel Gazquez <miguel.gazquez@bootlin.com>
Add Ethernet support including:
- Board initialization code with PHY reset handling
- Device tree definitions for ethernet
- PHY link state tracking fixes in ethernet driver
Signed-off-by: Khai Cao <khai.cao.xk@renesas.com>
Create option CONFIG_CRC_STM32_DMA_THRESHOLD used to select between CPU and
DMA copy based on buffer size. Depending on the application and hardware,
it can be faster to perform a CPU copy for small buffer sizes than request
a DMA transfer: this options allows limiting DMA usage only to buffers of a
large enough size.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Add a new driver for the STM32 CRC. The driver is instance-aware and
supports data transfers using DMA.
Co-authored-by: Francois Ramu <francois.ramu@st.com>
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Allocating buffer in response to control transfer is part of processing
and therefore should not be done in UDC driver but rather in the stack.
Simplify UDC driver design by moving all control transfer buffer
allocations and processing to USB stack.
New control transfer handling flow is as follows:
1. USB stack allocates and queues buffer for Setup stage. This informs
UDC driver that USB stack is ready to process new transfer.
2. UDC driver completes enqueued Setup buffer. SETUP data may have
been received by device before Setup buffer was enqueued.
If multiple SETUP data was received, UDC driver must complete
request using last received SETUP data.
3. USB stack processes request. USB stack is responsible for:
* Stalling control endpoint when request cannot be processed
* Allocating and enqueueing Data stage buffer if necessary
- Depending on enqueued endpoint (IN/OUT), UDC driver is
expected to complete the transfer. If host sends new SETUP
data for any reason (e.g. timeout), then Data stage buffer
must be completed with -ECONNRESET code.
- UDC driver may postpone processing Data IN until USB stack
enqueues new Setup stage buffer.
* Handling status stage if applicable
- If Data IN was enqueued, stack immediately allocates and
enqueues Status OUT stage buffer.
- If Data OUT was enqueued, stack waits for Data OUT buffer
completion before doing any further processing.
- If control transfer handling fails, stack is expected to
STALL control endpoint.
* Allocating and enqueuing Setup buffer.
- This informs UDC driver that stack has finished processing
control transfer. UDC driver may choose to start processing
Data IN and/or Status OUT only after new Setup buffer is
enqueued.
4. UDC driver must fail (complete with -ECONNRESET) any enqueued and
not completed Data and Status buffers if host sends new SETUP data.
UDC driver must be able to buffer last received SETUP data until
USB stack is ready (enqueues Setup buffer).
5. UDC driver must complete all Data and Status buffers before it
completes Setup buffer.
6. UDC driver may keep ownership of Setup, Data and/or Status buffers
across USB bus resets. USB stack does not attempt to dequeue any
control transfer buffer it enqueued.
This approach implicitly synchronizes UDC driver against USB stack,
which ensures that only one set of Setup/Data/Status buffers is
allocated at a time.
Another advantage of the rework is drawing a clear line on buffer
ownership. The buffer responsibilities are as follows:
* USB stack is the only entity that both allocates and frees the
buffers. Only USB stack is allowed to set "setup", "data" and
"status" fields in struct udc_buf_info.
* UDC takes ownership of buffers handed to it in udc_ep_enqueue().
* UDC releases buffer ownership by calling udc_submit_ep_event().
Because there is just a single place where the buffer ownership changes,
and all buffers must go USB stack (alloc) -> UDC (perform requests on
the bus) -> USB stack (free) route it would be possible in the future to
implement a "tap" similar to Linux usbmon that would ease debugging.
This commit significantly changes how USB stack communicates with UDC
drivers. It was decided that supporting both the old and new model
simultaneously would require way too much effort. Therefore all UDC
drivers were reworked. Following people worked on driver rework:
* Tomasz Moń - ambiq, dwc2, kinetis, mcux ip3511, nrf, numaker,
renesas ra, rpi pico, smartbond, virtual
* Mathieu Choplain - stm32
* Mark Wang - mcux ehci
* Johann Fischer - sam0, stm32
* Ren Chen - it82xx2
* Brandon Hurst - max32
* Gerson Fernando Budke - sam udp, sam usbc, sam usbhs
Co-authored-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Co-authored-by: Johann Fischer <johann.fischer@nordicsemi.no>
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Co-authored-by: Mark Wang <yichang.wang@nxp.com>
Signed-off-by: Mark Wang <yichang.wang@nxp.com>
Co-authored-by: Ren Chen <Ren.Chen@ite.com.tw>
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
Co-authored-by: Brandon Hurst <brandon.hurst@analog.com>
Signed-off-by: Brandon Hurst <brandon.hurst@analog.com>
Co-authored-by: Gerson Fernando Budke <nandojve@gmail.com>
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Ble host and link layer threads initialization is no more done
during the system initialization.
Add stm32wba_ble_ctlr_thread_init() and
stm32wba_ll_ctlr_thread_init() functions calls
during ble and ieee802.15.4 driver initialization
Signed-off-by: Vincent Tardy <vincent.tardy@st.com>
In calculation of the FREQUENCY register value take into account
the tolerance of the peripheral clock to ensure that the SCL
frequency does not exceed the specified value.
Signed-off-by: Michał Bainczyk <michal.bainczyk@nordicsemi.no>
The nocache memory may not be freed when the `transferSofar` is 0, it
is allocated when (transferBuffer != NULL && transferLength != 0), so
release it with same conditions.
Signed-off-by: Mark Wang <yichang.wang@nxp.com>
Track success explicitly and only report timeout when no matching PHY ID
was found after all retries.
Extend the Motorcomm YT8521 PHY driver to support YT8531 chip.
The YT8531 is compatible with YT8521 and shares the same register
layout and configuration interface.
- "motorcomm,yt8521" for YT8521
- "motorcomm,yt8531" for YT8531
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
