Add counter driver for the Renesas RA Ultra-Low-Power Timer (ULPT)
with Kconfig, devicetree binding, and driver implementation
Signed-off-by: Khanh Nguyen <khanh.nguyen.wz@bp.renesas.com>
Signed-off-by: Khai Cao <khai.cao.xk@renesas.com>
Add support for CMD5, CMD52, CMD53 for Renesas RA to support
SDIO mode
Add interrupt enable/disable API and support SDIO in-band interrupt
callback
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Extend the MSPI QSPI controller driver to support the MCXE31X
series. Key differences from MCXE24X:
- No FIFO byte-swap needed (native LE byte ordering)
- Use QSPI_SetDelayChainConfig instead of QSPI_SocConfigure
- No dataHoldTime field (FSL_FEATURE_QSPI_HAS_NO_TDH)
Signed-off-by: Ruijia Wang <ruijia.wang@nxp.com>
Add QSPI Serial Flash Clock (SFCK) initialization and rate query
to the MC_CGM clock driver. Configures MUX_10 divider and selects
PLL_PHI1 as clock source when QSPI is enabled in devicetree.
Signed-off-by: Ruijia Wang <ruijia.wang@nxp.com>
Add MSPI controller driver for NXP QSPI hardware. The driver
dynamically builds LUT sequences from MSPI transfer parameters,
supporting single and quad SPI modes. It handles MCXE24X hardware
quirks including SFAR auto-reset, minimum 16-byte TX IDATSZ, and
big-endian FIFO byte ordering.
Signed-off-by: Ruijia Wang <ruijia.wang@nxp.com>
Choose the per-chip config at build time from the node compatible
instead of matching device-name at runtime.
Signed-off-by: Ruijia Wang <ruijia.wang@nxp.com>
Generalise the octal-only driver to a per-chip config and LUT table
so it can also drive the on-board Winbond W25Q512NW quad SPI NOR on
RT700 XSPI0. The octal path is unchanged.
Signed-off-by: Ruijia Wang <ruijia.wang@nxp.com>
Add memc_xspi_reset(): an XSPI software reset that invalidates the
controller's AHB read/prefetch buffer while keeping the LUT and device
config. The flash driver calls it after a program or erase so a
memory-mapped read issued right afterwards returns the freshly written
data instead of stale prefetched data.
Signed-off-by: Ruijia Wang <ruijia.wang@nxp.com>
Fixes an issue where scanning nested multifunction bridges premature-
dives down the first bridge function before processing peer functions
on the same slot. This can cause missing hardware tracking cells if
secondary buses aren't allocated in order.
Maintain the core DFS pattern but defer the vertical branch descent until
the horizontal function traversal across the parent slot node completes.
This queues the target buses into an array buffer to secure parent
interfaces before downstream enumeration begins.
Signed-off-by: Khadem Ullah <khadem.systems@gmail.com>
The VSC8541 MAC-interface pad edge rate depends on the VDDMAC supply
voltage and board-level signal-integrity requirements. The driver
currently leaves the setting at its reset default, so boards cannot
select the value recommended for their electrical design.
Add a microchip,pad-edge-rate devicetree property accepting values 0
through 7. Default it to 7 to preserve existing behavior, and program
the selected value into page 2 register 27 after the PHY software
reset.
Signed-off-by: Yasushi SHOJI <yashi@spacecubics.com>
lis2de12_enable_xl_int() hard-coded the CTRL_REG3 I1_ZYXDA routing bit
to 1, so disabling the data-ready trigger left INT1 asserted with a NULL
handler, wedging lis2de12_handle_interrupt() in an endless status-read
loop. Program the bit from the enable argument and leave the handling
loop when no handler is registered.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:fable-5
Add a short delay after asserting or deasserting reset bits in the
Intel SoC reset controller. Some reset lines were not released on
hardware because the sequence completed too quickly.
Signed-off-by: Syed Muhammad Murtaza <syedx.muhammad.murtaza@altera.com>
CTIMER_SetupPwmPeriod() only rewrites the match registers; it does
not touch TC. Shrinking the period while the timer is running can
leave TC above the new MR[period_channel] value, so the reset-on-
match condition never fires again until TC wraps around 32 bits,
freezing the output for up to 2^32 timer cycles.
Reset the counter whenever the period value actually changes.
Duty-cycle-only updates keep the counter running, so they introduce
no phase discontinuity.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
"Enhanced Max PS" is supposed to provide a workaround for AP which does not
support PS-Poll frames.
This mode take place of the Fast PS mode. In practice, users enabling this
compile time option will never be able to restore Fast PS behavior.
Considering the PS-Poll algorithm is very bandwidth limited (2Mbps Rx in
the best case), most of the users want Fast PS. So, enabling this option by
default is confusing for most of the users.
Change the default and update the description.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
get_state and disconnect are optional in mux_control_driver_api, and
z_impl_mux_state_get()/z_impl_mux_control_disconnect() return -ENOSYS
when the slot is NULL. Their verifiers used
K_SYSCALL_DRIVER_MUX_CONTROL(), which also asserts the op is non-NULL,
so a userspace caller got killed instead of the documented -ENOSYS:
mux_state_get() on nxp,inputmux, or mux_control_disconnect() on
nxp,inputmux, nxp,trgmux and nxp,xbar.
Check the object type only with K_SYSCALL_OBJ(), leaving the op check
to z_impl. mux_control_set() and mux_state_apply() keep the op form
since set is mandatory.
Not built or run; the mux tests do not cover userspace.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
mux_control_copy_from_user() negated K_SYSCALL_VERIFY_MSG(), which is
already non-zero on failure. The cells-length guard therefore behaved
the opposite way round: every valid length was rejected with -EINVAL
and an oversized len was let through to overflow the k_cells[] stack
buffer. Drop the extra negation.
Not built or run; the mux tests do not cover userspace.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
regulator_get_voltage() is documented optional (-ENOSYS when
unimplemented), and six in-tree drivers leave .get_voltage NULL.
regulator_common_init() still treats -ENOSYS as fatal in its
range-snapping block, which is gated on the range being constrained -
something a binding can do with a default:, not just a board.
espressif,esp32-regulator defaults the range to 500000/3300000 and has
no get_voltage, so every LDO on every ESP32-P4 board fails init and
device_is_ready() is false for all of them.
Skip the range-snapping when the voltage cannot be read back; there is
nothing to snap, which is not an error.
Fixes: #116177
Assisted-by: Claude:claude-opus-5
Signed-off-by: Richard Osterloh <richard.osterloh@gmail.com>
AM13 IOMUX has PINCM[0] at base+0 (no RESERVED0 word), unlike MSPM0/
MSPM33 where PINCM[0] is at base+4. Select the correct offset at
compile time using CONFIG_SOC_SERIES_AM13E.
Signed-off-by: Aman Lachhiramka <a-lachhiramka@ti.com>
The generic dwc_mac driver handles the NuMaker EMAC, and both
in-tree boards now describe the MDIO controller and the PHY that it
needs. Remove the NuMaker Ethernet driver, its Kconfig option and the
phy-addr property that only it used.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
This driver accesses the PHY through the MAC itself and provides no
MDIO driver, so it cannot serve a devicetree with the MDIO node
enabled. Depend on that node being disabled, which leaves such boards
to the dwc_mac driver.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
Add a dwc_mac platform glue driver for the Synopsys DesignWare MAC
integrated in the Nuvoton NuMaker M467 and M55M1 SoCs, where the IP
is named EMAC.
When the devicetree carries no MAC address, the driver derives one
from the chip's unique ID read through hwinfo and spreads it over
the address the way the NuMaker Ethernet driver does, so a board
that relied on the generated address keeps the one it had.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
Report the EMAC module clock rate on the M467 and the M55M1, so
drivers can query it instead of hardcoding a frequency. The EMAC has
no clock source selection and no divider: it runs off HCLK on the
M467 and off HCLK0 on the M55M1.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
A DAT entry written when a device is attached, or during dynamic
address assignment, left the SIR reject bit clear, so an in-band
interrupt raised before any driver call had armed the target was
accepted with no callback registered.
Signed-off-by: Zayne Stites <Zayne.Stites@infineon.com>
Assisted-by: Claude:claude-opus-5
Program both the static address and the dynamic address into the DAT
entry. This way, a device that is only known by its static address
can still be addressed via SETDASA.
Signed-off-by: Zayne Stites <Zayne.Stites@infineon.com>
Assisted-by: Claude:claude-opus-5
get_free_pos() returns -1 when the table is full, but the return
type was unsigned. Consumers checked if the pos was valid with
pos < 0, which is always true, thus a full table wouldn't be
caught.
Signed-off-by: Zayne Stites <Zayne.Stites@infineon.com>
Assisted-by: Claude:claude-opus-5
Fixed the DA source - add_slave_from_daa read the address back out of
the DAT entry the driver had programmed rather than the one the IP
recorded. Databook figure 2-14 puts the assigned DA in DCT LOC4[7:0],
so read it from there and patch the DAT entry to match, otherwise the
descriptor and the target disagree on the address and every transfer
to it is NACKed.
Signed-off-by: Zayne Stites <Zayne.Stites@infineon.com>
Assisted-by: Claude:claude-opus-5
mfd_rv3028_read_regs() and mfd_rv3028_write_regs() log their size_t len
argument with %d, which fails to build with -Werror on targets where
size_t is unsigned long. Use %zu instead.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:opus-5
Restore memory mapping between chunks to limit the time interrupts
are masked to a single chunk instead of the entire operation.
Signed-off-by: Julien Racki <julien.racki-ext@st.com>
When CONFIG_FLASH_STM32_XSPI_XIP_RELOCATE is enabled, ISR handlers
are in flash. Lock IRQs for the entire write/erase operation while
memmap is off to prevent executing code from flash.
Signed-off-by: Julien Racki <julien.racki-ext@st.com>
When the device is already in memory-mapped XIP mode at boot, the full
init sequence is skipped. Set address_width and write_opcode to valid
defaults based on device config so that write and erase operations have
correct parameters without requiring a full re-init.
Signed-off-by: Julien Racki <julien.racki-ext@st.com>
Refactor internal helpers to take dev_data directly instead of struct
device, removing dev->data and dev->config calls that cause flash
accesses while executing from RAM.
Also zero-initialize XSPI_RegularCmdTypeDef to avoid implicit memset
calls from flash.
Signed-off-by: Julien Racki <julien.racki-ext@st.com>
Replace direct LOG_* calls with XSPI_LOG_* conditional macros that are
silenced when CONFIG_FLASH_STM32_XSPI_XIP_RELOCATE is enabled.
This avoids executing log code in Flash while
the memory map is under relocation.
Signed-off-by: Julien Racki <julien.racki-ext@st.com>
Allow abort and restore operations to run write or erase commands when
the code is relocated. In that configuration, the Flash is
memory-mapped by the bootloader and the XSPI driver needs to abort it
to run write or erase commands.
Signed-off-by: Julien Racki <julien.racki-ext@st.com>
This allows to relocate the XSPI driver code to RAM for the STM32N6
and the STM32H7RS series.
Code relocation is done when CONFIG_FLASH_STM32_XSPI_XIP_RELOCATE is
enabled.
Signed-off-by: Julien Racki <julien.racki-ext@st.com>
When no erase type is found, the erase exponent remains zero.
Applying BIT(0) produces an incorrect one-byte erase size and prevents
the fallback to SPI_NOR_SECTOR_SIZE.
Signed-off-by: Julien Racki <julien.racki-ext@st.com>
Move the semaphore init and IRQ config so it is initialized and
configured when running the app in external flash in XIP
Signed-off-by: Julien Racki <julien.racki-ext@st.com>
Replace the hand-maintained list of nine I3C controller compatibles
with a single iteration over the "i3c" device class. New I3C drivers
no longer need to patch this list, and the shell now also covers
out-of-tree I3C controllers.
The class set additionally covers microchip,xec-i3c, which the
hardcoded list had missed. Because class membership only means a node
can be bound as an I3C controller, the controller table and the
generated completion functions reference controllers by devicetree
node name and resolve the device at first use: a controller node
whose driver is not part of the build links fine and yields no
completion entries, where referencing it through DEVICE_DT_GET()
would have failed at link time.
Tested by building all 15 configurations of tests/drivers/build_all/
i3c, and shell_module for qemu_cortex_m3 with a status "okay"
microchip,xec-i3c node and CONFIG_I3C_DW=n, which now links with the
driverless controller absent from completion. Not run on hardware.
Assisted-by: Claude:claude-fable-5
Signed-off-by: Johan Hedberg <johan.hedberg@silabs.com>
Add a hardware-agnostic hwinfo backend that reads the device unique
identifier, and optionally the EUI-64, from NVMEM cells referenced by
a zephyr,hwinfo-nvmem devicetree pseudo-node.
As with the SoC-specific backends, only one device-id backend can be
linked into an image, so a conflicting backend must be disabled when
enabling this one.
Assisted-by: Claude:claude-fable-5
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
off_t may be unsigned long long, so we need to cast to unsigned long before
passing to LOG_DBG for printing with a %lu format.
Signed-off-by: Keith Packard <keithp@keithp.com>
Enable Bluetooth for Series 3 devices by adding new stubs for
symbols from blobs and increasing the link layer stack size.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Rename to SOC_FAMILY_SILABS_S2_XG* to reflect that they are
sub-options for the silabs_s2 SoC family, abiding by the
naming policy for Kconfig options in soc/.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Rename the Kconfig option to SOC_VENDOR_SILABS_HAS_RADIO to
match the guidelines requiring all Kconfig symbols in soc/
to have specific prefixes.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Since this driver can and will also be used for series 1, move it one level
up into the respective if-guard.
Signed-off-by: Michael Zimmermann <michael.zimmermann@sevenlab.de>
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
The DMA driver did not enable error interrupts, so the error
path in the interrupt handler was unreachable. Enable the
error interrupt and dispatch the error callback to the correct
channel if error_callback_dis isn't set.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
