This commit simplifies the flow of the STM32 SPI DMA transfer.
For the "st,stm32h7-spi" compatible, do not set the TSIZE register for a
DMA transfer (to define the size of the transfer). This setting was
leading to several disable/enable of the SPI instance in case multiple
buffers were used in the transaction, and it didn't bring noticeable
performance benefit. At the same time, do not use the SPI FIFO because
it's a hurdle to use without the TSIZE.
Rework the flow of initial operation to better match the procedure
described in the Reference Manuals.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
When waiting for DMA transfer done, wait for both TX and RX, instead of
only one of them.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Disable the EUSART transmitter and receiver immediately upon
completion of a transfer, rather than deferring it to PM Device
Runtime suspend.
The transmitter and receiver are always re-enabled as part of
configuring a new transfer.
This fixes an issue when CONFIG_PM=y where the driver would
not block deep sleep when it was idle, but would wake up with
an inconsistent internal shift register state. Safely shut down
the transmitter and receiver whenever they are not used to
avoid this scenario.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
When CONFIG_LOG_DEFAULT_LEVEL is set to 4 and SPI driver is used,
it will log debug messages idependently of CONFIG_SPI_LOG_LEVEL.
This allows disabling debug logs with the SPI log level config.
Signed-off-by: Eliott Speyser <eliott.speyser@st.com>
The spi_nrfx_spim device driver is used in nothread bootloaders, the
wake implementation waits on a k_sem, patch to poll a volatile bool
variable if CONFIG_MULTITHREADING=n
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
The reworked SPIM driver passes the whole continuous chunk returned by
spi_context_max_continuous_chunk() straight to the common transfer
layer, which rejects anything larger than the controller MAXCNT with
-EINVAL. On SoCs with a small EasyDMA MAXCNT (e.g. nRF91 SPIM with 13
bits, max 8191 bytes) a transfer of 8192 bytes or more fails outright.
The old monolithic driver used to cap the chunk to the MAXCNT limit and
let the event handler walk the rest of the buffer. That behaviour was
lost in the rework, so any caller pushing a buffer larger than MAXCNT
now breaks. One example is the nRF70 firmware patch download, which
copies the patch in 8192 byte chunks and ends up corrupting RPU memory,
leading to a boot signature mismatch.
Restore the cap in transfer_start() so an oversized chunk is split
across multiple EasyDMA transfers, with the remainder handled by the
next call from the event handler once the current chunk completes.
Signed-off-by: Chaitanya Tata <Chaitanya.Tata@nordicsemi.no>
Assisted-by: Cursor:Opus4.8
The DTS binding documents fifo-depth range as 2-256, but the
struct field is uint8_t which silently overflows 256 to 0.
Widen to uint16_t so the full hardware range is representable.
Signed-off-by: Ofir Shemesh <ofirshemesh777@gmail.com>
On SoCs with AXI GDMA, derive the DMA slot from the trigger
peripheral ID base. Flush the tx buffer and invalidate the rx
buffer around the transfer so CPU and DMA see coherent data.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
SPI_SILABS_SIWX91X_GSPI_DMA and SPI_SILABS_SIWX91X_GSPI_DMA_MAX_BLOCKS are
redundant. We can achieve the same by checking if
SPI_SILABS_SIWX91X_GSPI_DMA_MAX_BLOCKS > 0.
Then, rather than pulling the DMA if one device use it, automatically use
the DMA it exist (the user can still disable it by settings DMA_MAX_BLOCKS
== 0).
Thanks to that change, we can remove allthe #ifdef in the SPI driver.
A test in spi_siwx91x_is_dma_enabled_instance() is sufficient to make the
DMA relative functions orphans.
Then, we can enable the dma instances in the board DTS, so the user just
have to set DMA=y to enable DMA in the drivers.
The two errors cases are:
- DMA=y while referenced DMA instance in the DT is disabled. The user get
a compilation error
- DMA=n (or DMA driver is disabled) but the user explicitly set
DMA_MAX_BLOCKS > 0. The user get an error during runtime.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Until now, the SPI driver had to take care about the size of the blocks
sent to the DMA. There were several drawbacks:
- The SPI driver need to know the DMA internal parameter and the SPI
driver has configured for a specific DMA hardware block.
- For large transfer, the user has to allocate a large number of
descriptor in the SPI driver. The user had to know the DMA block size
of set the right parameter and the descriptors were duplicated with the
DMA driver (which store them in the hardware format).
However, our DMA drivers now automatically split the large blocks. So the
SPI driver no longer need to do that.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Update all drivers to use "flags" instead of "sense" when accessing
interrupt properties from device tree. This aligns with the updated
interrupt controller bindings that now consistently use "flags" as
the cell name for the IRQ type field.
Signed-off-by: Amneesh Singh <amneesh@ti.com>
Add a driver for the Generic Quad SPI hardware that is part of the
Xilinx MPSoC. This is mostly commonly used with QSPI flash devices which
are also used for initial image loading, but can also be used with other
SPI devices.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Add sleep retention support for GSPI driver. When peripheral
power down is enabled for light sleep, register data is lost,
so REGDMA backup is needed to mantein peripheral operational.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
spi_mcux_init_common() can fail, propagate the error on TURN_ON
instead of silently ignoring it.
Signed-off-by: Sofian Elmotiem <sofianelmotiem@gmail.com>
Add SPI driver support for Realtek Bee series SoCs,
including RTL87x2G and RTL8752H.
This driver supports:
- Master and Slave operation modes
- Polling, Interrupt, and DMA transfer modes
- Transmit (TX) and Receive (RX) functionality
Signed-off-by: Yuzhuo Liu <yuzhuo_liu@realsil.com.cn>
Validate the SPI bus frequency supplied via spi_config before it is
used to compute the baud-rate clock divider to prevent the following
faults:
- A zero frequency causes an integer division-by-zero when computing
the clock divider, resulting in a hardware fault or an undefined
value being written to the SPI_BAUDR register.
- A frequency exceeding half of the input core clock produces a
divider value less than the minimum of 2 required by the
DesignWare SSI databook (section 6.2.2), overclocking the
peripheral and causing undefined bus behaviour.
Return -EINVAL for a zero frequency and -EINVAL for a frequency
greater than clk_hz / 2, surfacing the error to the caller rather
than silently misconfiguring the hardware.
Assisted-by: Claude:claude-opus-4.6
Signed-off-by: Sudarshan Iyengar <sudarshan.iyengar@alifsemi.com>
When configuring the nRF SPIM, the frequency needs to be limited by
the max frequency of the SPIM, which is specified in the devicetree.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Fix SPI clock frequency being modified during DMA transfers.
Fix regression in DMA configuration structure update.
Signed-off-by: Rick Tsao <rick592@andestech.com>
Fix incorrect behavior for non-8-bit SPI word sizes.
Fix the handling when both TX and RX buffers are NULL.
Signed-off-by: Rick Tsao <rick592@andestech.com>
Replace direct esp_cache_msync() calls in the ESP32 GDMA and
SPI master drivers with the portable sys_cache_data_*() API.
Zephyr's API is a compile-time no-op when CACHE_MANAGEMENT is
disabled, so the same source compiles cleanly on every ESP32
SoC and stays cost-free where there is no writeback cache.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Improve the LPSPI RTIO FIFO path by increasing the fifo
watermark if possible, this reduces IRQ load. Add DMA
support
Signed-off-by: Peter van der Perk <peter.vanderperk@nxp.com>
Since commit 37717b229f ("sys: util: rename Z_MIN Z_MAX Z_CLAMP to min
max and clamp"), <zephyr/sys/util.h> unconditionally defines function-
like macros named `min`, `max`, and `clamp` in the global namespace (in
C mode). util.h gets pulled in transitively by very broad headers,
including the POSIX layer's <pthread.h>, so any third-party C code that
uses these names as ordinary identifiers (e.g. XNNPACK's static `clamp`
helper and its public `clamp` struct field) fails to build as soon as
<pthread.h> is included.
Following the approach used by Linux, move the lowercase `min`, `max`,
`min3`, `max3`, and `clamp` macros (and their helpers) into a new
<zephyr/sys/minmax.h> header that has to be included explicitly by
source files that want them. util.h keeps the uppercase MIN/MAX/CLAMP,
so most code is unaffected; only the (much smaller) set of files that
actually use the lowercase variants needs to pick up the new include.
Fixes#107853.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Move SSDE enable after preload to prevent premature SSL interrupts
Fix DMA fallback to always have ISR variables available
Signed-off-by: Mohamed Azhar <mohamed.azhar@microchip.com>
- Add DMA support for SPI on RZ/N2L, T2M since the previously supported
had not support DMA.
- Add initial support SPI driver for board RZ/T2L.
Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
add reset controller support to the NXP LPSPI driver and
use reset controller APIs if available.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
The current flow sets CS before the SPIM peripheral actually drives
the bus. This can cause SCK to be in the incorrect initial state
dictated by CPOL. New flow enables SPIM after it has been configured,
before CS is set, and disabled is after CS is cleared, thus the bus
is driven by SPIM during the entire transfer.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
The gpiote_nrfx.h header is needed for a macro used when handling
NRF52_ANOMALY_58
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
The spi context tx_buf, rx_buf, tx_count and rx_count members are
modified during the transfer. These members are currently accessed
in spi_context_wait_for_completion when calculating the expected
timeout, which happens concurrently with the transfer being in
progress. This can lead to concurrency issues as the mentioned
members may be modified independently as they are being accessed by
the thread setting up the wait.
Remove this potential conflict by calculating the number of bytes
as part of spi_context_buffers_setup and store it, before the
transfer is started. Then used the stored value when setting up
the wait.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Ensure SPI pins are correctly configured before setting CS, by
configuring the SPIM before setting CS.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
The common pm_suspend implementation for the spi_nrfx_spim drivers
unconditionally sets the sleep state. The sleep state may not be
available, in which case we should not try to set it. Check
CONFIG_PINCTRL_KEEP_SLEEP_STATE and only try to set sleep state if
true.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
The header at drivers/spi/rtio.h was moved to a relative path, and
renamed "spi_rtio.h".
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
The SAM0 SPI driver previously supported DMA only for asynchronous
operations, which required higher-level drivers needing blocking DMA
transfers to implement workarounds. This patch extends DMA support
to the synchronous transfer path, enabling efficient blocking SPI
transactions without driver-specific hacks.
With this change, both synchronous and asynchronous SPI operations
can leverage DMA for improved performance and reduced CPU overhead.
Signed-off-by: Ramya T <ramya.t@microchip.com>
Signed-off-by: Parthiban Veerasooran <parthiban.veerasooran@microchip.com>
Move to the new MXC_SPI_GetAndClearFlags API to avoid a race condition
where flags not handled in the ISR would be cleared and missed as a result.
This fix removes the need for the previous partial workaround that simply
masked the issue in most scenario.
Signed-off-by: Pete Johanson <pete.johanson@analog.com>
When DMA is enabled, but there are no DMA channels assigned to the SPI
peripheral, properly fall back to setting up the dummy bytes for SPI RTIO
operations.
Signed-off-by: Pete Johanson <pete.johanson@analog.com>
Add support for the SPI module on TI’s MSPM0 MCUs.
The driver supports master mode transfers with configurable
frame size (4–16 bits), clock polarity/phase, bit order.
Signed-off-by: Santhosh Charles <santhosh@linumiz.com>
Signed-off-by: Jackson Farley <j-farley@ti.com>
Co-authored-by: Hans Binderup <habi@bang-olufsen.dk>
Enable Active-High polarity for SPI chip-select in Xilinx AXI QSPI Driver.
Required e.g. for SD-Card support.
Signed-off-by: Martin Anschütz <martin.anschuetz@vert-tec.io>
Fixed CTRLA register write bugs in spi g1 driver
Updated the transfer function for handling dma mode
Fixes#106580
Signed-off-by: Mohamed Azhar <mohamed.azhar@microchip.com>
Refactor the nrf_spim device driver to share the common code between
the nrf_spim_rtio implementation.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Move the private spi_rtio.h header from the public path
include/zephyr/drivers/spi/rtio.h
the the private path
drivers/spi/spi_rtio.h
and update drivers to include it using a relative path.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
