Use controller/peripheral terminology in the Renesas RA SPI driver,
following coding guideline rule A.2: rename the driver-internal
transceive helpers, switch to the renamed core symbols and the
CONFIG_SPI_PERIPHERAL guard.
The SPI_MODE_MASTER/SPI_MODE_SLAVE operating mode constants come from
the Renesas FSP HAL and keep their names.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Use controller/peripheral terminology in the Microchip SERCOM G1 SPI
driver, following coding guideline rule A.2: rename the
driver-internal peripheral/controller helper functions and ISRs,
switch to the renamed core symbols and the CONFIG_SPI_PERIPHERAL
guard (including the SPI_MCHP_INTER_CHARACTER_SPACE default), and
update comments and log messages.
The SERCOM_SPI_CTRLA_MODE_SPI_MASTER/SLAVE register field macros come
from the Microchip device family pack headers and keep their names.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Use controller/peripheral terminology in the Realtek Ameba SPI
driver, following coding guideline rule A.2: rename
spi_ameba_is_slave() to spi_ameba_is_peripheral(), switch to the
renamed core symbols and the CONFIG_SPI_PERIPHERAL guard, and update
comments and log messages.
The SSI_MASTER/SSI_SLAVE role constants come from the Realtek Ameba
HAL and keep their names; the debug messages that print which HAL
role constant is selected keep referring to them verbatim.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Use controller/peripheral terminology in the NXP S32 SPI driver,
following coding guideline rule A.2:
- Add a "peripheral" boolean devicetree property; the old "slave"
property is still accepted, marked as deprecated in the binding,
and used as a fallback when the new one is not set.
- Rename driver-internal identifiers, guards, comments and log
messages accordingly.
The SPI_MCR_MSTR register field macros and the SlaveMode member of
the SPI configuration structure come from the NXP S32 RTD HAL and
keep their names.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Use controller/peripheral terminology in the Realtek Bee SPI driver,
following coding guideline rule A.2:
- Add an is-peripheral devicetree property; the old is-slave property
is still accepted, marked as deprecated in the binding, and used as
a fallback when the new one is not set.
- Rename driver-internal identifiers, guards, comments and log
messages accordingly.
The SPI0_SLAVE_TX/RX_FIFO_SIZE and SPI_Mode_Slave identifiers come
from the Realtek Bee SDK/HAL and keep their names, and the spi0_slave
devicetree node label keeps its name as it designates the dedicated
SPI0 slave-mode hardware instance of the SoC.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Use controller/peripheral terminology in the Cadence SPI driver,
following coding guideline rule A.2: switch to the renamed core
symbols and the CONFIG_SPI_PERIPHERAL guard, and update comments and
log messages.
The SPI_SLAVE_IDLE_COUNT register offset macro keeps its name as it
mirrors the "Slave_Idle_count" register of the Cadence SPI controller
datasheet.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Use controller/peripheral terminology in the DesignWare SPI driver,
following coding guideline rule A.2: rename spi_dw_is_slave() to
spi_dw_is_peripheral(), switch to the CONFIG_SPI_PERIPHERAL guard and
the renamed core symbols, and update comments and log messages.
The DW_SPI_CTRLR0_SLV_OE register bit macro keeps its name as it
mirrors the "Slave Output Enable" field of the Synopsys DesignWare
SSI databook.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Use SDO/SDI and controller/peripheral terminology in the Raspberry Pi
Pico PIO SPI driver, following coding guideline rule A.2:
- Rename the sdo-gpios/sdi-gpios devicetree properties from
mosi-gpios/miso-gpios. The old property names are still accepted,
marked as deprecated in the binding, and used as a fallback by the
driver when the new ones are not set.
- Rename driver-internal identifiers and log messages accordingly.
- Migrate all in-tree boards, samples and test overlays to the new
property names.
The pico-sdk PIO helper APIs used by the driver keep their vendor
names.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Use SDO/SDI and controller/peripheral terminology in the SPI bitbang
driver, following coding guideline rule A.2:
- Rename the sdo-gpios/sdi-gpios devicetree properties from
mosi-gpios/miso-gpios. The old property names are still accepted,
marked as deprecated in the binding, and used as a fallback by the
driver when the new ones are not set.
- Rename driver-internal identifiers and log messages accordingly.
- Migrate all in-tree boards and sample overlays to the new property
names.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Use controller/peripheral terminology in the SPI driver context
helpers, following coding guideline rule A.2:
- Rename spi_context_is_slave() to spi_context_is_peripheral(),
keeping the old name as a compatibility wrapper for out-of-tree
drivers.
- Rename the spi_ctx_runtime_op_mode enumerators to
SPI_CTX_RUNTIME_OP_MODE_CONTROLLER/PERIPHERAL, keeping the old
names as compatibility aliases.
- Guard peripheral-mode code with CONFIG_SPI_PERIPHERAL. The
deprecated CONFIG_SPI_SLAVE option selects SPI_PERIPHERAL, so
drivers that still test CONFIG_SPI_SLAVE keep working unchanged.
- Update comments accordingly.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Rename the SPI_SLAVE Kconfig option to SPI_PERIPHERAL, following
coding guideline rule A.2. The old option is kept as a compatibility
shim that selects SPI_PERIPHERAL, so existing configurations keep
working and both CONFIG macros are defined whenever either option is
enabled. This lets drivers migrate their guards independently.
The shim will additionally select DEPRECATED once all in-tree users
have been migrated.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Two-line copyright notices were wrapped in the SPDX "<text>...</text>"
construct, which is only valid in an SPDX document, not a file header.
The REUSE tool then folds the literal "<text>" into the holder name
and drops the second line from the SBOM.
Remove the markers and tag the continuation line. Holder, year and
e-mail are left unchanged; only the syntax is fixed.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
The RTIO path updated the transfer command with read-modify-writes of
TCR while the transmit FIFO held queued entries: clearing CONT and
CONTC when the last data word enters the FIFO, in the DMA TX complete
callback, and in the end-of-transfer touch. TCR reads are not reliable
in that state. The reference manual advises reading TCR only with an
empty transmit FIFO or reading it twice and comparing, and ERR050606
adds that a polled TCR read can return a stale value. A stale or torn
readback written back is queued as a command word and silently alters
the frame for the remaining words with no error flag raised.
On a 17 byte half duplex probe read of an AFBR-S50 on MCXN947 LPSPI
with its 8 word RX FIFO the transfer completes reporting success while
the payload arrives displaced: the device's 0x00..0x10 test ramp
returns ten 0x00 bytes with the values 0x01..0x07 landing at offsets
10..16. Reads at or below the FIFO size are unaffected.
Compose the transfer command once at start of transfer, while the
transmit FIFO is empty and the read is defined, cache it per instance,
and write the cached value with CONT and CONTC cleared at every later
command write instead of reading TCR back.
For transmit only transfers on the interrupt path, mask RX in the
cached command before the first FIFO fill rather than after it, so no
unread words collect in the RX FIFO behind the queued data. The DMA
path keeps RX unmasked since it drains every received word and its
completion is signaled by the RX channel. Skip the RX drain pass when
the receive data flag is clear, keeping the receive interrupt armed,
so transmit and completion interrupts no longer run empty drain loops.
The watermark scheme, FIFO tuning, and DMA support are unchanged.
Signed-off-by: Benjamin Perseghetti <bperseghetti@rudislabs.com>
spi_config() stored the config in the context before calling
am_hal_ios_configure(), so a failed HAL configure left the context
marked as configured. The next transceive then passed the
spi_context_configured() check and ran on unconfigured hardware, and
the raw HAL status leaked through the SPI API as a positive value.
Only publish the new config once the HAL accepts it and map a configure
failure to -EIO.
Fixes#116324
Signed-off-by: Richard Wheatley <richard.wheatley@ambiq.com>
spi_ambiq_transceive() returned early when spi_config() failed, skipping
the runtime PM put and leaking the usage count taken by the get; the
device could then never runtime-suspend again. It also overwrote the
transfer status with the return of pm_device_runtime_put_async(), hiding
transfer errors from the caller, and continued into the HAL after a
failed get.
Route the config-failure path through the common exit, keep the put
status in its own variable, and bail out when the get fails.
Fixes#116324
Signed-off-by: Richard Wheatley <richard.wheatley@ambiq.com>
spi_esp32_get_line_mode() takes the SPI operation as a uint16_t, but the
line-mode bits SPI_LINES_DUAL/QUAD/OCTAL live at bit 16 and above of the
spi_operation_t type, which is widened to uint32_t when
CONFIG_SPI_EXTENDED_MODES is enabled. Passing the full operation into the
uint16_t parameter truncates those bits, so operation & SPI_LINES_MASK is
always 0 and the function always reports single-line mode. Any request for
dual, quad or octal lines is silently downgraded to single-line, driving
only the D0 data line.
Widen the parameter to uint32_t so the line-mode bits survive, matching
how every other SPI driver reads the operation. Verified on an
ESP32-S3-Touch-AMOLED-1.8 QSPI panel, where quad transfers only produced
correct colors with this fix.
Signed-off-by: Dylan Rowe <dylanthomasrowe@gmail.com>
The AHB GDMA path passed dma-host, the SPI host index, as
the DMA peripheral trigger. That happens to match on SoCs
where the SPI2 trigger is zero, but on esp32c5 and esp32c61
the SPI2 trigger is 1, so RX and TX were connected to the
wrong peripheral and no data was transferred. Derive the
trigger from the SPI2 base as the AXI path already does.
spi_loopback DMA mode passes on esp32c5 and esp32c61.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The divider was left at its reset value, so with a pll source
the peripheral input exceeds its limit and the first clocked bit
is corrupted on esp32p4. Compute an even divider that respects
the limit and program it when the device is configured.
Assisted-by: Claude:opus-4-8
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The interrupt path released the context without waiting, so a
synchronous caller could read the rx buffer while the isr was
still filling it. Wait for completion before releasing.
Assisted-by: Claude:opus-4-8
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
__ASSERT_MSG_INFO() is an internal helper of <zephyr/sys/__assert.h>, not a
public API. A handful of drivers and inline helpers called it directly to
emit a message without an accompanying assertion.
Replace those direct uses with the appropriate mechanism: LOG_ERR() for the
recoverable runtime error paths in the display, RTC, SPI and CRC code, and
__ASSERT(false, ...) for the out-of-range programming errors in the ADC and
DAC inline helpers.
Signed-off-by: Måns Ansgariusson <mansgariusson@gmail.com>
Add macros that treat the QMSPI Mode register's three clock bits (idle
state, transmit phase, sample phase) as a single SPI-mode field to
simplify driver code.
The Control and Descriptor registers' TX and RX DMA-enable fields use
the same value encoding, so share one direction-agnostic set of value
macros (DMA_DIS; LDMA_CH0..2 for local-DMA channels; DMAC_U1B/U2B/U4B
for central-DMA access size) while keeping separate TX/RX get/set
macros. This also corrects the 4-byte TX value, which was 4 (out of
range for the 2-bit field) and is now 3, matching RX.
Update the existing spi_xec_qmspi_ldma.c consumer to the new LDMA_CH0
names; identical field values, so no functional change.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
The driver programmed its devicetree-assigned RX/TX DMA channels with
dma_config() without ever reserving them in the DMA controller's
allocation bitmap. A dma_request_channel(dev, NULL) caller on the same
controller (for example a memory-to-memory transfer) could therefore be
handed a channel already owned by SPI, corrupting both transfers.
Reserve each channel at init through dma_request_channel() with a
BIT(channel) filter. This forces exactly the devicetree channel, marks it
allocated in the shared bitmap so it can no longer be handed out, and
fails init if the channel is already in use.
Co-authored-by: Claude Opus 4.8 <noreply@anthropic.com>
Signed-off-by: Yuzhuo Liu <yuzhuo_liu@realsil.com.cn>
Valid slave selects are 0 to SPI_CHIP_SELECT_COUNT - 1, but the guard
used '>', letting slave 4 through to
Cy_SCB_SPI_SetActiveSlaveSelect(). Use '>=' and reword the error
message to match.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Update EUSART driver to use new HAL library that supports both
Series 2 and Series 3 SoCs.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Assert CS with zero-byte transaction since BLE HCI SPI(hci_spi_st.c) driver
relies on zero-byte transaction for asserting CS.
It fixes the SPI communication for radio co-processors (RCP).
Signed-off-by: Ali Hozhabri <ali.hozhabri@st.com>
Updated to complete peripheral transfer on TXC
Fixed dummysize calculation for multi-buffer transfers
Signed-off-by: Mohamed Azhar <mohamed.azhar@microchip.com>
The RTS5817's SPI is based on snps,designware-spi, but it's not
entirely the same, so DW spi drivers cannot be used directly.
The rts5817 spi driver uses some DW spi code:
1. pin_ctrl is handled in the spi_dw.c code initialization.
2. Several APIs defined in spi_dw.h is used by spi_rts5817.c.
Signed-off-by: Darcy Lu <darcy_lu@realsil.com.cn>
This commit adds an API for writing to the RX_SAMPLE_DLY register,
and also adds the `__maybe_unused` attribute to APIs such as
aux_reg_* and reg_*, so that these APIs can be used in other drivers
that based on snps,designware-spi
Signed-off-by: Darcy Lu <darcy_lu@realsil.com.cn>
Remove the unintialized variable from a DBG print to prevent compiler
warnings when the log level is set to debug.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
This change corrects sspi clock query for it8xxx2 register
v2. Additionally, the spi clock must be turned on when
setting ssck equal to sspi_clock.
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
The property was both `boolean` and `required: true` so it was always
present on nodes with the compatible (i.e., STM32WL5 "SUBGHZSPI" node).
The SPI driver serialized this property into field `use_subghzspi_nss`,
but it really acted as `is_subghzspi` instead... which does not require
a specific property: the SUBGHZSPI node can be identified by its special
compatible `st,stm32-spi-subghz` alone!
Drop the `use-subghz-nss` property from the binding since it is useless,
and update the STM32WL SoC DTSI accordingly. In the STM32 SPI driver,
rename the `use_subghzspi_nss` field to `is_subghzspi` and initialize it
to true iff an SPI node has the special compatible. While at it, inline
function spi_stm32_is_subghzspi() into its only caller and add a comment
explaining why the check is needed to slightly simplify the driver.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
The driver stored the devicetree register address in cfg->base and used
it as a virtual address without ever mapping it. That only works where
the boot page tables already cover the peripheral. On the ZynqMP and
Versal NET APUs they do not, so the SPI_CONF write at the top of
spi_cdns_init() faults.
Convert to the DEVICE_MMIO helpers, which map the region in init() and
drop the assumption that the virtual address equals the physical one.
Also fixes a truncation: base was uint32_t, while DT_INST_REG_ADDR() is
pointer-width.
No functional change on non-MMU targets, where DEVICE_MMIO_IS_IN_RAM is
unset: building drivers.spi.build.spi_cdns for qemu_cortex_m3 before and
after gives byte-for-byte identical disassembly.
Signed-off-by: Iustin Stolniceanu <stolniceanuiustin@gmail.com>
Use %zu instead of %d in LOG_DBG for size_t arguments (fill_len,
offset) to fix -Wformat build warnings.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
- spi_context_lock: move the ISR assert from function entry to guard the
actual blocking call (inside !already_locked), so the legitimate
SPI_LOCK_ON fast path is not falsely caught.
- spi_context.h comment: clarify that calling from ISR is legal when the
lock is already held via SPI_LOCK_ON.
- spi.h: point to the RTIO submit path as the correct way to chain
asynchronous transactions, per @teburd and @npitre.
Suggested-by: Nicolas Pitre <npitre@baylibre.com>
Signed-off-by: Tibor Kiss <kiss.tibor@gmail.com>
Switch the Cadence SPI driver to use the DEVICE_MMIO API instead
of directly accessing the physical base address from the devicetree.
This is required to support platforms with an active MMU (such as the
Cortex-A9 on Zynq 7000), where accessing unmapped physical addresses
causes MMU translation faults.
Closes#113693
Signed-off-by: Simon Maurer <mail@maurer.systems>
The 16-bit branch of spi_gd32_frame_exchange() read the TX buffer
through a uint8_t pointer, copied from the 8-bit branch, so the high
byte of every 16-bit frame was transmitted as zero. Read a full
16-bit word, matching the RX side.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Some SPI devices need the CS pin to be deasserted between multiple
transceive calls (e.g. the Microchip LAN8651). The MCSPI driver didn't do
this until now and kept the CS pin asserted for hardware controlled CS
pins, except if the channel changed.
This has been changed and additionally during init the GPIO pins are now
also being initialized.
Signed-off-by: Mika Braunschweig <mika.braunschweig@siemens.com>
Header file include/zephyr/sys_clock.h is deprecated and will be removed
someday. Update the whole file tree to include zephyr/sys/clock.h
straight instead of zephyr/sys_clock.h.
This change was made running the sed shell command below:
$ sed -i 's/zephyr\/sys_clock\.h/zephyr\/sys\/clock\.h/' \
`grep -rsl "zephyr/sys_clock\.h" drivers/`
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
lpspi_end_xfer() only clears TCR CONT/CONTC when SPI_HOLD_ON_CS is
absent from the transfer's config, so that consecutive
spi_transceive() calls within a HOLD_ON_CS transaction keep native
(non-GPIO) CS asserted between transfers, as intended.
However, once the caller finishes the whole transaction and calls
spi_release(), those bits were never cleared, leaving native CS
asserted indefinitely - spi_context_unlock_unconditionally() already
force-releases GPIO-based CS via _spi_context_cs_control(ctx, false,
true), but has no way to know about the LPSPI-specific TCR bits for
native CS.
Clear TCR CONT/CONTC directly in spi_lpspi_release() so that
spi_release() actually deasserts native CS as its API contract
implies, matching the existing GPIO CS behavior.
Confirmed on real hardware (FRDM-MCXN947, LPSPI1 native PCS0): CS
previously stayed low indefinitely after the first HOLD_ON_CS
transaction (as used by the Arduino SPI API, which always sets
SPI_HOLD_ON_CS to support multiple transfer() calls per transaction);
with this fix CS correctly returns high after each endTransaction().
Signed-off-by: Tedd OKANO <okano.akifumi@gmail.com>
Updated spi_xec_qmspi_ldma driver with low power support.
Add a pm_action handler that clears MODE.ACTV and applies the
pinctrl sleep state on suspend, and reverses both on resume.
Hold a PM_STATE_SUSPEND_TO_IDLE policy lock for the duration of
each transfer (sync and async) so suspend cannot enter mid-
transaction.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
Let's avoid a build warning/error in the spim interrupt handler mapping,
by being explicit about passing to it as parameter the address of
`nrfx_spim_t spim` data instead of knowing implicitly that it is the first
element of `struct driver_data`.
This avoid the following build warning/error:
nfx_spim.h:472:42: note: expected 'nrfx_spim_t *' but argument is of
type 'struct driver_data *'
Issue introduced in:
6f2829ea0c
Can be reproduced building
tests/arch/arm/arm_irq_vector_table for thingy53/nrf5340/cpuapp
with CONFIG_SPI_RTIO=y
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Let's avoid a build warning/error in the spim interrupt handler mapping,
by being explicit about passing to it as parameter the address of
`nrfx_spim_t spim` data instead of knowing implicitly that it is the first
element of `struct driver_data`.
This avoid the following build warning/error:
nrfx_spim.h:472:42: note: expected 'nrfx_spim_t *' but argument is of
type 'struct driver_data *'
Issue introduced in:
e4d61fc472
Can be reproduced building
tests/arch/arm/arm_irq_vector_table for thingy53/nrf5340/cpuapp
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
The last TX word must be written to FIFOWR as a full 32-bit write to
properly set the EOT (end-of-transfer) control bit at bit 20. Commit
7cb3fca changed the DMA block_size for the last word from
sizeof(uint32_t) to data->word_size_bytes, which meant only the lower
data bytes were transferred, missing the EOT flag entirely.
The issue #107484 mentions that this will cause the last
transfer to be incorrect width, but deep down in the NXP dma driver
there is a fix for this. See dma_mcux_lpc.c (line 262-273).
Fixes: #107484
Signed-off-by: Lars Jeppesen <lje@foss.dk>
The async completion path handed the driver data pointer to
spi_smartbond_pm_policy_state_lock_put(), which expects the device and
forwards it to pm_device_runtime_put(). Pass dev, as every other call
site does.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
The driver reads the rate of the configured clock source and
calculates the timing divider against it, but never programs
the hardware mux that selects that source. The mux keeps its
reset value, so the peripheral runs from XTAL while the
divider assumes a PLL rate.
On esp32p4 the default source is the 480 MHz SPLL and the
reset value selects the 40 MHz XTAL, making every transfer 12
times slower than requested: a 1 MHz request measures 83 kHz.
Program the mux at init so it matches the rate the divider is
calculated from.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
