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spi_nxp_lpspi: Refactor validation args to func

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Minor refactor to make a separate function to validate configuration
arguments.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
This commit is contained in:
Declan Snyder 2025-02-18 10:32:46 -06:00 • committed by Benjamin Cabé
commit ef60f88162
1 changed files with 35 additions and 23 deletions
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58
drivers/spi/spi_nxp_lpspi/spi_nxp_lpspi_common.c
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@ -69,29 +69,14 @@ int spi_mcux_release(const struct device *dev, const struct spi_config *spi_cfg)
return 0;
}
int spi_mcux_configure(const struct device *dev, const struct spi_config *spi_cfg)
static inline int lpspi_validate_xfer_args(const struct spi_config *spi_cfg)
{
const struct spi_mcux_config *config = dev->config;
struct spi_mcux_data *data = dev->data;
struct spi_context *ctx = &data->ctx;
LPSPI_Type *base = (LPSPI_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
uint32_t word_size = SPI_WORD_SIZE_GET(spi_cfg->operation);
bool configured = ctx->config != NULL;
lpspi_master_config_t master_config;
uint32_t clock_freq;
int ret;
/* fast path to avoid reconfigure */
/* TODO: S32K3 errata ERR050456 requiring module reset before every transfer,
* investigate alternative workaround so we don't have this latency for S32.
*/
if (spi_context_configured(ctx, spi_cfg) && !IS_ENABLED(CONFIG_SOC_FAMILY_NXP_S32)) {
return 0;
}
uint32_t pcs = spi_cfg->slave;
if (spi_cfg->operation & SPI_HALF_DUPLEX) {
/* the IP DOES support half duplex, need to implement driver support */
LOG_ERR("Half-duplex not supported");
LOG_WRN("Half-duplex not supported");
return -ENOTSUP;
}
@ -103,22 +88,49 @@ int spi_mcux_configure(const struct device *dev, const struct spi_config *spi_cf
* Minimum hardware word size is 2. Since this driver is intended to work
* for 32 bit platforms, and 64 bits is max size, then only 33 and 1 are invalid.
*/
LOG_ERR("Word size %d not allowed", word_size);
LOG_WRN("Word size %d not allowed", word_size);
return -EINVAL;
}
if (spi_cfg->slave > (LPSPI_CHIP_SELECT_COUNT - 1)) {
LOG_ERR("Peripheral %d select exceeds max %d", spi_cfg->slave,
LPSPI_CHIP_SELECT_COUNT - 1);
if (pcs > LPSPI_CHIP_SELECT_COUNT - 1) {
LOG_WRN("Peripheral %d select exceeds max %d", pcs, LPSPI_CHIP_SELECT_COUNT - 1);
return -EINVAL;
}
return 0;
}
int spi_mcux_configure(const struct device *dev, const struct spi_config *spi_cfg)
{
const struct spi_mcux_config *config = dev->config;
struct spi_mcux_data *data = dev->data;
struct spi_context *ctx = &data->ctx;
bool already_configured = spi_context_configured(ctx, spi_cfg);
LPSPI_Type *base = (LPSPI_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
uint32_t word_size = SPI_WORD_SIZE_GET(spi_cfg->operation);
lpspi_master_config_t master_config;
uint32_t clock_freq;
int ret;
/* fast path to avoid reconfigure */
/* TODO: S32K3 errata ERR050456 requiring module reset before every transfer,
* investigate alternative workaround so we don't have this latency for S32.
*/
if (already_configured && !IS_ENABLED(CONFIG_SOC_FAMILY_NXP_S32)) {
return 0;
}
ret = lpspi_validate_xfer_args(spi_cfg);
if (ret) {
return ret;
}
ret = clock_control_get_rate(config->clock_dev, config->clock_subsys, &clock_freq);
if (ret) {
return ret;
}
if (configured) {
if (already_configured) {
/* Setting the baud rate in LPSPI_MasterInit requires module to be disabled. Only
* disable if already configured, otherwise the clock is not enabled and the
* CR register cannot be written.