The clock-frequency value in dtsi can be used to change
the bus frequency for rts5912 driver and
it support in the range between 15000 to 50000000.
Signed-off-by: Lin Yu-Cheng <lin_yu_cheng@realtek.com>
Currently, clk_div_factor is force to 1 if user request more than 110MHz.
However, in this case, gspi_siwx91x_get_divider() will never return 2 or
more, unless the input clock is >= 220MHz. The si91x is not designed for
such high clock frequency. So, this case has never been tested.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
In gspi_siwx91x_config(), clk_div_factor can't be < 1. Therefore, we can
remove the dead code.
This code has been tested with tests/drivers/spi/spi_loopback, with a PLL
clock configured to 160MHz and a bus clock to 80MHz with success. I have
not found the case where change in GSPI_CLK_CONFIG are required.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Until now, GSPI_DATA_SAMPLE_EDGE was enabled as soon as the user requested
> 40Mhz (even if the actual frequency was in fact 40Mhz). However, at 40MHz
and at 80MHz, use of GSPI_DATA_SAMPLE_EDGE generated read errors on the
last bit of the transaction:
Buffer contents are different:
[...],0xaa,0xaa,0xaa,0xaa,
vs:
[...],0xaa,0xaa,0xaa,0xab,
I have not found any case where GSPI_DATA_SAMPLE_EDGE is useful, so this
patch just remove this parameter.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
In functions requiring to lock/release resources, it is less error prone to
have only one exit point and user goto to manage errors.
The behavior of the new code is exactly identical to the initial one.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
The guard against rx_bufs == NULL was originally added to prevent a
DMA misconfiguration observed when no RX buffer was provided.
The issue can no longer be reproduced, and the check was incomplete
since it did not cover rx_bufs->buffers == NULL or rx_bufs->count == 0,
which lead to the same effective condition.
Removing the check simplifies the driver and avoids blocking valid
TX-only transfers.
Signed-off-by: Alexandre Rey <alx.rey@icloud.com>
If spi_sam_configure() is called with more than 4 chip selects the
current check fails even if the pins are used as gpios. The variable
spi_csr_idx already has the correct index to be checked and must be
used in this check.
Signed-off-by: Munawar Ali <ali@sofiha.de>
Signed-off-by: Axel Utech <utech@sofiha.de>
Allows "egis_et171_spi" to use basic clock information
provided by the clock driver to calculate the runtime
SPI frequency.
Signed-off-by: Jacky Lee <jacky.lee@egistec.com>
The Cadence SPI controller has a hardware issue (Xilinx AR#65885
contains more details) where the RX_NOT_EMPTY (RNE) status bit
reports inconsistent state. This causes the driver to unreliably
detect when RX FIFO contains valid data, leading to transfer
failures and test hangs.
Signed-off-by: Srikanth Boyapally <srikanth.boyapally@amd.com>
Extend the number of SPI data sizes supported for series that allow it.
The driver uses the new property st,stm32-data-width to create a table
with all compatible data widths and to check if the SPI instance
support the required width (some instances may have a limited set
of widths compared to others on the same SoC).
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Inverts ll_func_spi_dma_busy logic so that the function returns true if
the SPI DMA is busy (as suggested by the name) instead of the other way
around.
Also completes the check for H7-compatible with the LL_SPI_IsActiveFlag_EOT
function when transfer size is set.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Guard callback registration with CONFIG_SPI_ASYNC to avoid
build error for blocking SPI transfers using DMA
Signed-off-by: Sai Santhosh Malae <Santhosh.Malae@silabs.com>
Swap the write and read data paths within the GSPI controller to ensure
correct data is seen on the SPI lines during 16-bit transfers.
Signed-off-by: Sai Santhosh Malae <Santhosh.Malae@silabs.com>
Updated mosi_overrun alignment from 4 bytes to 32 bytes to
ensure compatibility with the GPDMA driver. This prevents
alignment-related errors during DMA transfers.
Signed-off-by: Sai Santhosh Malae <Santhosh.Malae@silabs.com>
Enable higher SPI burst sizes when using GPDMA to improve throughput.
Bursts are only enabled when both TX and RX channels use GPDMA and
the SPI clock frequency is at least 10 MHz, as DMA flow control is
unreliable at lower SPI rates.
Signed-off-by: Sai Santhosh Malae <Santhosh.Malae@silabs.com>
Add gspi_siwx91x_pick_lower_freq() to select the nearest lower
supported GSPI clock frequency based on the requested value.
The GSPI clock can operate only at discrete frequencies such as
80 MHz, 40 MHz, 26.6 MHz, 20 MHz, and so on (80 MHz divided by
integer factors). If the requested frequency does not match one
of these valid steps, it is rounded down to the nearest lower
supported frequency.
The driver now logs both the requested and the actual programmed
frequency along with the divider value, helping users verify the
effective SPI clock configuration.
Signed-off-by: Sai Santhosh Malae <Santhosh.Malae@silabs.com>
Some STM32 SPI have the ability to bypass the baudrate prescaler, which is
equivalent to having a prescaler of 1.
Adds this new value in the prescaler calculation if available.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
The `ll` part of driver's file name indicates that the implementation uses
the STM32Cube Low Level ("LL") library, which is not interesting because
there is only *one* STM32 driver implementation anyways. Addtionnally, the
presence of `ll` among STM32 drivers is not consistent.
Get rid of it for this class's driver to match most other STM32 drivers.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
The burst length unit is bytes, not number of transfers. This had not been
an issue since the DMA driver historically ignored the values, but has now
become one since they are used and (most importantly for us) validated.
Fixes broken 16-bit on STM32N6 series.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Enable clock control by default for siwx91x SoCs. Moreover, most
drivers for siwx91x soc depend on clock control, but didn't declare
it.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
Added calls to pm_device_runtime_put() to ensure proper device runtime
management when configuration or DMA transceive operations fail.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
Most drivers for Series 2 depend on clock control, but didn't
declare it. Enable clock control by default for Series 2 SoCs.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
New nrfx release contains major rework of nrfx drivers
instantiation making it easier to integrate with dts nodes.
Now, nrfx driver instances can no longer be `const`
because they contain driver runtime state.
Additionally, all nrfx drivers return `errno` error codes
instead of deprecated `nrfx_err_t`.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
Removing references to infineon,cat1-spi-pdl from the device tree files.
Updates the driver bindings and driver file to look at the
infineon,cat1-spi binding and uses a Kconfig option to select Legacy HAL
implementation instead.
See https://github.com/zephyrproject-rtos/zephyr/pull/98035 for context.
Signed-off-by: John Batch <john.batch@infineon.com>
This driver had a lot of regressions introduced by commits that were
clearly mixing up what values had units of bytes and what values had
units of words. Fix the issues in the DMA path of the driver.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The asserts are hard to debug and unrecoverable, they just say kernel
panicked but difficult to realize where and why, it's better to return
an error and log message clearly from spi driver.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
It is not illegal to provide an RX len with no buffer.
It just means the controller should clock out that many
words but not store them in memory. So remove the assert
and just avoid null dereference.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Refactor this function to return an error code, instead of assert.
Put the data into a pointed argument instead.
Refactor other functions to make sure to
propogate this error all the way up the call stack.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Fixes an issue with an unused function being defined if
CONFIG_DEVICE_DEINIT_SUPPORT was disabled
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Release the PM constraint at the end of the context in which it was
requested (`transceive`), instead of in a semi-related function
(`finalize_spi_transaction`) which is also called by other API functions
(`spi_release`). Asynchronous usage is released in the transaction
complete callback.
Signed-off-by: Jordan Yates <jordan@embeint.com>
When SPI spec is reconfigured, avoid reallocating another sm and properly
free the loaded sm programs before attempting to load new programs.
Fix#94416.
Signed-off-by: Terry Geng <terry@terriex.com>
Enabled intel LPSS DMA interface using dw common to support
usage of internal DMA in LPSS SPI to transfer and
receive data.
Signed-off-by: Bindu S <bindu.s@intel.com>
This patch adds a check for the EOT (End Of Transfer) flag
inside the polling loop in spi_stm32_half_duplex_switch_to_receive().
If EOT is set, the transfer is already complete and the loop
is exited, preventing the lockup.
Signed-off-by: Khaoula Bidani <khaoula.bidani-ext@st.com>
Signed-off-by: Julien Racki <julien.racki-ext@st.com>
The current implementation checking for the validity of the spi slave
number is wrong. First of all, there is an off by one error where it
allows SPI_CHIP_SELECT_COUNT value as a valid slave, when really it
should be that value minus one. Secondly, it doesn't take into account
the fact that having software controlled GPIO CS can technically have
any number of slaves on the bus. So fix by finding the max of these two
values and fixing the off by one mistake. Also, for RW612, only one HW
native CS is available due to SOC pinmux limitations.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The version register is not accessible through aux-reg interface,
So skip it entirely on platforms with aux-reg device tree property.
Signed-off-by: Mohamed Moawad <moawad@synopsys.com>
Because of limitation of gpdma, DMA Rx won't run if user doesn't specify
destination buffer.
Thus, the DMA Rx may stop before the end of the full transaction. So, wait
on DMA Tx instead.
Then, the SPI data won't be consumed by the DMA. We need to properly reset
the fifo before to start a new transaction (it is better to ensure we start
with a clean state before every transaction).
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
