Adapt all Espressif SoC and driver code to the updated
hal_espressif module synced with IDF master branch.
Main changes:
- clock control: delegate peripheral clock gating to HAL
layer using new clock/reset APIs
- SPI/GDMA: adapt to restructured DMA HAL with new channel
allocation and configuration interfaces
- ethernet: add RMII clock configuration and PHY management
- GPIO: simplify using direct HAL function calls
- flash: adapt to updated SPI flash HAL interfaces
- linker scripts: update IRAM/DRAM mappings for new HAL
object files
- DTS: fix ESP32-S2 PSRAM dcache1 address to match actual
MMU mapping region (0x3f800000 DRAM1 instead of 0x3f500000
DPORT which lacks 8-bit access capability)
- west.yml: update hal_espressif revision
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This commit is to add DTC transfer feature for both SPI controller mode
and peripheral mode on board RSK-RX130-512KB
Signed-off-by: Minh Tang <minh.tang.ue@bp.renesas.com>
Add the additional required busy wait needed when accesseng SPI registers
during setup of a new SPI transaction.
Signed-off-by: Pete Johanson <pete.johanson@analog.com>
Update driver to follow this, stated in the documentation of the
spi_context_release: "appropriate time to call this would be at the
end of a transfer that was initiated by a transceive API call, except
in the case that the SPI_LOCK_ON bit was set"
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
The SPI loopback test suite passes up transfers nop and null buffers
to the device drivers, expecting them to return early with -EINVAL
or -ENOTSUP, before setting the CS pins. Currently the NRFX based
nRF SPIM device driver sets CS unconditionally, without checking
the buffers, resulting in no transfer while toggling CS.
Add a check of the provided buffers in the transceive() function and
return early if buffers are invalid (result in 0 lenght transfer).
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Avoid this warning associated with the spi_context_cs_* functions
when DT_SPI_CTX_HAS_NO_CS_GPIOS is defined.
warning: statement with no effect [-Wunused-value]
Signed-off-by: Bill Waters <bill.waters@infineon.com>
Several NXP drivers require clock control subsystem name definition in
Devicetree. It prevents usage of clock control without subsystem such
as fixed-clock. fixed-clock can be used for early SoC enablement when
complete clock controller is not available or not required.
Allow optional usage of clock control without subsystem by using 0 as
subsystem name if the name is not defined in devicetree. Add the option
for port, i2c, spi and serial drivers.
Signed-off-by: Michal Smola <michal.smola@nxp.com>
Define IFX_SCB_ARRAY_SIZE for PSoC Edge SoCs to properly
determine the SCB array size.
Without this change, the driver fails to compile on
PSoC Edge platforms
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
Fix trailing commas in ADVANCED_SPI_FIELDS macro definition
and its usage to ensure clean macro expansion.
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
Use the new SPI FIFO related property to retrieve FIFO size (instead of
guessing it from the supported data width), and to check that the
TSIZE register is not written with a value that exceeds the maximal
supported transfer size.
Also reorder the spi_stm32_config structure to have better packing.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
For an asynchronous transfer, the driver was waiting until transfer was
ended to leave the transceive function, which defeated the purpose of
async. Restore previous behavior. The transfer is still blocking for
half duplex though.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
This commit adds the support of the FIFO threshold for H7-compatible SPI.
This makes full use of the two FIFOs (Tx and Rx) available for these
devices, by packing the frames together in a single read or write when
possible, reducing the number of operations.
The FIFO threshold is supported only when fifo-enabled property is enabled
in device tree.
This new implementation is useful in interrupt mode at fast speed:
on Nucleo H753ZI, test_spi_complete_multiple_timed at fast speed indicates
a theoretical minimum duration of 27 µs, with a latency measurement of
18 µs for the new code against 34 µs previously, and a huge 76 µs when
fifo-enable is not present.
There are no noticeable changes at slow speed, or in polling or DMA mode.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Until now, SPI DMA transfers were not possible for H7-compatible STM32
devices if the fifo-enable property was enabled.
This commit adds the support of this property with DMA usage.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
In Slave Half-Duplex TX mode, the driver disables SPE immediately
after loading data into DR, before the Master provides clock.
Since the Slave depends on the Master for clock, data is never
actually shifted out.
Fix by treating Slave Half-Duplex TX like SPI_HOLD_ON_CS: keep SPE
enabled after spi_write() returns, and let the application call
spi_release() once the Master has clocked out the data.
Tested on NUCLEO-F439ZI with SPI1 (master) and SPI3 (slave) in
half-duplex configuration.
Signed-off-by: PyoJin Yoon <volphin310@gmail.com>
Add support for the Infineon PSoC 4 family to the SPI driver,
Kconfig options, and polling-based transfer completion for slave
mode as PSoC 4 slave hardware does not control transaction start.
Signed-off-by: Dharun krithik k <dharunkrithik@aerlync.com>
Signed-off-by: Sayooj K Karun <sayooj@aerlync.com>
Implement ifx_get_hw_block_num to retrieve the hardware block number
for a given SCB base address. This replaces the dependency on the
UART-specific lookup function ifx_cat1_uart_get_hw_block_num, making
the SPI driver more self-contained and ensuring correct resource
identification for SCB blocks.
Signed-off-by: Dharun krithik k <dharunkrithik@aerlync.com>
Signed-off-by: Sayooj K Karun <sayooj@aerlync.com>
Rename Kconfig options and internal macros to remove "CAT1" specificity,
making the driver more generic for the Infineon family. This is a
non-functional change to prepare for PSoC 4 support.
Signed-off-by: Dharun krithik k <dharunkrithik@aerlync.com>
Signed-off-by: Sayooj K Karun <sayooj@aerlync.com>
If the clock device (i.e., RCC) failed to initialize, we have bigger
problems than trying to call clock_control_{off,on,configure} on it.
Don't bother checking to save some footprint.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Replace remaining ll_func_* by ll_* for LL function redefinitions in the
STM32 SPI driver.
Fixes: 938fe74aae
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
We converted the QMSPI-LDMA driver to linux style with a local
register header in the driver folder. This is part of the long
term plan to remove the MEC5 HAL and have common drivers for
as many SoC's as possible. QMSPI register definitions are in
the SoC layer to be shared with other drivers (MSPI). The driver
was also updated based on changes in the SPI config structure.
The lastest SPI config structure changes force hardware controlled
chip selects and GPIO controlled chip selects to be mutually exclusive.
NOTE: driver works with the flash driver sample
and passes the common flash driver test.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Before that commit spi was not available for the soc sy1xx.
With this commit a basic usage of spi is possible.
Signed-off-by: Sven Ginka <s.ginka@sensry.de>
Co-authored-by: Fin Maaß <f.maass@vogl-electronic.com>
The Siwx91x GSPI controller requires the FIFO reset bits to be
held high for a minimum of one GSPI bus clock cycle.
Currently, the driver asserts and deasserts the reset back-to-back,
which may result in an insufficient reset pulse width at higher
frequencies.
Add a small, frequency-based delay after asserting the FIFO reset
bits to guarantee the minimum reset duration, ensuring reliable
FIFO reset behavior.
Signed-off-by: Sai Santhosh Malae <Santhosh.Malae@silabs.com>
Update the GSPI DMA configuration to conditionally register the DMA
callback based on transfer direction and RX buffer presence. The
callback is enabled for TX-only transfers when the RX buffer is NULL
and for RX transfers when a valid RX buffer is provided.
Signed-off-by: Sai Santhosh Malae <Santhosh.Malae@silabs.com>
On Cortex-M with NVIC, if a peripheral sets its interrupt
flag again while the current handler is executing, the NVIC
pending bit is set. Even after the current handler clears
the flags, the pending bit still remain set. The current
implementation manually clears the pending bit to avoid
unneccesary extra handler calls when no additional
processing is required.
On other Arm GIC-based platforms like Cortex-R52, the GIC
automatically clears the pending bit when the peripheral
flag is cleared since these interrupts are level-sensitive.
Therefore, manually clearing the pending bit is unneccesary.
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
The current stm32 drivers will only enable soft NSS support if
the device is using a Zephyr managed GPIO for CS, or if the
CONFIG_SPI_STM32_USE_HW_SS flag is set. Neither of these are
actually appropriate for a peripheral, which doesn't control CS.
With this change, it is possible for the SPI interface to be
configured as a peripheral but still use soft NSS -- otherwise,
short of creating a "fake" GPIO configuration, the peripheral
will always use hard NSS, and for some boards/configurations,
that is unworkable. In the case of a board where the CS
is not hooked up, we can use soft NSS to allow the peripheral
to assume CS and be driven by the SPI clock signal alone.
Our board has only three signals (clock, COPI, POCI) enabled
on one of the SPI interfaces (it is communicating with another
MCU on the same board), and works with this change. Without
the change, we must enable a "fake" GPIO driver configuration
(which is never used for anything, and really makes little
sense for a peripheral, but it just happens to force the
driver to go down that code path). We cannot disable the
CONFIG_SPI_STM32_USE_HW_SS mechanism, as that impacts ALL
interfaces, and we have a second interface in controller
mode that speaks to flash and requires the NSS_HARD codepath.
Signed-off-by: Rob Newberry <rob@zenomoto.com>
With writing to `master_rxtx_addr` the transfer starts
and with that the interrupt for rx can also come at any time after it.
If that interrupt happens during
spi_context_update_tx, it can lead to some undefined behavior.
In my case I got a `Load access fault` due to some later code,
then wanting to read a write only area. Probably
`tx_count` in `struct spi_context` being decremented one to many,
so it would be the max value of size_t.
Also we don't want to do `spi_context_update_tx`
before `spi_context_wait_for_completion()`. As
it contains `spi_context_total_tx_len()` and that
needs the not incremented `current_tx`.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Add the `DEVICE_API` wrapper to the remaining `spi_driver_api` instances,
ensuring that each driver API is placed in its respective linker section.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Initialize p_reg with the register base address from devicetree.
Signed-off-by: Hoang Nguyen <hoang.nguyen.jx@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
make the rxtx size a define, as this driver
does not support any other value and it's
also not configureable in litex.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Harmonize the variable names frame_size, bytes_per_frame or word_size_bytes
by replacing them all with dfs, which is already used in the Zephyr SPI
driver.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Replace the direct read from the registers by dedicated LL functions
since that they are now available.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Define a single function to enable the DMA requests instead of duplicating
the same lines several times.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
This commit removes some line breaks from function definitions that were
not needed since it can fit on one line.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
In case of error from the spi_stm32_shift_frames, spi_stm32_complete
could be called twice if one of the condition with the transfer directiion
were true. To prevent this, add a return after the call to
spi_stm32_complete.
Simplify the if/else block with a single if since spi_stm32_complete is
called in every case.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
The functions spi_stm32_send_next_frame and spi_stm32_read_next_frame
already exist to send and receive next frame. Use them in slave mode
instead of doing it manually.
Additional checks with spi_context_tx_buf_on and spi_context_rx_buf_on are
done inside these functions but they are already done beforehand in slave
mode.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
