Validate the SPI bus frequency supplied via spi_config before it is
used to compute the baud-rate clock divider to prevent the following
faults:
- A zero frequency causes an integer division-by-zero when computing
the clock divider, resulting in a hardware fault or an undefined
value being written to the SPI_BAUDR register.
- A frequency exceeding half of the input core clock produces a
divider value less than the minimum of 2 required by the
DesignWare SSI databook (section 6.2.2), overclocking the
peripheral and causing undefined bus behaviour.
Return -EINVAL for a zero frequency and -EINVAL for a frequency
greater than clk_hz / 2, surfacing the error to the caller rather
than silently misconfiguring the hardware.
Assisted-by: Claude:claude-opus-4.6
Signed-off-by: Sudarshan Iyengar <sudarshan.iyengar@alifsemi.com>
When configuring the nRF SPIM, the frequency needs to be limited by
the max frequency of the SPIM, which is specified in the devicetree.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Fix SPI clock frequency being modified during DMA transfers.
Fix regression in DMA configuration structure update.
Signed-off-by: Rick Tsao <rick592@andestech.com>
Fix incorrect behavior for non-8-bit SPI word sizes.
Fix the handling when both TX and RX buffers are NULL.
Signed-off-by: Rick Tsao <rick592@andestech.com>
Replace direct esp_cache_msync() calls in the ESP32 GDMA and
SPI master drivers with the portable sys_cache_data_*() API.
Zephyr's API is a compile-time no-op when CACHE_MANAGEMENT is
disabled, so the same source compiles cleanly on every ESP32
SoC and stays cost-free where there is no writeback cache.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Improve the LPSPI RTIO FIFO path by increasing the fifo
watermark if possible, this reduces IRQ load. Add DMA
support
Signed-off-by: Peter van der Perk <peter.vanderperk@nxp.com>
Since commit 37717b229f ("sys: util: rename Z_MIN Z_MAX Z_CLAMP to min
max and clamp"), <zephyr/sys/util.h> unconditionally defines function-
like macros named `min`, `max`, and `clamp` in the global namespace (in
C mode). util.h gets pulled in transitively by very broad headers,
including the POSIX layer's <pthread.h>, so any third-party C code that
uses these names as ordinary identifiers (e.g. XNNPACK's static `clamp`
helper and its public `clamp` struct field) fails to build as soon as
<pthread.h> is included.
Following the approach used by Linux, move the lowercase `min`, `max`,
`min3`, `max3`, and `clamp` macros (and their helpers) into a new
<zephyr/sys/minmax.h> header that has to be included explicitly by
source files that want them. util.h keeps the uppercase MIN/MAX/CLAMP,
so most code is unaffected; only the (much smaller) set of files that
actually use the lowercase variants needs to pick up the new include.
Fixes#107853.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Move SSDE enable after preload to prevent premature SSL interrupts
Fix DMA fallback to always have ISR variables available
Signed-off-by: Mohamed Azhar <mohamed.azhar@microchip.com>
- Add DMA support for SPI on RZ/N2L, T2M since the previously supported
had not support DMA.
- Add initial support SPI driver for board RZ/T2L.
Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
add reset controller support to the NXP LPSPI driver and
use reset controller APIs if available.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
The current flow sets CS before the SPIM peripheral actually drives
the bus. This can cause SCK to be in the incorrect initial state
dictated by CPOL. New flow enables SPIM after it has been configured,
before CS is set, and disabled is after CS is cleared, thus the bus
is driven by SPIM during the entire transfer.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
The gpiote_nrfx.h header is needed for a macro used when handling
NRF52_ANOMALY_58
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
The spi context tx_buf, rx_buf, tx_count and rx_count members are
modified during the transfer. These members are currently accessed
in spi_context_wait_for_completion when calculating the expected
timeout, which happens concurrently with the transfer being in
progress. This can lead to concurrency issues as the mentioned
members may be modified independently as they are being accessed by
the thread setting up the wait.
Remove this potential conflict by calculating the number of bytes
as part of spi_context_buffers_setup and store it, before the
transfer is started. Then used the stored value when setting up
the wait.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Ensure SPI pins are correctly configured before setting CS, by
configuring the SPIM before setting CS.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
The common pm_suspend implementation for the spi_nrfx_spim drivers
unconditionally sets the sleep state. The sleep state may not be
available, in which case we should not try to set it. Check
CONFIG_PINCTRL_KEEP_SLEEP_STATE and only try to set sleep state if
true.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
The header at drivers/spi/rtio.h was moved to a relative path, and
renamed "spi_rtio.h".
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
The SAM0 SPI driver previously supported DMA only for asynchronous
operations, which required higher-level drivers needing blocking DMA
transfers to implement workarounds. This patch extends DMA support
to the synchronous transfer path, enabling efficient blocking SPI
transactions without driver-specific hacks.
With this change, both synchronous and asynchronous SPI operations
can leverage DMA for improved performance and reduced CPU overhead.
Signed-off-by: Ramya T <ramya.t@microchip.com>
Signed-off-by: Parthiban Veerasooran <parthiban.veerasooran@microchip.com>
Move to the new MXC_SPI_GetAndClearFlags API to avoid a race condition
where flags not handled in the ISR would be cleared and missed as a result.
This fix removes the need for the previous partial workaround that simply
masked the issue in most scenario.
Signed-off-by: Pete Johanson <pete.johanson@analog.com>
When DMA is enabled, but there are no DMA channels assigned to the SPI
peripheral, properly fall back to setting up the dummy bytes for SPI RTIO
operations.
Signed-off-by: Pete Johanson <pete.johanson@analog.com>
Add support for the SPI module on TI’s MSPM0 MCUs.
The driver supports master mode transfers with configurable
frame size (4–16 bits), clock polarity/phase, bit order.
Signed-off-by: Santhosh Charles <santhosh@linumiz.com>
Signed-off-by: Jackson Farley <j-farley@ti.com>
Co-authored-by: Hans Binderup <habi@bang-olufsen.dk>
Enable Active-High polarity for SPI chip-select in Xilinx AXI QSPI Driver.
Required e.g. for SD-Card support.
Signed-off-by: Martin Anschütz <martin.anschuetz@vert-tec.io>
Fixed CTRLA register write bugs in spi g1 driver
Updated the transfer function for handling dma mode
Fixes#106580
Signed-off-by: Mohamed Azhar <mohamed.azhar@microchip.com>
Refactor the nrf_spim device driver to share the common code between
the nrf_spim_rtio implementation.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Move the private spi_rtio.h header from the public path
include/zephyr/drivers/spi/rtio.h
the the private path
drivers/spi/spi_rtio.h
and update drivers to include it using a relative path.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
The SPI_LOCK_ON flag is not compatible with RTIO, nor is the
related spi_release API. Introduce stub implementation for drivers to
use which simply returns -ENOTSUP and validate SPI_LOCK_ON within the
spi_rtio_transceive wrappers.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Introduce spi_rtio_transceive_cb which is an implementation of the
spi_transceive_cb API based on the spi_rtio context.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Don't rely on drivers protecting the spi_rtio ctx from multiple
threads as this is generic and could just be part of the spi_rtio
context to avoid duplicate code and thus make using it safer and
more efficient.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
The spi_rtio_copy implementation incorrectly sets up a transceive sqe
in place of a write or read when an empty "spacer" spi_buf is passed
which is not aligned with the "opposing" spi_buf. Using transceive in
these cases passes a NULL receive/transmit buffer with positive length,
which is a bug.
Some drivers have an additional check to clear the size if the buffer
is NULL, but we should not rely on this check in drivers as it is
duplicate code.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Correct some behaviors that were broken in the original SPI DMA + RTIO
work:
* Properly fallback to interrupt behavior if no DMA channels are assigned
to a given SPI peripheral.
* Properly handle held CS lines across transactions when using hardware CS
control.
Signed-off-by: Pete Johanson <pete.johanson@analog.com>
The Cadence SPI driver relied on a conditional guard around software RX
accounting (tx_remain_entry/fifo_diff) in spi_cdns_send(). During
opcode/address/dummy phases (e.g., SPI NOR reads), the RX segment may be
NULL (discard), causing the guard to evaluate false. This prevented the
driver from tracking RX entries generated by each TX entry and could
lead to RX FIFO overflow.
Fix this by always decrementing tx_remain_entry and incrementing
fifo_diff for every TX FIFO entry pushed. Since SPI is full‑duplex, each
TX entry clocks in one RX entry, regardless of whether the client
provides an RX buffer for that phase. The ISR drains RX while fifo_diff
> 0, so keeping fifo_diff accurate prevents overflow.
Also update spi_cdns_recv() RX context handling to be mode-aware:
- In slave mode, advance RX context only when an RX buffer is present.
- In master mode, advance RX context for each received frame.
This keeps slave receive accounting consistent while preserving correct
master behavior, and aligns with the software-tracking approach used to
avoid unreliable RX_NOT_EMPTY status (AR#65885).
As part of this change, refactor spi_cdns_recv() to reduce cognitive
complexity and improve readability, without changing functional behavior.
Signed-off-by: Srikanth Boyapally <srikanth.boyapally@amd.com>
Includes file for mapping DFP macros to follow a common macro
name for sercom spi g1 driver
Optimizes the driver
Signed-off-by: Mohamed Azhar <mohamed.azhar@microchip.com>
After #99399 the workaround for errata 58 in nRF52 chips is removed from
zephyr RTOS and is now part of the nrfx sdk. The initial glue code
between zephyr->nrfx 4.0.0 missed the initializatio of the errata 58
workaround. This commit adds the initialization to the glue code. Given
the errata only applies to nRF52 chips, is safe to assume there is a
single GPIOTE instance present.
Signed-off-by: Jose Morales <josfemova@gmail.com>
There are different naming conventions between
the two HAL, so we make conditional compilation
through intermediate symbols.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
Select the GPIO driver in the Kconfig if at least one active SPI instance
is using a GPIO Chip Select.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Added DMA support for transcieve_async using k_work for multi-buffer
transfers. Fixed bug where error isn't reported to spi_context_complete
when DMA callback receives an errorby ensuring it's invoked and the
transceive exits gracefully. Fixed bug where transceive would
loop infinitely when data size less than dma word size by skipping
the buffer that is too short.
Signed-off-by: Ryan Wiebe <ryan.wiebe@analog.com>
Remove the duplicated ifx_cat1_get_hfclk_for_peri_group() function and
replace with the version from the clock_control header.
Assisted-by: GitHub Copilot:claude-opus-4.6
Signed-off-by: John Batch <john.batch@infineon.com>
