The SPI_LOCK_ON flag is not compatible with RTIO, nor is the
related spi_release API. Introduce stub implementation for drivers to
use which simply returns -ENOTSUP and validate SPI_LOCK_ON within the
spi_rtio_transceive wrappers.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Introduce spi_rtio_transceive_cb which is an implementation of the
spi_transceive_cb API based on the spi_rtio context.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Don't rely on drivers protecting the spi_rtio ctx from multiple
threads as this is generic and could just be part of the spi_rtio
context to avoid duplicate code and thus make using it safer and
more efficient.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
The spi_rtio_copy implementation incorrectly sets up a transceive sqe
in place of a write or read when an empty "spacer" spi_buf is passed
which is not aligned with the "opposing" spi_buf. Using transceive in
these cases passes a NULL receive/transmit buffer with positive length,
which is a bug.
Some drivers have an additional check to clear the size if the buffer
is NULL, but we should not rely on this check in drivers as it is
duplicate code.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Correct some behaviors that were broken in the original SPI DMA + RTIO
work:
* Properly fallback to interrupt behavior if no DMA channels are assigned
to a given SPI peripheral.
* Properly handle held CS lines across transactions when using hardware CS
control.
Signed-off-by: Pete Johanson <pete.johanson@analog.com>
The Cadence SPI driver relied on a conditional guard around software RX
accounting (tx_remain_entry/fifo_diff) in spi_cdns_send(). During
opcode/address/dummy phases (e.g., SPI NOR reads), the RX segment may be
NULL (discard), causing the guard to evaluate false. This prevented the
driver from tracking RX entries generated by each TX entry and could
lead to RX FIFO overflow.
Fix this by always decrementing tx_remain_entry and incrementing
fifo_diff for every TX FIFO entry pushed. Since SPI is full‑duplex, each
TX entry clocks in one RX entry, regardless of whether the client
provides an RX buffer for that phase. The ISR drains RX while fifo_diff
> 0, so keeping fifo_diff accurate prevents overflow.
Also update spi_cdns_recv() RX context handling to be mode-aware:
- In slave mode, advance RX context only when an RX buffer is present.
- In master mode, advance RX context for each received frame.
This keeps slave receive accounting consistent while preserving correct
master behavior, and aligns with the software-tracking approach used to
avoid unreliable RX_NOT_EMPTY status (AR#65885).
As part of this change, refactor spi_cdns_recv() to reduce cognitive
complexity and improve readability, without changing functional behavior.
Signed-off-by: Srikanth Boyapally <srikanth.boyapally@amd.com>
Includes file for mapping DFP macros to follow a common macro
name for sercom spi g1 driver
Optimizes the driver
Signed-off-by: Mohamed Azhar <mohamed.azhar@microchip.com>
After #99399 the workaround for errata 58 in nRF52 chips is removed from
zephyr RTOS and is now part of the nrfx sdk. The initial glue code
between zephyr->nrfx 4.0.0 missed the initializatio of the errata 58
workaround. This commit adds the initialization to the glue code. Given
the errata only applies to nRF52 chips, is safe to assume there is a
single GPIOTE instance present.
Signed-off-by: Jose Morales <josfemova@gmail.com>
There are different naming conventions between
the two HAL, so we make conditional compilation
through intermediate symbols.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
Select the GPIO driver in the Kconfig if at least one active SPI instance
is using a GPIO Chip Select.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Added DMA support for transcieve_async using k_work for multi-buffer
transfers. Fixed bug where error isn't reported to spi_context_complete
when DMA callback receives an errorby ensuring it's invoked and the
transceive exits gracefully. Fixed bug where transceive would
loop infinitely when data size less than dma word size by skipping
the buffer that is too short.
Signed-off-by: Ryan Wiebe <ryan.wiebe@analog.com>
Remove the duplicated ifx_cat1_get_hfclk_for_peri_group() function and
replace with the version from the clock_control header.
Assisted-by: GitHub Copilot:claude-opus-4.6
Signed-off-by: John Batch <john.batch@infineon.com>
Driver initialization is expected to keep the driver in the
suspended stage before calling pm_device_driver_init. It means
that initialization should set pinctrl SLEEP stage. Nordic SPIS
driver was not doing that. If device runtime PM was enabled it
resulted in pins being in the default state when it was expected
that they are in the sleep state.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Adapt all Espressif SoC and driver code to the updated
hal_espressif module synced with IDF master branch.
Main changes:
- clock control: delegate peripheral clock gating to HAL
layer using new clock/reset APIs
- SPI/GDMA: adapt to restructured DMA HAL with new channel
allocation and configuration interfaces
- ethernet: add RMII clock configuration and PHY management
- GPIO: simplify using direct HAL function calls
- flash: adapt to updated SPI flash HAL interfaces
- linker scripts: update IRAM/DRAM mappings for new HAL
object files
- DTS: fix ESP32-S2 PSRAM dcache1 address to match actual
MMU mapping region (0x3f800000 DRAM1 instead of 0x3f500000
DPORT which lacks 8-bit access capability)
- west.yml: update hal_espressif revision
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This commit is to add DTC transfer feature for both SPI controller mode
and peripheral mode on board RSK-RX130-512KB
Signed-off-by: Minh Tang <minh.tang.ue@bp.renesas.com>
Add the additional required busy wait needed when accesseng SPI registers
during setup of a new SPI transaction.
Signed-off-by: Pete Johanson <pete.johanson@analog.com>
Update driver to follow this, stated in the documentation of the
spi_context_release: "appropriate time to call this would be at the
end of a transfer that was initiated by a transceive API call, except
in the case that the SPI_LOCK_ON bit was set"
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
The SPI loopback test suite passes up transfers nop and null buffers
to the device drivers, expecting them to return early with -EINVAL
or -ENOTSUP, before setting the CS pins. Currently the NRFX based
nRF SPIM device driver sets CS unconditionally, without checking
the buffers, resulting in no transfer while toggling CS.
Add a check of the provided buffers in the transceive() function and
return early if buffers are invalid (result in 0 lenght transfer).
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Avoid this warning associated with the spi_context_cs_* functions
when DT_SPI_CTX_HAS_NO_CS_GPIOS is defined.
warning: statement with no effect [-Wunused-value]
Signed-off-by: Bill Waters <bill.waters@infineon.com>
Several NXP drivers require clock control subsystem name definition in
Devicetree. It prevents usage of clock control without subsystem such
as fixed-clock. fixed-clock can be used for early SoC enablement when
complete clock controller is not available or not required.
Allow optional usage of clock control without subsystem by using 0 as
subsystem name if the name is not defined in devicetree. Add the option
for port, i2c, spi and serial drivers.
Signed-off-by: Michal Smola <michal.smola@nxp.com>
Define IFX_SCB_ARRAY_SIZE for PSoC Edge SoCs to properly
determine the SCB array size.
Without this change, the driver fails to compile on
PSoC Edge platforms
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
Fix trailing commas in ADVANCED_SPI_FIELDS macro definition
and its usage to ensure clean macro expansion.
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
Use the new SPI FIFO related property to retrieve FIFO size (instead of
guessing it from the supported data width), and to check that the
TSIZE register is not written with a value that exceeds the maximal
supported transfer size.
Also reorder the spi_stm32_config structure to have better packing.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
For an asynchronous transfer, the driver was waiting until transfer was
ended to leave the transceive function, which defeated the purpose of
async. Restore previous behavior. The transfer is still blocking for
half duplex though.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
This commit adds the support of the FIFO threshold for H7-compatible SPI.
This makes full use of the two FIFOs (Tx and Rx) available for these
devices, by packing the frames together in a single read or write when
possible, reducing the number of operations.
The FIFO threshold is supported only when fifo-enabled property is enabled
in device tree.
This new implementation is useful in interrupt mode at fast speed:
on Nucleo H753ZI, test_spi_complete_multiple_timed at fast speed indicates
a theoretical minimum duration of 27 µs, with a latency measurement of
18 µs for the new code against 34 µs previously, and a huge 76 µs when
fifo-enable is not present.
There are no noticeable changes at slow speed, or in polling or DMA mode.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Until now, SPI DMA transfers were not possible for H7-compatible STM32
devices if the fifo-enable property was enabled.
This commit adds the support of this property with DMA usage.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
In Slave Half-Duplex TX mode, the driver disables SPE immediately
after loading data into DR, before the Master provides clock.
Since the Slave depends on the Master for clock, data is never
actually shifted out.
Fix by treating Slave Half-Duplex TX like SPI_HOLD_ON_CS: keep SPE
enabled after spi_write() returns, and let the application call
spi_release() once the Master has clocked out the data.
Tested on NUCLEO-F439ZI with SPI1 (master) and SPI3 (slave) in
half-duplex configuration.
Signed-off-by: PyoJin Yoon <volphin310@gmail.com>
Add support for the Infineon PSoC 4 family to the SPI driver,
Kconfig options, and polling-based transfer completion for slave
mode as PSoC 4 slave hardware does not control transaction start.
Signed-off-by: Dharun krithik k <dharunkrithik@aerlync.com>
Signed-off-by: Sayooj K Karun <sayooj@aerlync.com>
Implement ifx_get_hw_block_num to retrieve the hardware block number
for a given SCB base address. This replaces the dependency on the
UART-specific lookup function ifx_cat1_uart_get_hw_block_num, making
the SPI driver more self-contained and ensuring correct resource
identification for SCB blocks.
Signed-off-by: Dharun krithik k <dharunkrithik@aerlync.com>
Signed-off-by: Sayooj K Karun <sayooj@aerlync.com>
Rename Kconfig options and internal macros to remove "CAT1" specificity,
making the driver more generic for the Infineon family. This is a
non-functional change to prepare for PSoC 4 support.
Signed-off-by: Dharun krithik k <dharunkrithik@aerlync.com>
Signed-off-by: Sayooj K Karun <sayooj@aerlync.com>
If the clock device (i.e., RCC) failed to initialize, we have bigger
problems than trying to call clock_control_{off,on,configure} on it.
Don't bother checking to save some footprint.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Replace remaining ll_func_* by ll_* for LL function redefinitions in the
STM32 SPI driver.
Fixes: 938fe74aae
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
