We converted the QMSPI-LDMA driver to linux style with a local
register header in the driver folder. This is part of the long
term plan to remove the MEC5 HAL and have common drivers for
as many SoC's as possible. QMSPI register definitions are in
the SoC layer to be shared with other drivers (MSPI). The driver
was also updated based on changes in the SPI config structure.
The lastest SPI config structure changes force hardware controlled
chip selects and GPIO controlled chip selects to be mutually exclusive.
NOTE: driver works with the flash driver sample
and passes the common flash driver test.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Before that commit spi was not available for the soc sy1xx.
With this commit a basic usage of spi is possible.
Signed-off-by: Sven Ginka <s.ginka@sensry.de>
Co-authored-by: Fin Maaß <f.maass@vogl-electronic.com>
The Siwx91x GSPI controller requires the FIFO reset bits to be
held high for a minimum of one GSPI bus clock cycle.
Currently, the driver asserts and deasserts the reset back-to-back,
which may result in an insufficient reset pulse width at higher
frequencies.
Add a small, frequency-based delay after asserting the FIFO reset
bits to guarantee the minimum reset duration, ensuring reliable
FIFO reset behavior.
Signed-off-by: Sai Santhosh Malae <Santhosh.Malae@silabs.com>
Update the GSPI DMA configuration to conditionally register the DMA
callback based on transfer direction and RX buffer presence. The
callback is enabled for TX-only transfers when the RX buffer is NULL
and for RX transfers when a valid RX buffer is provided.
Signed-off-by: Sai Santhosh Malae <Santhosh.Malae@silabs.com>
On Cortex-M with NVIC, if a peripheral sets its interrupt
flag again while the current handler is executing, the NVIC
pending bit is set. Even after the current handler clears
the flags, the pending bit still remain set. The current
implementation manually clears the pending bit to avoid
unneccesary extra handler calls when no additional
processing is required.
On other Arm GIC-based platforms like Cortex-R52, the GIC
automatically clears the pending bit when the peripheral
flag is cleared since these interrupts are level-sensitive.
Therefore, manually clearing the pending bit is unneccesary.
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
The current stm32 drivers will only enable soft NSS support if
the device is using a Zephyr managed GPIO for CS, or if the
CONFIG_SPI_STM32_USE_HW_SS flag is set. Neither of these are
actually appropriate for a peripheral, which doesn't control CS.
With this change, it is possible for the SPI interface to be
configured as a peripheral but still use soft NSS -- otherwise,
short of creating a "fake" GPIO configuration, the peripheral
will always use hard NSS, and for some boards/configurations,
that is unworkable. In the case of a board where the CS
is not hooked up, we can use soft NSS to allow the peripheral
to assume CS and be driven by the SPI clock signal alone.
Our board has only three signals (clock, COPI, POCI) enabled
on one of the SPI interfaces (it is communicating with another
MCU on the same board), and works with this change. Without
the change, we must enable a "fake" GPIO driver configuration
(which is never used for anything, and really makes little
sense for a peripheral, but it just happens to force the
driver to go down that code path). We cannot disable the
CONFIG_SPI_STM32_USE_HW_SS mechanism, as that impacts ALL
interfaces, and we have a second interface in controller
mode that speaks to flash and requires the NSS_HARD codepath.
Signed-off-by: Rob Newberry <rob@zenomoto.com>
With writing to `master_rxtx_addr` the transfer starts
and with that the interrupt for rx can also come at any time after it.
If that interrupt happens during
spi_context_update_tx, it can lead to some undefined behavior.
In my case I got a `Load access fault` due to some later code,
then wanting to read a write only area. Probably
`tx_count` in `struct spi_context` being decremented one to many,
so it would be the max value of size_t.
Also we don't want to do `spi_context_update_tx`
before `spi_context_wait_for_completion()`. As
it contains `spi_context_total_tx_len()` and that
needs the not incremented `current_tx`.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Add the `DEVICE_API` wrapper to the remaining `spi_driver_api` instances,
ensuring that each driver API is placed in its respective linker section.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Initialize p_reg with the register base address from devicetree.
Signed-off-by: Hoang Nguyen <hoang.nguyen.jx@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
make the rxtx size a define, as this driver
does not support any other value and it's
also not configureable in litex.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Harmonize the variable names frame_size, bytes_per_frame or word_size_bytes
by replacing them all with dfs, which is already used in the Zephyr SPI
driver.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Replace the direct read from the registers by dedicated LL functions
since that they are now available.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Define a single function to enable the DMA requests instead of duplicating
the same lines several times.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
This commit removes some line breaks from function definitions that were
not needed since it can fit on one line.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
In case of error from the spi_stm32_shift_frames, spi_stm32_complete
could be called twice if one of the condition with the transfer directiion
were true. To prevent this, add a return after the call to
spi_stm32_complete.
Simplify the if/else block with a single if since spi_stm32_complete is
called in every case.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
The functions spi_stm32_send_next_frame and spi_stm32_read_next_frame
already exist to send and receive next frame. Use them in slave mode
instead of doing it manually.
Additional checks with spi_context_tx_buf_on and spi_context_rx_buf_on are
done inside these functions but they are already done beforehand in slave
mode.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Create a new function that calculates and set the transfer size depending
on the transfer direction (for H7 compatibles).
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Fixes the Kconfig name of this so that it matches the value from
soc.yml, and deprecates the old name - this is required to support
future build system features. Additionally, it fixes an issue in
Kconfigs of this SoC of duplicating existing symbols
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Adds making a peripheral clock connection to the initialiazation for SCB
based drivers. These drivers are the UART/Serial driver, I2C driver, and
SPI driver.
Signed-off-by: John Batch <john.batch@infineon.com>
Use SHELL_HELP macro for help strings to ensure consistency across
various shell modules and to save on code size.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
RUN_FN_ON_SPI_DEVICE to run a given fn only if the node_id is a direct
child of the SPI controller (i.e. DT_PARENT(node_id) == DT_BUS(node_id)),
and the node itself has status okay. This prevents enumerating sub-nodes
of SPI devices (for example GPIO sub-devices) which are not direct
children of the SPI controller.
Fixes#99785
Signed-off-by: Andreas Schmidt <andreas.schmidt@dormakaba.com>
This adds optional clock control support to the spi_dw driver. The
support currently assumes that the clock control binding uses clkid for
the clock cell name.
Signed-off-by: Łukasz Kędziora <lkedziora@antmicro.com>
Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com>
Signed-off-by: Andreas Weissel <andreas.weissel@synaptics.com>
- Add SPI driver for Microchip SERCOM g1
- Add and update Kconfig files to support the driver
- Update CMakeLists.txt to include the new driver
Signed-off-by: Mohamed Azhar <mohamed.azhar@microchip.com>
Add clock_control_configure() call during initialization to properly
configure the LPSPI clock. The implementation gracefully handles
platforms that don't support clock configuration by checking for
-ENOTSUP and -ENOSYS return codes and continuing with default
settings. Real configuration errors are logged and propagated.
Signed-off-by: Albort Xue <yao.xue@nxp.com>
The condition `!spi_context_rx_buf_on(ctx) && spi_context_rx_on(ctx)`
only returns early when RX is active with a NOP buffer.
However, when `rx_len == 0`, `spi_context_rx_on(ctx)` returns false,
causing the early return to be skipped.
This leaves `ctx->rx_buf` (which can be NULL) to be dereferenced.
Since `lpspi_handle_rx_irq()` already guarantees `spi_context_rx_on(ctx)`
is true before calling this function, only check
`!spi_context_rx_buf_on(ctx)` to safely handle NOP buffers.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Refactor `lpspi_rx_buf_write_words()` to compute `words_read` upfront
using `MIN(rx_len, max_read)`, simplifying control flow and making
the read limit explicit without changing behavior.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Use NRF_DT_INST_IRQ_ macros which support building with and without
SW ISR table for all nordic socs.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
For clarity and compactness, use
`spi_context_max_continuous_chunk()` instead of open-coding
the same tx/rx length selection logic.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
When transceive is called on a chip without CONFIG_SPI_STM32_INTERRUPT,
spi_stm32_shift_frames was called even if there was no transfer ongoing.
This lead to an unwanted SPI transfer shifting the whole connection,
causing drivers to malfunction.
Fix it by replacing the do-while loop with a while loop.
Signed-off-by: Robyn Milas <robyn.milas@valotec.com>
Since RPI_PICO_PIO_GET_PROGRAM returns const variable, so changed
`pio_program_t *` variables in data to `const pio_program_t *`.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Move pinctrl_apply_state() from configure to init to ensure pinctrl
is applied once at boot rather than on every transaction.
When cs-gpios is defined, spi_context_cs_configure_all() runs after
pinctrl and reconfigures the CS pin as GPIO, properly overriding
any CS routing set by pinctrl.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Split the code for DMA setting to consider the tx and rx buffers
separately, this makes the driver work for use cases where tx only or rx
only is needed, such as when using this with the ws2812 driver.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The driver was unconditionally setting hal_dev->cs_pin_id to the target
number, which activates hardware CS lines even when GPIO-based chip
select (cs-gpios) is used. This caused issues when using hardware CS
via pinctrl with reg > 0.
Also update the binding documentation to clarify the interaction between
cs-gpios and hardware CS via pinctrl.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Drop cat1 from the binding files to enable reuse by other
category devices as well.
Fixes#99174
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
Remove duplicated #include directives within the same
preprocessor scope across the Zephyr tree.
Duplicates inside different #ifdef branches are preserved
as they may be intentional.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
depending on build configuration, spi_context_cs_configure_all() is a
no-opt, so mark the data variable as maybe unused.
Signed-off-by: Martin Gysel <me@bearsh.org>
- call spi_stm32_pm_policy_state_lock_xxx functions wenn context is
locked
- do not call spi_stm32_pm_policy_state_lock_put() in internal helper
spi_stm32_complete() (which gets called from various places) but at the
end of a transfer where it belong
Signed-off-by: Martin Gysel <me@bearsh.org>
