Add support for SPI to cc23x0 SoC. Only controller mode is implemented.
Signed-off-by: Julien Panis <jpanis@baylibre.com>
Signed-off-by: Stoyan Bogdanov <sbogdanov@baylibre.com>
ISR safe runtime PM can only be used for all instances except for
spis120 which requires standard runtime PM.
Added compilation guard against using CONFIG_PM_DEVICE_SYSTEM_MANAGED
with spis120.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Add FOREACH macro which iterates over all SPIM instances and creates
device instances for each enabled instance.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Add compile time detection if fast SPIM instances are used
and system managed device PM is enabled. This configuration is
not supported.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Since these drivers mainly do not use MCUX except for the configure
function (which will soon also be changed), change namespace prefix to
lpspi_ instead of spi_mcux_ to avoid confusion.
Also improve descriptions of kconfigs to clarify what they are for.
Not changing the kconfig names for now since they are user-facing.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Remove SDK types and defines from header file.
And since now the common file is the only consumer of SDK header, move
that include there.
Also rename the tristate boolean to be more clean about what it does
rather than trying to be similar to the SDK config name.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
We should not release context until transfer ends. The code previously
would return from wait_for_completion and then release the context. This
is only supposed to be done in the dma callback except for the case of
error in the transceive call. For async transfer this was most likely
always happening wrong and probably broken for multi threads trying to
access the bus due to this premature release of the context.
Also we should not enable CS and leave enabled in case of error, move CS
enable to after the error check.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Stop the transfer with error if at any point there is some
execution reached where transfer is being set up for 0 length, this can
cause problems where for example eDMA set up with this nonsense 0 length
channels can get an infinite error interrupt.
And this is probably an erroneously crafted transfer request anyways.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
If there are HAL definitions available, do these two things:
Ungate the clock for the device from the zephyr driver. Eventually it
would be better to have a clocks property in the LPSPI DT node and get
the resources from there rather than the HAL.
Some platforms require the peripheral to be reset at system level, add
code to do this. Eventually it would be more ideal to have Zephyr
reset drivers for all of the NXP platforms and use DT to describe the
reset resources, but for now we can just do this to get the LPSPI
supported.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
This commit adds ambiq iom binding file to consolidate
spi and i2c that share the same IO Master module on
Apollo MCUs
Signed-off-by: Hao Luo <hluo@ambiq.com>
Drivers update to use shared interrupt allocator for Xtensa
and RISCV devices.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Allow STM32 SPI driver to operate with DMA support even when
CONFIG_MEM_ATTR is disabled which happen when CONFIG_ARM_MPU is
intentionally disabled despite the CPU supports MPU.
By the way, remove some #ifdef directive on header files inclusion
that add noise in the header file inclusion section without any
benefit.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
The passive level of the clock does not change instanteneously when
it's set using function XMC_SPI_CH_ConfigureShiftClockOutput().
This means that the passive level of the clock can be in the wrong
state when the chip select goes low.
Fix this by adding a small delay when the polarity changes to allow
the clock to return to the proper level.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Fixes wait for completion problems where the ISR was not sending
out TX NOP's when needed causing the transfer to timeout
Signed-off-by: Peter van der Perk <peter.vanderperk@nxp.com>
Remove unnecessary check that the SPI clock is being set to a frequency
above 2 MHz to allow devices running at common lower frequencies (i.e.
1.2 MHz and 400 kHz).
Replace with check that the frequency is not below the minimum frequency
supported by the chipset to prevent overflow error which can occur if
the HAL sets a frequency too low resulting in a SPI clock much larger
than expected.
Fixes#69986
Signed-off-by: David Lim <dlim04@qub.ac.uk>
This commit changes to use ambiq hal power control APIs
to replace the previous register settings to power on
ambiq drivers.
Signed-off-by: Hao Luo <hluo@ambiq.com>
Extend runtime PM to support fast instance (spis120) which requires
additional action in suspend/resume phase.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
clean up usage of select USE_STM32_LL_spi from Kconfig.stm32
this modifications due to the include unconditionally of
stm32xxxx_ll_spi.h in the HAL.
Signed-off-by: Khaoula Bidani <khaoula.bidani-ext@st.com>
There is a bug here clearly which is that if there is some error in the
transceive function, it returns without releasing the context.
This should be fixed by properly handling the errors with a context release
before returning.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
For multi-byte word, there is clearly a bug in that the same byte is
written to each spot in the word instead of writing all the bytes
properly.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Fix the ASYNC DMA API on the lpspi driver and actually make the entire
driver go through that path. Rather than having an orthogonal
internally synchronous path we can just have both APIs go through the
same asynchronous path and just use wait_for_completion from spi context
to implement either sync or async.
Also make DMA driver default y if dependency (an lpspi having dmas
property) is met.
And lpspi_wait_tx_fifo_empty can be shared between drivers.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Since the RA2L1 uses the macro "ICU_EVENT" instead of
"ELC_EVENT" (which is currently used) to input into
the IELSR register, the ek_ra2l1 board cannot assign
any interrupts for any driver.
This commit aim to correct the Event macro to input correct
value for IELSR register on all the Renesas SoC by using
"BSP_PRV_IELS_ENUM" macro.
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
Reintroduce the fast path that skips reconfiguring if we use the same
configuration, this fixes regression that causes a lot of latency at the
start of repeated transfers. Unfortuantely need to find alternative
workaround for S32K3 in order to do this instead of module reset, so
disable skipping for that platform.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
On some platforms, the module is not getting clocked until call to
LPSPI_MasterInit, this will be fixed soon with upcoming update to native
driver and will clock the module in driver init instead of start of
transfer, but for now, move this code within the condition check that
already exists for this purpose.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Personally I found this file hard to understand at first,
but since now it is clear to me, I decided to put these comments
with my understanding to help anyone else who needs to use these.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
This fixes failures seen with the SPI loopback test.
The fix waits for the TX and RX side to be complete
i.e when RX SHIFTBUF has been loaded from the RX Shifter
and the TX SHIFTBUF has transferred to the TX Shifter.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
There are two bugs that caused regression for S32:
First there is a silicon errata specifically for the mask version on
this board that causes FIFO flush to not work as expected. The
workaround is to do a module reset before each transfer.
Second there was a division error for word size > 1 byte. The division
should be rounded up, not down, otherwise there will be an infinite
interrupt loop because the TX fifo will not be written to but the TDR
interrupt enabled causes interrupt when TX fifo is empty.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
These two fields were not being used and were a relic of some
intermediate implementation, and forgot to be removed.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The Kconfig description is wrong, this driver can be used with or
without RTIO. Also, rename the kconfig to be less confusing, as _NORMAL
is meaningless, this is the CPU/interrupt based driver.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Change the driver behavior so that if the provided RX buffer set is
bigger than the TX buffer, we will read all the RX buffer and fill the
TX with NOPs. The SPI driver API does not say to do this, and my
original interpretation of the API was that the TX length controls the
entire transfer length, but this behavior might fit better with some de
facto expectations of in tree consumers.
Also add some robustness to the calculation of how many extra bytes to fill
when tx should be nops.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
This patch fixes transaction op items not performed within a single
SPI transfer. This is common for Write + Read commands, that depend on
the CS kept asserted until the end, otherwise the context will be lost.
A similar fix was applied to i2c_rtio_default on #79890.
Signed-off-by: Luis Ubieda <luisf@croxel.com>
Fixes a bug in nrfx spi when used in modes where only MOSI is needed such
as driving a WS2812. In this mode NRFX_ASSERT() is triggered when sck pin
is configured as no-connect.
Signed-off-by: Anthony Williams <anthony289478@gmail.com>
For the CPU-based drivers, delete the old MCUX based RTIO driver and use
the default RTIO submit implementation instead.
Rationale:
- 300 LOC -> 1 LOC to maintain.
- MCUX SDK based driver cannot control the chip select for the transfer
properly, but the new spi_nxp_lpspi.c driver can. So this fixes the
bug with the PCS when using RTIO.
Also enable the default RTIO implementation for DMA based driver.
In the future a DMA based RTIO driver with custom implementation can be
designed, but for CPU based transfer, which is already not optimal
performance, code maintenance is more important. Only requirement is
asynchronous submit, which is accomplished by p4wq in rtio workq.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
