Enable EOT interrupts after finishing filling the TxFIFO. Otherwise, the
interrupt can be triggered before the tx_len data is decremented, which
leads to a stall.
Also explicitly disable the EOT before starting the transfer.
It solves an issue seen on WBA with the spi_loopback test.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add helper functions for transfer size, FIFO-related interrupts, and
status flags so the SPI driver can use a common workflow across STM32
series. These new helpers are empty (or return 0) for non-H7 variants.
This allows removing a bunch of preprocessor guards, making the driver
code more easily readable.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Use the IS_ENABLED macro instead of #ifdef for CONFIG_SPI_STM32_INTERRUPT
when possible.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Rework FIFO handling for full- and half-duplex transfers to prevent
RxFIFO overruns. Read pending RX data before sending new TX data and
drain the RxFIFO at end of transfer.
Use explicit equality checks for each transfer direction to make the
FIFO handling workflow clearer.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
For H7-like devices, it is possible to set the SPI size transfer prior to
starting the communication. It is useful to increase performance,
especially when combined with the use of the FIFO threshold.
But this size is limited and can't be arbitrarily high (depending on SoCs
and SPI instances, it is typically either 65535 or 1023).
When the transfer size exceeds this limit, the driver now automatically
fallback to the unlimited transfer option instead of returning an error.
Although performance are inferior in this case, at least the transfer
takes place.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
For H7-devices in full-duplex master mode, seed one initial SPI frame at
transfer start instead of relying on the TXP flag only for the first
transfer. Now only DXP and EOT flag are used (in both polling and IT).
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
In the STM32 SPI driver, buffers in cache are not supported in DMA mode.
Instead of returning an error in such cases, fallback to interrupt or
polling mode so that the transfer still takes place.
Replace the error message by a warning.
Also move the asynchronous check after the cache one to avoid falling
back to polling mode while in asynchronous mode.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
- Add DMA support for SPI on RZ/A3UL since the previously supported
had not supported DMA.
Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
The slot argument from macros STM32_DT_INST_DMA_SLOT* was useless.
With it the macro was basically a redefinition a the Zephyr macro.
It is now removed to be similar to other STM32 DMA macros that call
DT_INST_DMAS_CELL_BY_NAME.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Typically Zephyr device tree macros that take a inst as argument
start with DT_INST_.
For the STM32 DMA driver we currently have several macros taking an inst as
argument but missing this prefix.
For consistency, it is added to these macros. The goal is to also define
DT_ variants of these macros that take a node_id as argument.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
When spi_context_wait_for_completion() times out, the SDK transfer
handle is left busy and every later transfer on the bus fails with
kStatus_ECSPI_Busy until reboot.
Abort the transfer and deassert the chip select on error so the bus
recovers, as spi_nrfx_spim already does on -ETIMEDOUT.
ECSPI_MasterTransferHandleIRQ() does not check the handle state, so a
completion interrupt latched just before the abort would still run the
callback, start the next word and signal the context again. Disarm the
callback with a flag before aborting, with interrupts locked so the ISR
cannot interleave with the abort, and clear the completion signal
(ctx.sync, or ctx.ready without CONFIG_MULTITHREADING) to drop a
completion that raced in before the flag was set.
Signed-off-by: Ryomei Osaki <o.ryomei1020@gmail.com>
The SDO pin (previously known as MOSI) of the STM32 SPI controller is
floating when the SPI is idle. As we use a pull-up on that pin (it is
used as a multi-function pin), this causes an idle-high voltage
on the SDO pin. We use the SDO pin for control of WS2812 LEDs, and they
require an idle-low voltage.
Add a devicetree setting 'st,gpio-control' so the SPI controller keeps
control of the SDO pin also between transmissions.
This enables the AFCNTR bit in the STM32 SPI controller, via the
LL_SPI_EnableGPIOControl() HAL function.
The functionality is available for SPI in STM32H7, STM32H5, STM32C5
and some other series: all that rely on "st,stm32h7-spi"
DT compatible ID.
Tested on STM32H562.
Signed-off-by: Jonas Berg <jonas.berg@voiapp.io>
Add an ifx_cat1_spi_deinit() implementation and register it via
SPI_DEVICE_DT_INST_DEINIT_DEFINE so device_deinit(dev) succeeds on the
Infineon PSE84 / CAT1 SCB SPI driver. Without this hook the upstream
tests/drivers/spi/spi_loopback test_spi_deinit case returns -ENOTSUP and
skips.
The deinit:
- returns -EBUSY while a transfer is still in flight, to avoid tearing
down the SCB block in the middle of a transaction. The busy check is
consolidated into ifx_cat1_spi_is_busy(), which reports busy while the
SPI context still holds outstanding tx/rx buffers
(spi_context_tx_on()/spi_context_rx_on()), while Cy_SCB_SPI_IsBusBusy()
is active, or while an async transfer is still pending. The large-chunk
DMA path drives the transfer purely through the DMA channels without
setting data->pending, and Cy_SCB_SPI_IsBusBusy() can read idle between
FIFO-paced DMA bursts, so the SPI context buffer state is used as the
authoritative in-flight indicator that covers both the FIFO and DMA
paths for synchronous and asynchronous transfers,
- unregisters the deep-sleep SysPm callback (only when CONFIG_PM=y),
- disables the SCB IRQ and the SCB SPI block (Cy_SCB_SPI_Disable),
- stops the rx and tx DMA channels via the shared ifx_cat1_spi_dma_stop()
helper, also used by ifx_cat1_spi_release() (only when
CONFIG_SPI_INFINEON_DMA=y),
- deinits the SCB SPI block last with Cy_SCB_SPI_DeInit(), then clears the
cached SPI config so the next transceive after device_init() takes the
full reconfigure path instead of being short-circuited by
spi_context_configured().
The DMA channels are stopped before the SCB is deinitialized so the SCB
teardown is the last hardware step, and the rx/tx dma_stop sequence is
factored into ifx_cat1_spi_dma_stop() rather than duplicated between the
deinit and release paths.
The deinit function and its reference in the device definition are
guarded by CONFIG_DEVICE_DEINIT_SUPPORT, matching the pattern used by
drivers/spi/spi_nrfx_spim.c and drivers/spi/spi_bflb.c.
Also drop the unused dma_configured field from struct ifx_cat1_spi_data:
it was never read and never set to true anywhere in the driver.
Verified on kit_pse84_eval/pse846gps2dbzc4a/m55:
- [spi_loopback.test_spi_deinit] PASS
- [spi_loopback.test_spi_deinit_busy] PASS (device_deinit() returns
-EBUSY while an 8192-byte DMA transfer is in flight, then succeeds
and re-inits once the bus is idle)
Assisted-by: AI (GitHub Copilot)
Signed-off-by: Bill Waters <bill.waters@infineon.com>
This commit enables the new clock managers by switching the device
tree to use the new bindings. It also moves some initialization code
from the old clock manager to soc_early_init_hook() since some clocks
configuration needs to be done before the clock drivers are initialized.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
The driver rejects peripheral mode with SPI_OP_MODE_SLAVE, which is
marked __DEPRECATED_MACRO and so makes the build fail under -Werror.
Use SPI_OP_MODE_PERIPHERAL instead and reword the log message to match
the controller/peripheral terminology the other SPI drivers use.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:opus-5
- Add CONFIG_SPI_RENESAS_RA_SCI_B_DMAC configuration option
- Add device tree properties for DTC (rx-dtc, tx-dtc)
- Support both DTC/DMAC transfer with shared transfer infrastructure
- Add tx-dtc and rx-dtc properties to device tree binding
- Add DMAC configurations, interrupt and callback declarations
Signed-off-by: Khai Cao <khai.cao.xk@renesas.com>
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
- Add CONFIG_SPI_B_DMAC configuration option
- Support both DTC/DMAC transfer with shared transfer infrastructure
- Add DMAC configurations, interrupt and callback declarations
Signed-off-by: Khai Cao <khai.cao.xk@renesas.com>
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
Connect every SERCOM interrupt line the devicetree node declares via
LISTIFY(DT_INST_NUM_IRQS), instead of a fixed index 0-3 subset
Signed-off-by: Mohamed Azhar <mohamed.azhar@microchip.com>
Add a driver for the VIRTIO SPI controller device (virtio spec 1.4,
section 5.21), letting a Zephyr guest drive a SPI bus exposed by a
hypervisor or a vhost-user backend.
The device carries a single transfer per request, so a transceive call
is split into one request per contiguous chunk of the buffer sets, with
cs_change holding the chip select asserted in between. The controller
capabilities are read from the device configuration space at init and
checked against the SPI configuration. Every request is a round trip to
the device, so the SPI API can only be used from a thread.
Assisted-by: Claude Code:opus-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
DMA is only supported for full-duplex controller mode. Add an error
message and return an error if DMA is asked while in peripheral mode
or in half-duplex.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
In non-H7 full-duplex controller mode, using independent TXE/RXNE
handling in interrupt context can trigger RX overruns.
Switch this path to an RXNE-driven pipeline: seed one initial TX frame
at transfer start, then in each RXNE ISR read one frame and queue the
next TX frame. After the last TX frame, re-enable TXE once so transfer
completion is still detected when BSY clears.
Keep H7 behavior unchanged, and keep the existing non-full-duplex logic
unchanged.
This avoids ISR busy-wait loops while maintaining TX/RX synchronization
on non-H7 full-duplex transfers.
Assisted-by: GitHub Copilot:GPT-5.3-Codex
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
For the SPI devices with st,stm32-spi-fifo compatible, when configured
as master in half duplex RX mode, the clock is output non-stop on the
SCK line (the clock can't be started explicitly by filling the TX FIFO
since we're in half duplex RX), and the device has no way to know when to
stop (there is no TSIZE-like register like on st,stm32h7-spi compatible).
So, to prevent reception of unwanted extra data, the SPI must be disabled
as soon as all data have been received.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add support of half duplex transfers on peripheral side.
This adds the support for all STM32.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Introduce polling-based SPI driver for the NXP Kinetis-L series.
The driver implements spi_context and utilizes standard Zephyr
Clock Control and Pinctrl subsystems.
Signed-off-by: Gabriel Ivo <gabriel.bozi@usp.br>
Now that all in-tree users have been migrated to the inclusive SPI
terminology, formally deprecate the old names:
- SPI_OP_MODE_MASTER, SPI_OP_MODE_SLAVE and the SPI_MOSI_OVERRUN_*
compatibility aliases now emit a deprecation warning through
__DEPRECATED_MACRO.
- The "slave" member of struct spi_config and the
spi_context_is_slave() compatibility wrapper are marked
__deprecated.
- The SPI_CTX_RUNTIME_OP_MODE_MASTER/SLAVE aliases now emit a
deprecation warning through __DEPRECATED_MACRO.
- The SPI_SLAVE Kconfig shim now selects DEPRECATED.
Document the renames in the v4.5 migration guide and release notes.
Per the API lifecycle policy the deprecated names are kept for two
releases, and are scheduled for removal in Zephyr v5.0.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Use controller/peripheral terminology in the Realtek RTS5817 SPI
driver, following coding guideline rule A.2: switch to the renamed
core symbols and update comments, log messages and Kconfig help
prose.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Use controller/peripheral and SDO/SDI terminology in the remaining
SPI drivers, following coding guideline rule A.2. These changes are
limited to uses of the renamed core symbols (SPI_OP_MODE_CONTROLLER/
PERIPHERAL, spi_config.peripheral, spi_context_is_peripheral(),
SPI_SDO_OVERRUN_DT), driver-local identifiers (e.g. the silabs
mosi_overrun config members renamed to sdo_overrun), comments and
log messages. The Kconfig.renesas_ra8 hardware chip-select prompt
and help prose are reworded as well.
Vendor HAL/SDK and datasheet register identifiers keep their names,
notably: Ambiq IOSLAVE* base macros, Telink spi_master_* HAL calls,
TI driverlib SSI_MODE_MASTER, GD32 SPI_MASTER register bit, Nuvoton
BSP SPI_MASTER/SPI_SLAVE/QSPI_*/USPI_MASTER/SPI_CTL_SLAVE_Msk,
Microchip MSS_QSPI_CONTROL_MASTER and XEC CHPA_MOSI/CHPA_MISO
register bits, Silabs emlib EUSART/USART init symbols, and the
Zephyr PCIe core PCIE_CONF_CMDSTAT_MASTER bus-master bit referenced
by spi_pw.c (out of scope for this migration).
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Use controller/peripheral terminology in the Infineon CAT1 (PDL and
HAL based), PSoC-6 and XMC4xxx SPI drivers, following coding
guideline rule A.2: switch to the renamed core symbols, rename
driver-local identifiers (is_slave, spi_psoc6_master_get_defaults),
and update comments and log messages.
All Cypress/Infineon PDL identifiers (CY_SCB_SPI_MASTER/SLAVE,
Cy_SCB_*Master* APIs, enableMisoLateSample, masterSlaveIntEnableMask)
keep their vendor names, along with the devicetree property tokens
that mirror them (enable-miso-late-sample,
master-slave-int-enable-mask, miso-src).
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Use controller/peripheral terminology in the NXP MCUX SPI drivers
(flexcomm, dspi, ecspi, flexio, rv32m1 lpspi and nxp lpspi),
following coding guideline rule A.2: switch to the renamed core
symbols, rename driver-local callbacks, helpers and variables
(spi_mcux_master_transfer_callback, spi_flexio_master_init,
lpspi_master_setup_native_cs, master_config/slave_config locals),
and update comments and log messages.
All NXP MCUX SDK API names, types and enum flags (SPI_Master*,
DSPI_Master*, kDSPI_*, ECSPI_*, FLEXIO_SPI_Master*, LPSPI_Master*,
*_master_config_t, *_master_handle_t, enableMaster) and CMSIS
register field macros (LPSPI_CFGR1_MASTER_MASK, *_MASTER_PCS_SHIFT)
keep their vendor names.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Use controller/peripheral terminology in the Nordic nrfx SPI/SPIM/
SPIS shim drivers, following coding guideline rule A.2: switch to the
renamed core symbols, make SPI_NRFX_SPIS select SPI_PERIPHERAL
instead of the deprecated SPI_SLAVE, and reword Kconfig prose,
comments and log messages.
The nrfx HAL API names keep their vendor names.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Use controller/peripheral terminology in the ESP32 SPI driver,
following coding guideline rule A.2: switch to the renamed core
symbols, make ESP32_SPI_TARGET select SPI_PERIPHERAL instead of the
deprecated SPI_SLAVE, reword the Kconfig prompt/help, and update
comments.
All ESP-IDF HAL names (spi_slave_hal_* API and types,
hal/spi_slave_hal.h, SPI_MASTER_FREQ_* macros) keep their vendor
names.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Use controller/peripheral terminology in the TI OMAP MCSPI driver,
following coding guideline rule A.2: switch to the renamed core
symbols and the CONFIG_SPI_PERIPHERAL guard, and update comments and
log messages.
The ti,d1-miso-d0-mosi devicetree property and its matching code
tokens keep their names, as the property is defined by the TI binding
and mirrors the TI TRM signal naming.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Use controller/peripheral terminology in the ITE IT8xxx2 SPI driver,
following coding guideline rule A.2: switch to the renamed core
symbols and update log messages.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Use controller/peripheral terminology in the ITE IT51xxx SPI driver,
following coding guideline rule A.2: switch to the renamed core
symbols and update log messages.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Use controller/peripheral terminology in the Xilinx AXI Quad SPI
driver, following coding guideline rule A.2: switch to the renamed
core symbols and the CONFIG_SPI_PERIPHERAL guard, and update comments
and log messages.
The SPICR_MASTER*, SPISR_SLAVE_* and IPIXR_SLAVE_* register bit
macros mirror the Xilinx PG153 datasheet register field names and
keep their names.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Use controller/peripheral terminology in the STM32 SPI driver,
following coding guideline rule A.2: rename the Zephyr-owned
ll_spi_swap_mosi_miso() wrapper to ll_spi_swap_sdo_sdi(), rename
local variables, switch to the renamed core symbols and the
CONFIG_SPI_PERIPHERAL guard, and update comments, log messages and
Kconfig help prose.
All ST LL/HAL API names (LL_SPI_MODE_MASTER/SLAVE,
LL_SPI_StartMasterTransfer, LL_SPI_EnableMosiMisoSwap,
LL_SPI_SetMasterSSIdleness, ...) keep their vendor names, and the
verbatim errata sheet quote in Kconfig.stm32 is left intact.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Use controller/peripheral terminology in the LiteX SPI and LiteSPI
drivers, following coding guideline rule A.2: switch to the renamed
core symbols and update comments and log messages.
All master_*/mosi_*/miso_* identifiers tied to LiteX
gateware-generated CSR register names or devicetree reg-names
(master_cs, master_rxtx, master_phyconfig, master_status,
master_ev_*, master_clk_divisor, SPIFLASH_MASTER_*, reg-names
"mosi"/"miso") keep their names, as they must match the LiteX
gateware and devicetree definitions.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Use controller/peripheral terminology in the Microchip PolarFire MSS
SPI driver, following coding guideline rule A.2: rename the
driver-local mss_spi_select_slave() helper and the
MSS_SPI_MIN/MAX_SLAVE bounds macros, switch to the renamed core
symbols, and update comments.
The MSS_SPI_CONTROL_MASTER register bit macro mirrors the PolarFire
MSS SPI datasheet and keeps its name.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Use controller/peripheral terminology in the ADI MAX32 SPI driver,
following coding guideline rule A.2: rename driver-local variables,
switch to the renamed core symbols and the CONFIG_SPI_PERIPHERAL
guard, and update comments.
The MXC_SPI_SetSlave() HAL function and the
ADI_MAX32_SPI_CTRL_MASTER_MODE register bit macro come from the ADI
MSDK and keep their names.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Use controller/peripheral terminology in the Bouffalo Lab SPI driver,
following coding guideline rule A.2: rename the driver-local
spi_bflb_trigger_master()/spi_bflb_detrigger_master() helpers, switch
to the renamed core symbols, and update comments.
The GLB_REG_SPI_*_MASTER_MODE_POS register field macros come from the
Bouffalo Lab HAL and keep their names.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Use controller/peripheral terminology in the Atmel SAM0 SERCOM SPI
driver, following coding guideline rule A.2: rename
spi_sam0_shift_master() to spi_sam0_shift_controller(), switch to the
renamed core symbols, and update comments.
The SERCOM_SPI_CTRLA_MODE_SPI_MASTER_Val register field value macro
mirrors the Microchip SERCOM header and keeps its name.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Use controller/peripheral terminology in the Microchip FLEXCOM G1 SPI
driver, following coding guideline rule A.2: rename the driver-local
helpers spi_slave_to_mr_pcs() and spi_sam_shift_master(), switch to
the renamed core symbols, and update comments and log messages.
The SPI_MR_MSTR_Msk register field macro comes from the Microchip SoC
header and keeps its name.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Use controller/peripheral terminology in the Atmel SAM SPI driver,
following coding guideline rule A.2: rename the driver-local helpers
spi_slave_to_mr_pcs() and spi_sam_shift_master(), switch to the
renamed core symbols, and update comments and log messages.
The Atmel SPI_MR/SPI_CSR register field macros keep their vendor
names.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Use controller/peripheral terminology in the Renesas RZ SPI and RSPI
drivers, following coding guideline rule A.2: switch to the renamed
core symbols and the CONFIG_SPI_PERIPHERAL guard, and update comments
and log messages.
Renesas FSP identifiers (SPI_MODE_MASTER/SLAVE, mosi_idle,
*_MOSI_IDLE_VALUE_FIXING_DISABLE, BSP_FEATURE_BSP_MASTER_MPU_*) keep
their names, and the RZ_MASTER_MPU_* macros and related comments keep
theirs as they designate the Renesas RZ "Master MPU" bus-master
hardware block.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Use controller/peripheral terminology in the Renesas RX RSPI driver,
following coding guideline rule A.2: rename the driver-internal
transceive helpers, switch to the renamed core symbols and the
CONFIG_SPI_PERIPHERAL guard, update comments, and reword the
hardware chip-select Kconfig prompt and help text.
The rspi_chnl_settings_t.master_slave_mode member, the
RSPI_MS_MODE_MASTER/SLAVE enum constants (Renesas RDP r_rspi_rx_if.h)
and the SPCR.MSTR register bit field (iodefine.h) come from the
vendor HAL/datasheet and keep their names.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Use controller/peripheral terminology in the Renesas RA8 SPI-B
driver, following coding guideline rule A.2: rename the
driver-internal transceive helpers, switch to the renamed core
symbols and the CONFIG_SPI_PERIPHERAL guard.
The SPI_MODE_MASTER/SPI_MODE_SLAVE operating mode constants come from
the Renesas FSP HAL and keep their names.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Use controller/peripheral terminology in the Renesas RA SCI-B SPI
driver, following coding guideline rule A.2: switch to the renamed
core symbols and the CONFIG_SPI_PERIPHERAL guard, and update comments
and log messages.
The SPI_MODE_MASTER/SPI_MODE_SLAVE operating mode constants come from
the Renesas FSP HAL and keep their names.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Use controller/peripheral terminology in the Renesas RA SCI SPI
driver, following coding guideline rule A.2: switch to the renamed
core symbols and the CONFIG_SPI_PERIPHERAL guard, and update comments
and log messages.
The SPI_MODE_MASTER/SPI_MODE_SLAVE operating mode constants come from
the Renesas FSP HAL and keep their names.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
