Switch the Cadence SPI driver to use the DEVICE_MMIO API instead
of directly accessing the physical base address from the devicetree.
This is required to support platforms with an active MMU (such as the
Cortex-A9 on Zynq 7000), where accessing unmapped physical addresses
causes MMU translation faults.
Closes#113693
Signed-off-by: Simon Maurer <mail@maurer.systems>
The 16-bit branch of spi_gd32_frame_exchange() read the TX buffer
through a uint8_t pointer, copied from the 8-bit branch, so the high
byte of every 16-bit frame was transmitted as zero. Read a full
16-bit word, matching the RX side.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Some SPI devices need the CS pin to be deasserted between multiple
transceive calls (e.g. the Microchip LAN8651). The MCSPI driver didn't do
this until now and kept the CS pin asserted for hardware controlled CS
pins, except if the channel changed.
This has been changed and additionally during init the GPIO pins are now
also being initialized.
Signed-off-by: Mika Braunschweig <mika.braunschweig@siemens.com>
Header file include/zephyr/sys_clock.h is deprecated and will be removed
someday. Update the whole file tree to include zephyr/sys/clock.h
straight instead of zephyr/sys_clock.h.
This change was made running the sed shell command below:
$ sed -i 's/zephyr\/sys_clock\.h/zephyr\/sys\/clock\.h/' \
`grep -rsl "zephyr/sys_clock\.h" drivers/`
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
lpspi_end_xfer() only clears TCR CONT/CONTC when SPI_HOLD_ON_CS is
absent from the transfer's config, so that consecutive
spi_transceive() calls within a HOLD_ON_CS transaction keep native
(non-GPIO) CS asserted between transfers, as intended.
However, once the caller finishes the whole transaction and calls
spi_release(), those bits were never cleared, leaving native CS
asserted indefinitely - spi_context_unlock_unconditionally() already
force-releases GPIO-based CS via _spi_context_cs_control(ctx, false,
true), but has no way to know about the LPSPI-specific TCR bits for
native CS.
Clear TCR CONT/CONTC directly in spi_lpspi_release() so that
spi_release() actually deasserts native CS as its API contract
implies, matching the existing GPIO CS behavior.
Confirmed on real hardware (FRDM-MCXN947, LPSPI1 native PCS0): CS
previously stayed low indefinitely after the first HOLD_ON_CS
transaction (as used by the Arduino SPI API, which always sets
SPI_HOLD_ON_CS to support multiple transfer() calls per transaction);
with this fix CS correctly returns high after each endTransaction().
Signed-off-by: Tedd OKANO <okano.akifumi@gmail.com>
Updated spi_xec_qmspi_ldma driver with low power support.
Add a pm_action handler that clears MODE.ACTV and applies the
pinctrl sleep state on suspend, and reverses both on resume.
Hold a PM_STATE_SUSPEND_TO_IDLE policy lock for the duration of
each transfer (sync and async) so suspend cannot enter mid-
transaction.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
Let's avoid a build warning/error in the spim interrupt handler mapping,
by being explicit about passing to it as parameter the address of
`nrfx_spim_t spim` data instead of knowing implicitly that it is the first
element of `struct driver_data`.
This avoid the following build warning/error:
nfx_spim.h:472:42: note: expected 'nrfx_spim_t *' but argument is of
type 'struct driver_data *'
Issue introduced in:
6f2829ea0c
Can be reproduced building
tests/arch/arm/arm_irq_vector_table for thingy53/nrf5340/cpuapp
with CONFIG_SPI_RTIO=y
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Let's avoid a build warning/error in the spim interrupt handler mapping,
by being explicit about passing to it as parameter the address of
`nrfx_spim_t spim` data instead of knowing implicitly that it is the first
element of `struct driver_data`.
This avoid the following build warning/error:
nrfx_spim.h:472:42: note: expected 'nrfx_spim_t *' but argument is of
type 'struct driver_data *'
Issue introduced in:
e4d61fc472
Can be reproduced building
tests/arch/arm/arm_irq_vector_table for thingy53/nrf5340/cpuapp
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
The last TX word must be written to FIFOWR as a full 32-bit write to
properly set the EOT (end-of-transfer) control bit at bit 20. Commit
7cb3fca changed the DMA block_size for the last word from
sizeof(uint32_t) to data->word_size_bytes, which meant only the lower
data bytes were transferred, missing the EOT flag entirely.
The issue #107484 mentions that this will cause the last
transfer to be incorrect width, but deep down in the NXP dma driver
there is a fix for this. See dma_mcux_lpc.c (line 262-273).
Fixes: #107484
Signed-off-by: Lars Jeppesen <lje@foss.dk>
The async completion path handed the driver data pointer to
spi_smartbond_pm_policy_state_lock_put(), which expects the device and
forwards it to pm_device_runtime_put(). Pass dev, as every other call
site does.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
The driver reads the rate of the configured clock source and
calculates the timing divider against it, but never programs
the hardware mux that selects that source. The mux keeps its
reset value, so the peripheral runs from XTAL while the
divider assumes a PLL rate.
On esp32p4 the default source is the 480 MHz SPLL and the
reset value selects the 40 MHz XTAL, making every transfer 12
times slower than requested: a 1 MHz request measures 83 kHz.
Program the mux at init so it matches the rate the divider is
calculated from.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The syscall handler functions forward parameters with identical casts
that are redundant since the variables already have those types. Drop
the casts to let the compiler type-check the arguments unobstructed.
Signed-off-by: Flavio Ceolin <flavio@hubble.com>
On USCI the shallow buffer is not SPI FIFO buffers RX words.
The pipelined pattern can't work. So revised spi_numaker_usci_txrx.
More, USCI SPI only supports 4–16 bit words, not accepts 24/32.
Signed-off-by: cyliang tw <cyliang@nuvoton.com>
The siwx91x SPI driver required to wait for a very small amouth of time
(100ns to 50µs).
When CONFIG_PM is enabled, the granularity of k_busy_wait() is not
sufficient (~32µs). So, the driver implement a raw busy loop.
This busy loop depends on the frequency of the CPU. This was wrongly
retrieved from CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC.
DT_PROP(DT_NODELABEL(cpu0), clock_frequency) is more accurate.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
When the SPI hardware block is use to send data (without receiving any
data), the DMA callback is called when the data are transmitted to the SPI
controller, but before the data are actually sent over the wire.
Then, the chip-select signal could be released while the Tx was still in
progress.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
The SPI_STM32_BUSY_FLAG_TIMEOUT option had no help text, leaving
users with no explanation of its purpose when browsing menuconfig. Add
a description that documents how long the driver polls for the BSY flag
to clear after a DMA transfer on STM32F7 and STM32L4 devices affected
by the busy-flag errata.
Assisted-by: OpenAI Codex:gpt-5
Signed-off-by: Collins Culbert <coculbert@icloud.com>
Use <> operator to include a Zephyr header file instead of "" that
is intended to local header files, not header files relative to
specifically defined search paths.
This change was made running the sed shell command below:
$ sed -i -E 's/#include "zephyr\/([^"]+)\.h"/#include <zephyr\/\1.h>/g' \
`grep -rsl "#include \"zephyr/" drivers/`
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
This commit deploys a workaround for errata 2.21.3 from ES0491 (and similar
for other H7 SoCs).
This prevent the SPI interrupt to fire when SPI is disabled, by disabling
the EOT and TXP interrupt before disabling the SPI.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
The NXP ECSPI represents clock polarity with two separate fields:
channelConfig.polarity (SCLK_POL), the active polarity, and
channelConfig.clockInactiveState (SCLK_CTL), the level SCLK idles at
between bursts. spi_mcux_configure() set polarity from the CPOL bit but
left clockInactiveState at the kECSPI_ClockInactiveStateLow default
applied by ECSPI_MasterGetDefaultConfig().
As a result, transfers to CPOL=1 devices (SPI modes 2 and 3) ran with an
inconsistent clock: the active polarity was inverted as requested while
the idle SCLK level stayed low. Drive clockInactiveState from the same
CPOL bit so the idle level matches the configured mode.
Signed-off-by: Marvin Gnad <marvin.gnad@gmail.com>
When a SPI device uses a GPIO chip select, spi_mcux_configure() initialises
the controller on ECSPI channel 0. However spi_mcux_transfer_next_packet()
started every transfer on transfer.channel = ctx->config->slave.
A device with reg != 0 transfers on an ECSPI channel that was never
configured.
Select the transfer channel the same way spi_mcux_configure() already does:
channel 0 when the chip select is a GPIO, and the slave number only for
native chip selects.
Signed-off-by: Marvin Gnad <marvin.gnad@gmail.com>
Check that the buffer length is a multiple of the data size, and return
an error if it's not the case.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Do not store stack-allocated pointers in the SPI data structure.
Set current_tx and current_rx to NULL since they are not used in RTIO
anyway.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Adapt the STM32 SPI driver so that in RTIO, transactions can be done either
in interrupt or in DMA mode, for different instances (until now, once
CONFIG_SPI_STM32_DMA was enabled, all transactions had to be done with
DMA).
Also use the asynchronous DMA callback for RTIO since it shares a lot of
code.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
The transceive and transceive_dma functions had some similar code.
Factorize them to reduce code duplication. transceive_dma is now called
from the transceive function, and only the latter is called from the
.transceive and .transceive_async API functions.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
This commit fixes issues that could arise notably when only the slave was
sending data (and the master was only receiving). By keeping track of bytes
transmitted in both directions (the context may not keep track of a
direction if the associated buffer is NULL or the length is 0), we prevent
the master side to abort the transmission prematurely.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Fixes the slave mode for st,stm32h7-spi compatibles by setting the
transfer size also for the slave device, and also waiting for SPI to not be
busy before calling the "complete" function (or else the transaction might
end too early in case where only the slave sends data).
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
The SAM SPI peripheral natively supports 8-16 bit word sizes via
the SPI_CSR.BITS field, but the driver rejects anything other than
8-bit with -ENOTSUP.
Remove the 8-bit-only restriction and map word_size to the BITS
field. Add 16-bit-wide fast-path transfer functions (TX, RX, TXRX)
for word sizes > 8, where each word occupies a uint16_t in the
buffer. The spi_sam_fast_{tx,rx,txrx} wrappers added in the
previous commit now dispatch to the 8-bit or 16-bit variant based
on the configured word size.
This enables MIPI DBI Type C (3-wire 9-bit SPI) displays and other
peripherals that require non-8-bit word sizes on SAM MCUs.
Tested on SAM4S with a 9-bit SPI display (ILI9806 via MIPI DBI).
Signed-off-by: Ričards Poriņš <ricards.porins@gmail.com>
Rename spi_sam_fast_{tx,rx,txrx} to *_8 to make the 8-bit nature
explicit, and introduce thin wrappers with the original names that
take a device handle and delegate to the _8 variant. Update the
callers in spi_sam_{tx,rx,txrx} to pass the device handle through.
This is a pure refactor with no functional change; it sets up the
follow-up patch that adds 9-16 bit word size support by dispatching
to a 16-bit variant inside the wrapper.
Signed-off-by: Ričards Poriņš <ricards.porins@gmail.com>
The SPI SCK pin needs to be initialized to match the current SPI
transfer CPOL setting. The SPIM peripheral is enabled after CS is
toggled, thus all pins need to be configured to drive correct
initial state using gpio. Since the SCK pin is defined in pinctrl
rather than as a gpio pin, nrfy is used to get the pin number and
set the pin rather than gpio peripheral driver.
Without this addition, CPOL=1 may cause an incorrect clock to be
registered at the start of the transfer, shifting the data 1 bit.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Add target (peripheral) mode to the Espressif SPI driver. The scattered
transfer buffers are coalesced into one FIFO transfer and the received
data is scattered back on completion. Socs with the integrated SPI-DMA
use DMA, as their CPU/FIFO slave path drops the final received byte.
Also fix the controller chip-select hold to track the remaining length
so trailing zero-length buffers no longer keep the line asserted.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
To avoid MXC_SPI_Shutdown having an invalid state (for DMA channels,
specifically), add a call to initialize the internal state of the SPI
driver before calling shutdown. This avoids a bug with DMA channels being
released that shouldn't be by shutdown.
Signed-off-by: Pete Johanson <pete.johanson@analog.com>
Pull the code for checking if a given peripheral has DMA channels assigned
into a shared inline function.
Signed-off-by: Pete Johanson <pete.johanson@analog.com>
To avoid accidentally sending bogus data placed into the dummy buffer
during an RX, use dedicated two-byte buffers for TX/RX each.
Signed-off-by: Pete Johanson <pete.johanson@analog.com>
Add support for target mode for the MAX32 SPI peripheral, including testing
support for the APARD32690 board.
Signed-off-by: Pete Johanson <pete.johanson@analog.com>
Fixes for properly setting half duplex mode for the SPI peripheral, and
handle fifo/interrupts properly for that mode of operation.
Signed-off-by: Pete Johanson <pete.johanson@analog.com>
CACHE_MANAGEMENT depends on DCACHE,
therfore we should also only select it, if it is
enabled and not just if the cache exists, as the
user could disable DCACHE and then there
would be a problem.
DCACHE btw depends on CPU_HAS_DCACHE
and is enabled by default.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
This reverts commit 8c2a903829.
Chunk transfers are now handled in spi_nrfx_spim_common.c to support
both DMM, RAM and EasyDMA limits for spim and spim_rtio drivers.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
The nrfx_spim drivers need to handle transfers larger than the
internal buffers and DMA capabilities by splitting them into chunks.
Additionally, DMM and RAM buffers are mutually exclusive.
Update the common code to split the transfer internally, and update
the event callback to include the result of the transfer, since the
transfer can now fail. Update the spim and spim_rtio drivers to use
the new callback. Add new kconfig for DMM chunk size and update both
common code and kconfig to make it clear DMM and RAM buf are mutually
exclusive.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Add build assert which validates that memory region has been defined
for SPIM instance if HAS_NORDIC_DMM is enabled.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Since nordic DMM has been introduced, the SPIM RAM buffer is no
longer used in case DMM is enabled. Before DMM the SPIM RAM buffer
was manually placed in the DMM linker section, now the driver
allocates a buffer from the DMM linker section dynamically instead.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
- Kconfigs in modules/ should not define configs with an SOC_ prefix.
Furthermore, these options are SDK specific, not SoC specific.
- The simplicity_sdk configs do the same.
Signed-off-by: Michael Zimmermann <michael.zimmermann@sevenlab.de>
For STM32H7, disable IRQ in RTIO when tranfer is completed to prevent
spurious IRQ to stall the system.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
For st,stm32h7-spi compatible, always use the TSIZE register and the FIFO
for polling and interrupt mode. This increases performance compared to not
using it, and it reduces code complexity. This removes the need for the
fifo-enable property.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
For st,stm32h7-spi compatibles, when fifo-enable property is set, the
driver was setting the TSIZE register with the size of each buffer in the
transaction, leading to several disable/enable of the SPI instance.
Now, it sets the complete size of the transaction without intempestive
disabling of the SPI.
To add flexibility, the FIFO threshold is now configurable from a dts
property.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
