The current implementation checking for the validity of the spi slave
number is wrong. First of all, there is an off by one error where it
allows SPI_CHIP_SELECT_COUNT value as a valid slave, when really it
should be that value minus one. Secondly, it doesn't take into account
the fact that having software controlled GPIO CS can technically have
any number of slaves on the bus. So fix by finding the max of these two
values and fixing the off by one mistake. Also, for RW612, only one HW
native CS is available due to SOC pinmux limitations.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The version register is not accessible through aux-reg interface,
So skip it entirely on platforms with aux-reg device tree property.
Signed-off-by: Mohamed Moawad <moawad@synopsys.com>
Because of limitation of gpdma, DMA Rx won't run if user doesn't specify
destination buffer.
Thus, the DMA Rx may stop before the end of the full transaction. So, wait
on DMA Tx instead.
Then, the SPI data won't be consumed by the DMA. We need to properly reset
the fifo before to start a new transaction (it is better to ensure we start
with a clean state before every transaction).
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
For all STM32 drivers and SoC, replace the READ_REG macro and the
LL_xxx_ReadReg functions (defined in the STM32 HAL) by
stm32_reg_read defined in Zephyr.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
This commit enhances the SPI shell in a number of different ways:
- Previously only spi buses could be specified in the shell.
Now both spi buses and spi devices (physical device on the spi bus,
not the device struct) can be specified.
- Both spi buses and spi devices can be specified by their node name or
by any of their node labels.
- Instead of having a single instance of a spi config struct, each spi
bus/device has it's own dedicated config. This means that
users only have to configure spi config once for each device and use
them freely, without needing to reconfigure them every time after
switching between different spi buses/devices.
- Spi devices get their spi configs automatically from the devicetree at
compile time. This means that once a good working configuration is
found for a spi device, that can be specified as a "default" in the
devicetree.
- Spi devices don't need to have their status set to "okay" or be
initialized by their driver to be accessible from the spi shell. As
long as the spi bus that they are on has status="okay", they can
be accessed.
- When changing a cs pin with spi cs command, the spi device/bus
needs to first be specified before specifying the gpio device.
The nested dynamic subcommands enable users to autocomplete both
of the arguments.
Implementation details
- It was possible to gather all the information about the spi devices
from the devicetree at the compile time, but not for the spi buses.
For the spi devices we have a way to get spi device nodes that are
on an okay spi bus with a devicetree macros and extract data from
those nodes. For the spi buses that is not possible,
since there is no macro to get all spi bus nodes at once.
- So, for the spi buses this discovery step has to be done at the
runtime, with the help of SYS_INIT macro and shell_device_filter
function.
- Since we now allow users to either specify a spi bus or a spi device
by their node label or their node name, we needed to have a way to map
those strings to the correct spi config struct, so we can later pass
it to the spi API functions or do some configuration on it. That is
made possibly by the find_spec_by_label and the two arrays,
spi_things and maps.
Signed-off-by: Marko Sagadin <marko.sagadin42@gmail.com>
Remove the handling of cross domain pins from nrf drivers. To use
cross domain in tests, force on constlat and disable power domains
for the test.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
This patch fixes an issue in the SPI driver that caused the chip select
line to remain low after a transaction completed (when using a GPIO and
operating in non-interrupt mode).
Signed-off-by: Ian Morris <ian.d.morris@outlook.com>
Silabs siwx91x offer two DMA hardware block: GPDMA and UDMA.
While UDMA has some benefit when running in low power modes, GPDMA offer
better performances. So GDMA is probably better suited for SPI device.
Ideally, we would like to leave the ability to switch back to UDMA.
Unfortunately, UDMA and GPDMA are not configured in the same way:
- the maximum length of the block are different (1024 or 2048 for UDMA
and 4096 for GPDMA)
- the burst length is different
So, we only support GPDMA.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Since various macros don't end with a colon, the code formatters give bad
results. Let's fix that.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
The siwx91x platform provides two DMA block: UDMA and GPDMA. GPDMA require
the dma_slot attribute.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Replace a #ifndef directive with a if(!IS_ENABLED()) instrcution
in transceive() function. This change makes later integration of RTIO
support in this function smoother, polluting a bit less this function
with #if based directives.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Fix a missing braces pair around a conditioned instruction in
STM32 SPI driver. Fix that by aggregating the 2 if() instructions
into a single ANDed one.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Correct some indentation issues, a few useless line escapes,
double space characters or parentheses pair in STM32 SPI driver.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Remove bits2byte() helper function than was not always used. Replace it
with a division by BITS_PER_BYTE that is explicit enough.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Reorder inclusions of header files to clarify and simplify later changes.
By the way, remove #ifdef CONFIG_SPI_STM32_DMA condition to include
DMA header files as its not required.
Keep zephyr/log.h with use of LOG_MODULE_REGISTER() first since included
local spi_context.h depends on log resources to be defined.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Remove inclusion of zephyr_arch/cache.h header file from STM32 SPI
driver. This header file is included by zephyr/cache.h if applicable
(e.g. CONFIG_ARCH_CACHE is enabled) and should not be used when
CONFIG_EXTERNAL_CACHE is enabled.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Move some code into a new function to prepare for RTIO integration.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Clocks are requested automatically by hardware on the nRF54H.
Remove additional handling from device drivers, and disable
the now unmanaged clocks in the devicetree.
Updates:
- can_nrf
- counter_nrfx_timer
- uart_nrfx_uarte
- spi_nrfx_spim
- spi_nrfx_spis
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
When performing polling-based data transfer without enabling interrupts,
the current implementation stops transferring as soon as either the TX or
RX buffer becomes NULL. This causes the transfer to stop prematurely,
even if the other direction still has data to send or receive.
This commit fixes the condition so that data transfer continues
as long as one direction (TX or RX) still has data remaining.
Signed-off-by: Khoa Tran <khoa.tran.yj@bp.renesas.com>
Add SPI driver support for Renesas RZN2L, T2M
Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
The Kconfig symbols for selecting HAL content should be part
of the HAL module integration, not defined by the SoC. Split the
symbols between the Series 0/1 Gecko HAL and Series 2 SiSDK HAL
when moving them.
For now, the Series 0/1 HAL symbols retain their name, while new
names consistent with the symbols already defined in the module
integration layer are used for the Series 2 HAL.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Fix QSPI and half duplex
Support hold on CS flag
Create functions to assert and deassert CS
Signed-off-by: Benjamin Santon <benjamin.santon@analog.com>
In case of hardware controlled CS pins the SPI context must be
initialized after the clock and pin control have been initialized.
Otherwise, corresponding STM32 LL operations would access a SoC
functional unit that is not yet supplied with a clock and fail
silently without error handling.
Signed-off-by: Stephan Linz <linz@li-pro.net>
Add PM support to cc23x0 SPI module. This implies listing states which
cause power loss and enabling device runtime PM for the DMA in the DT.
Signed-off-by: Julien Panis <jpanis@baylibre.com>
Add a miniscule delay to ensure the MAX32 SPI config is applied and active
before returning and initiating any transactions.
Signed-off-by: Pete Johanson <pete.johanson@analog.com>
A race condition occurs when the TX DMA callback is triggered before
the `dma_stat` variable is initialized to zero. This leads to
`dma_stat` being reset after the DMA TX done flag is already set.
To prevent this, move the initialization of `dma_stat` before starting
the DMA load operation.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
Without this check, `spi_context_unlock_unconditionally()` is capable
to release the SPI bus semaphore (ctx->lock) which might be taken by
another SPI slave device in the meantime.
Actually, this race condition happens when `spi_release()` is called
when the SPI slave device in question (spi_cfg) has already released
its chip select and also the SPI bus lock semaphore.
So, any not required call of `spi_release()` may result in a SPI
communication issue where the SPI bus lock, held by another SPI
slave device, is prematurely released.
The observable result is the simultaneous engagement of two SPI
chip selects after such an SPI release call.
Signed-off-by: Stefan Schwendeler <Stefan.Schwendeler@husqvarnagroup.com>
Not motivated by any impacted functionality but rather following good
practices. Recursive inclusions may be confusing and hard to diagnose.
Signed-off-by: Luis Ubieda <luisf@croxel.com>
This version is based on the CPU LPSPI driver, directly implementing
the submit call following the non-blocking asynchronous pattern.
This has been re-introduced after struggling to keep up with data
streaming applications, which demands reduced and controlled latency,
which for the default implementation (using RTIO workqueue) is not
guaranteed, due to being serviced by a thread-pool vs directly in the
ISR context.
This version includes limited feature-set, yet stress-tested:
- Required both rx-fifo and tx-fifo to be equal.
- 8-byte words supported only.
- SPI Controller-only supported (target mode not included).
- SPI_HOLD_ON_CS only supported with CS GPIOs.
Signed-off-by: Luis Ubieda <luisf@croxel.com>
This commit adds a new property in the device-tree bindings for swapping
the MISO and MOSI pins of the SPI/I2S peripheral for STM32 microcontrollers
that support it.
Signed-off-by: Arthur Gay <arthur.gay@marshmallow.kids>
The driver did send some extra 0 bytes when the receive hasn't been
finished yet. This patch makes sure to avoid that.
Signed-off-by: Christian Mauderer <christian.mauderer@embedded-brains.de>
At the moment, if you would pass a NULL buffer to the driver, the rx and
tx counts of that buffer would not advance. This patch fixes that.
Signed-off-by: Christian Mauderer <christian.mauderer@embedded-brains.de>
The driver has ignored the first RX buffer. Most likely it has been
modeled for accesses to a SPI flash or similar where the first read data
is not relevant.
This commit makes sure that the driver can work as a universal SPI
master instead.
Signed-off-by: Christian Mauderer <christian.mauderer@embedded-brains.de>
Use the timing params from spi_config that are specific to the slave
instead of using the same timing for the controller for all slaves.
Remove these properties from the LPSPI DT binding.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Requesting/releasing SPIM device may be ISR safe, but
it cannot be reliably known whether managing its power
domain is. Is is then assumed that if power domains are used,
device is no longer ISR safe. This macro let's us check if
we will be requesting/releasing power domains and determines
PM device ISR safety value.
Signed-off-by: Michał Stasiak <michal.stasiak@nordicsemi.no>
