Add sleep hold flag to allow setting groups of pins to
automatically hold pad value during low power states (light/deep sleep).
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
This adds the pinctrl driver for Synaptics SR100-series SoCs.
Signed-off-by: Łukasz Kędziora <lkedziora@antmicro.com>
Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com>
Signed-off-by: Andreas Weissel <andreas.weissel@synaptics.com>
Perform iosync configuration in the common stm32_gpioport_configure_pin()
function instead of doing it from the pinctrl driver. This simplifies the
pinctrl driver and also opens the door to iosync configuration using the
GPIO API (via vendor-specific extensions) in the future.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Currently, PINCTRL_IMX_SCMI depends on the SCMI stack being enabled and
the existence of the pinctrl protocol node. This, by itself, is not enough
since this condition can be met by any vendor wanting to use the pinctrl
protocol. Thus, the IMX SCMI pinctrl driver will end up being selected for
other vendors as well, which is not correct.
Fix this by adding a dependency on the IMX-specific pinctrl child being
present. By doing this, the driver will remain auto-selected.
Fixes#105673.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Fix a typo in `pinctrl_configure_pins` where the variable `pin_cgf`
was used instead of `pin_cfg`. Update all references accordingly.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Extend the shared pinctrl driver for BL70XL:
- Use 4 UART signal routing slots (vs 8 on BL60x/BL70x)
- Add XTAL32K pin muxing disable for GPIO30/31
- Handle key scan drive function (disable IE)
- Replace magic numbers with register field defines
- Add BL70XL to pinctrl CMakeLists.txt (reuses bl60x_70x driver)
Signed-off-by: William Markezana <william.markezana@gmail.com>
Replace raw clock_ip_name_t cast with a structured decode of the
encoded `id` clock cell introduced by the KINETIS_SIM_CLOCK() macros.
The sub_system pointer carries a 32-bit encoded value. Extract it via
(uint32_t)(uintptr_t)sub_system and use the KINETIS_SIM_CLOCK_DECODE_*()
macros to retrieve gate_offset, gate_bit and clock_name. This avoids
relying on a C bitfield struct overlay (implementation-defined bit
ordering) or undefined pointer casting behaviour.
Also add mcux_sim_validate_gate_offset() which checks that the decoded
gate register offset is word-aligned and within the SIM register region
size declared in DT, returning -EINVAL if not. This prevents a malformed
clock specifier from accidentally enabling or disabling an unintended
peripheral gate.
Remove the LOG_ERR call and the entire logging module infrastructure
(LOG_LEVEL define, log.h include, LOG_MODULE_REGISTER) since no log
calls remain in the file. This also eliminates the GNU statement
expression extension warning triggered by LOG_ERR macro expansion
under -Wpedantic.
The NXP_KINETIS_SIM_NODE macro is moved to the top of the file so it
can be shared by both the validation helper and the clkout_source /
clkout_divider property accessors.
Fix pinctrl_nxp_port.c to pass the encoded `id` cell (name) as the
clock subsystem instead of constructing CLK_GATE_DEFINE() directly
from the explicit offset/bits DT cells. The old approach bypassed
the new encoding and caused PORT clocks to not be enabled, resulting
in UART pins not being muxed and no serial output.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Now that obtaining the GPIO port device object is always done, the IOsync
configuration logic can be cleaned up. Notably, we can perform it while
still holding the PM Device Runtime reference to avoid an unnecessary
clock_disable and clock_enable.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
The `gpio_stm32_configure()` function is used by both the GPIO and PINCTRL
drivers to configure I/O pins. Move it to the GPIO port manager module's
code so it can be shared properly and update both drivers accordingly.
With this change, the GPIO and PINCTRL drivers are completely decoupled.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
On STM32 hardware, the GPIO port's MMIO interface is used for two purposes
which have their own separate Zephyr API: controlling the state of digital
I/O pins directly (GPIO API) and configuring I/O pins for a specific usage
(PINCTRL API). Historically, this was handled by having the PINCTRL driver
call inside the GPIO driver which works but creates a dependency loop.
Introduce a new `GPIO port manager` module in SoC-specific common code that
takes over various from the existing GPIO/PINCTRL drivers: GPIO port device
instantiation and `GPIO port index -> device` mapping respectively.
Modify the GPIO and PINCTRL drivers to make use of this GPIO port manager
module - a first step in decoupling both drivers from each other.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Adapt all Espressif SoC and driver code to the updated
hal_espressif module synced with IDF master branch.
Main changes:
- clock control: delegate peripheral clock gating to HAL
layer using new clock/reset APIs
- SPI/GDMA: adapt to restructured DMA HAL with new channel
allocation and configuration interfaces
- ethernet: add RMII clock configuration and PHY management
- GPIO: simplify using direct HAL function calls
- flash: adapt to updated SPI flash HAL interfaces
- linker scripts: update IRAM/DRAM mappings for new HAL
object files
- DTS: fix ESP32-S2 PSRAM dcache1 address to match actual
MMU mapping region (0x3f800000 DRAM1 instead of 0x3f500000
DPORT which lacks 8-bit access capability)
- west.yml: update hal_espressif revision
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Several NXP drivers require clock control subsystem name definition in
Devicetree. It prevents usage of clock control without subsystem such
as fixed-clock. fixed-clock can be used for early SoC enablement when
complete clock controller is not available or not required.
Allow optional usage of clock control without subsystem by using 0 as
subsystem name if the name is not defined in devicetree. Add the option
for port, i2c, spi and serial drivers.
Signed-off-by: Michal Smola <michal.smola@nxp.com>
A special SYS_INIT() callback with hardcoded PRE_KERNEL_1 level 0 priority
inside the STM32 pinctrl driver was configuring the SWD-JTAG ports on
STM32F1 series.
Since this is the only series which requires such configuration, move this
code to the SoC-specific init hook instead (which has almost the same
priority as PRE_KERNEL_1 level 0 - it runs just slightly earlier).
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Add pin control driver for Alif SoCs. The driver manages
pin muxing (alternate function selection) and pad configuration
for Alif SoCs.
Signed-off-by: Silesh C V <silesh@alifsemi.com>
Fix inconsistent macro name from IOMUX_GET_SCTIMER_IN_CLR_ENABLE
to IOMUX_GET_CTIMER_CLR_ENABLE to align with the actual CTimer
functionality and related macro naming convention.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
The BCM2711 GPIO controller provides 58 GPIO pins (0-57) that can be
configured for various functions including GPIO input/output and
alternate functions for peripherals like SPI, I2C, UART, PWM, etc.
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
GPIO hardware in Microchip MEC parts is the same except for the MUX
field (number of alternate functions). We modify the old XEC PINCTRL
driver to work on all MEC parts and also be independent of HAL and
CMSIS register structures. During development we found a DT issue
with DT_ENUM_IDX_OR always inserting the default value. Worked around
by converting slew rate and drive strength to YAML integer type and
created defines for the values in the dt-bindings header.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Drop cat1 from the binding files to enable reuse by other
category devices as well.
Fixes#99174
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
Only modify the definitions that need to be changed in the pinmux register;
SR/IS will retain their default values after reset.
Signed-off-by: Haoran Jiang <halfsweet@halfsweet.cn>
Use the "zephyr-keep-sorted-start/stop" comment to have CI check
the alphabetical order of includes, to help reducing the chance
of conflicts while contributing drivers.
Signed-off-by: Josuah Demangeon <me@josuah.net>
GPIO pad power domain management is not neccesary if the quirky
cross domain feature is handled at the application level. Replace it
with directly setting/clearing pin retention, as hardware will force
power domains on automatically.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Pinctrl needs to set the needed drive and direction of the pins. Also
this later allows automatically setting the clock bit for the traceclk
pin.
Signed-off-by: Karsten Koenig <karsten.koenig@nordicsemi.no>
Certain SPIM instances in nRF52/53/54L/54H Series provide hardware
control of the CSN (chip select) line. Although the standard SPI
drivers do not use this feature, it should be possible to configure
this line through pinctrl in case some special driver needs this.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
The SIUL2 pin control driver is a native implementation usable across
all NXP SoCs with SIUL2 IP. Remove the "S32" prefix to allow clean
reuse by other families.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
When PM or PM_DEVICE is enabled pinctrl sleep state is using for
device suspension. However, there are cases where power management is
not used but we still want to be able to put pins to sleep state, e.g.
device deinit.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
The STM32MP2 series needs gpioz pinctrl support to be able to use
the GPIOZ pins.
Signed-off-by: Tanguy Raufflet <tanguy.raufflet@savoirfairelinux.com>
