The pinmux controller provides the total number of muxable pins.
Read this number during initialization and check against it
during each pin configuration.
Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
Enabling the rp1 pinctrl also requires the bcm2712 pinctrl,
so add a minimal stub.
This does not perform any processing, but preserves the register
settings at reset.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
This commit moves pinctrl registers definition file to RTS5817
soc directory, because gpio driver will also include this file
Signed-off-by: Darcy Lu <darcy_lu@realsil.com.cn>
GPIO index 32 belongs to GPIO_GRP1 bit 0, but the split used '> 32',
sending index 32 into a 32-bit shift on GPIO_GRP0 instead. Use '>=',
consistent with the gpio_idx - 32 addressing used for the high group.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
This commit migrates the existing pinmux driver for the musca-b1
board to the newer pinctrl API. The new implementation also fixes
a bug in the original pinmux driver which would have selected
alternative function 2 instead of ALTF1 as desired.
The musca-s1 pinmux driver has been left as this board is
deprecated.
Signed-off-by: Laurie Fay <Laurie.Fay@arm.com>
Support Zephyr RTOS on Cortex A720 for R-Car X5H.
For more information and documentation, please visit the product page:
https://www.renesas.com/secure/gen5-r-car-x5h
Signed-off-by: Nam Nguyen <nam.nguyen.xn@renesas.com>
With PULLEN set, the PORT_OUT bit selects the pull direction. The
pull-down path never cleared a previously set OUT bit, so a requested
pull-down could configure a pull-up instead. Clear the latch in the
pull-down case, as the gpio_mchp_port_g1 driver does.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Add SoC and devicetree support for the R-Car Gen4 R8A779G0 A76.
Co-authored-by: Yuya Hamamachi <yuya.hamamachi.sx@renesas.com>
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Don't allow enabling the STM32 pinctrl driver if no GPIO port is enabled
as this would cause a build error in the GPIOport manager module.
If no GPIO port is enabled, the pinctrl driver is useless anyways.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
The DINOFF update read back SMTEN instead of DINOFF, so the write
seeded the input-disable register from Schmitt-trigger state and
destroyed the other pins' DINOFF bits. Read DINOFF, matching every
other read-modify-write in the function.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Add a pin controller driver for the WCH CH570 SoC.
Implements `pinctrl_configure_pins` to enable GPIO initialization and
alternate function configuration.
Update hal_wch revision in west.yml and hal_ch32fun.h to sync with
changes merged in zephyrproject-rtos/hal_wch#6
Signed-off-by: Elie Carrot <elie.carrot@smile.fr>
Add the initial pinctrl driver support for the ELAN EM32 SoC family.
This driver provides basic pin multiplexing and electrical configuration
support. Device tree bindings are included for pin function definitions.
Signed-off-by: Johnny Chuang <johnny.chuang@emc.com.tw>
Add a pinctrl driver for the CH32H41x AFIO block. Unlike the CH32V20x/30x
remap (PCFR) model, the CH32H41x selects pin alternate functions through
a per-pin 4-bit field in the AFIO GPIOx_AFLR/AFHR registers (STM32-style
mux), in addition to the usual GPIO CFGLR/CFGHR direction and bias
configuration.
The driver is gated by CONFIG_PINCTRL_WCH_H41X_AFIO (default y when the
wch,h41x-afio node is enabled) and is wired into the pinctrl CMakeLists
and Kconfig alongside the existing WCH AFIO drivers.
Signed-off-by: Liu Changjie <liucj1228@outlook.com>
AESC_PINCTRL_MAX_PINS is the pin count, so valid indices are
0 to MAX_PINS - 1, but the guard used '>', letting pin 128 write one
register past the pin mux range. Use '>='.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
The PIN_POSEL case AND-ed the two disjoint bit masks, producing 0, so
the old POC0/POCSEL0 values were never cleared and could not be set
back to zero. OR the masks, matching the POC2/POC3 cases.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Add a required ngpios property to the BCM2711 pinctrl binding
and set it in the SoC dtsi. Update the driver to read the number
of GPIOs from devicetree via DT_INST_PROP.
This makes the GPIO count explicit in devicetree and avoids
hardcoded assumptions in the driver.
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
The PMUX register was not being properly cleared before setting
the new mux value. This causes incorrect pin configuration when
the register contains non-zero initial values.
Signed-off-by: Fabin V Martin <Fabinv.Martin@microchip.com>
Register structs rely on the compiler emitting 32-bit volatile accesses
and on the struct layout staying in sync with the hardware. sys_read32
and sys_write32 make the access width explicit, work with DEVICE_MMIO
address mapping, and match the convention used by in-tree drivers.
Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
Use <> operator to include a Zephyr header file instead of "" that
is intended to local header files, not header files relative to
specifically defined search paths.
This change was made running the sed shell command below:
$ sed -i -E 's/#include "zephyr\/([^"]+)\.h"/#include <zephyr\/\1.h>/g' \
`grep -rsl "#include \"zephyr/" drivers/`
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
-Added pinctrl driver for the NXP LPC84x series.
-The driver manages pin configuration via the IOCON
peripheral and dynamic pin function assignment via
the Switch Matrix (SWM).
Signed-off-by: Surya Prakash T <suryat@aerlync.com>
Signed-off-by: Sayooj K Karun <sayooj@aerlync.com>
Co-authored-by: Dilip Raman <dilipr@aerlync.com>
Pins configured with SAM_PINMUX_FUNC_extra (e.g. ADC analog inputs)
fall through the pinctrl configuration with the function field
defaulting to 0, which maps to SOC_GPIO_FUNC_A (Peripheral A).
If Peripheral A for that pin is an active output (e.g. SSC_TD on
PA17/SAM4S), it drives the pin LOW and the ADC reads 0V despite a
valid analog signal on the input.
Configure extra-function pins as PIO input (high-impedance) so no
peripheral output driver interferes with the analog signal path.
The ADC reads via its own internal analog connection regardless of
PIO mode.
Tested on SAM4S where PA17 (ADC ch0) Peripheral A is SSC_TD — ADC
now reads correctly instead of returning 0.
Signed-off-by: Ričards Poriņš <ricards.porins@gmail.com>
The Alif pinctrl driver needs to be usable by MMU-enabled Cortex-A32
based board variants (in addition to the Cortex-M55 based boards), which
require MMIO regions to be mapped into the virtual address space at
runtime. Map the pinctrl and lpgpio pinctrl regions using device_map()
during boot.
The driver does not use the device model, and the two regions are named
reg entries on a single pinctrl node. As the DEVICE_MMIO_TOPLEVEL_*
macros do not support named reg entries, device_map() is called directly
to map each region.
No behavioral change for the existing non-MMU (Cortex-M55) targets, as
device_map() collapses to a simple address assignment in them, now done
once at boot instead of compile time.
Signed-off-by: Silesh C V <silesh@alifsemi.com>
Add CY_GPIO_DM_CFGOUT3_STRONG_PULLUP_HIGHZ support to pinctrl
driver for Infineon
Assisted-by: Claude:claude-opus-4.7
Signed-off-by: Zayne Stites <Zayne.Stites@infineon.com>
A pin requesting both input-enable and output-enable matched neither
switch case and left both disabled. Test the two bits independently
so a bidirectional pin keeps both directions enabled.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add support for pinctrl to R-Car X5H SoC. Like for other Renesas SoCs,
a node approach is implemented (no grouping approach).
Pin configuration operations can optionally be performed through SCMI
(System Control and Management Interface).
Signed-off-by: Julien Panis <jpanis@baylibre.com>
Select the gpio1 register field layout used by C5/C6/H2 on P4 and
fold the initial pin-level set into a single gpio0/gpio1 path.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The qspi flash controller uses the Serial Memory Interface (SMIF) to
interact with an external memory. This is done through dedicated
data pins which reside in the SMIF HW block. These were not exposed
up until now in the Infineon devices because the extended boot takes
care of initializing the pins properly when booting from external flash.
However this might not always be the case so expose the pin info and
configuration. Additionally, correct the flash controller address to
match the SMIF CORE base address corresponding to the SMIF instance
in use.
Assisted-by: Claude:claude-opus-4.7
Signed-off-by: Laura Carlesso <laura.carlesso@infineon.com>
Encode the SF32LB52x slew-rate pinctrl property into HPSYS_PINMUX.
The devicetree value 0 selects slow slew rate and 1 selects fast
slew rate, while the hardware bit uses 1 for slow and 0 for fast.
PA39-PA42 reuse the same bit as MODE instead of SR. Mask SR out for
those pads and drive MODE separately from the selected pinctrl
function, setting it only for I2C routing and clearing it otherwise.
Signed-off-by: Haoran Jiang <halfsweet@halfsweet.cn>
The pinmux controller for the aesc silicon platform is a simple
controller to mux differnt input outputs to one output option.
Since this is an internal controller, pull, drive strength and slew
rate are not implemented due missing IO pad features.
Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
Enable IOCON clocks from the devicetree clocks property during
pinctrl initialization.
Keep the existing LPC path intact and only use the clock control
flow when a clock is described in devicetree.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Current implementation does not allow omitting a port. Also, if a port is
disabled, the last port is not present in ports array.
Use fixed index for each port in ports array, i.e. porta is always index 0,
portb is index 1, etc. If a port is ommitted or disabled, NULL is assigned
instead of port address.
Signed-off-by: Michal Smola <michal.smola@nxp.com>
Rename BL61x GPIO and pinctrl drivers to bl61x_808 variants since
BL808 shares identical register layouts. Update compatible strings,
Kconfig, CMakeLists, and BL61x device tree accordingly. Extend the
DMA and IR receiver drivers' BL61x guards to also cover BL808.
Signed-off-by: William Markezana <william.markezana@gmail.com>
The `pinctrl_soc_pin_t` format occupied two uint32_t even though all info
it stores can be compressed in 32 bits only, and also didn't map very well
to the hardware (especially on STM32F1). Due to defects, the format was
also NOT what the `stm32_gpioport_configure_pin()` function consumed to
actually configure a GPIO port, requiring additional decoding/manipulation
logic.
Introduce a vastly reworked format which only requires 32-bit per pinctrl
entry and maps nicely to hardware and becomes the new format consumed by
stm32_gpioport_configure_pin(). This heavily simplifies the pinctrl driver
since it no longer needs to examine the actual values (except to determine
the target GPIO port and pin - this is done on purpose!). The GPIO driver
converts Zephyr flags to this new format too.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Move the logic which sets the output level based on configuration to the
common `stm32_gpioport_configure_pin()` function to reduce duplication.
To support the GPIO use case where a pin's configuration is changed without
modifying its output state, a new parameter is introduced which specifies
whether or not the output level should be modified.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Use `_Pos`/`_Msk` suffixed defines for pinctrl format bits definitions and
declare `_Msk` already shifted. This is aligned with the CMSIS definitions
format which shorter, easier to understand and enables use of
macros _FLD2VAL/_VAL2FLD.
Update all code using these defines accordingly.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
QSPI peripheral is now called MSPI in the MDK. To align
with this change, peripheral has been renamed in the
devicetree to MSPI.
Signed-off-by: David Jewsbury <david.jewsbury@nordicsemi.no>
Same issue as the GPIO driver: esp32_pin_is_valid() and
esp32_pin_is_output_capable() use BIT() which overflows on 32-bit
Xtensa for pin numbers >= 32.
Fix by using BIT64() to match the 64-bit SOC_GPIO_VALID_GPIO_MASK.
Signed-off-by: Matin Lotfaliei <matinlotfali@gmail.com>
