Remove redundant register updates in pinctrl_configure_pins, and replace
the improper (and inefficient) use of bitwise OR assignment (|=) with
direct assignments when writing to the write-only BSHR registers
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Modify the STM32 pinctrl driver and SoC-specific pinctrl macros
to introduce support of the st,stm32n6-pinctrl variant.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
The sleep-output property is no longer used. This results in the sleep
bit to be always cleared. Delete this code so we can retain any sleep
mode configuration done.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Some devices have multiple pinctrl regions; for instance, main pinctrl and
mcu pinctrl. Currently there can only be a single pinctrl instance picked
form a DT label. This patch makes the pinctrl driver initialise one
instance for each node with correct compatible string.
Signed-off-by: Amneesh Singh <a-singh7@ti.com>
Fix incorrect use of bitwise OR operator when checking pull-up and
pull-down resistor configuration.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Add MPS4 pinctrl support by referring to
`mps4/common/partition/platform_base_address.h`
from TF-M's main branch.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
Update hal_wch.
As the hal upstream changed name, there is now a name conflict.
Rename ch32fun.h to hal_ch32fun.h to fix this conflict.
Signed-off-by: Miguel Gazquez <miguel.gazquez@bootlin.com>
Added a pinctrl driver support for MSPM0 Family.
Signed-off-by: Saravanan Sekar <saravanan@linumiz.com>
Signed-off-by: Jackson Farley <j-farley@ti.com>
Add missing curly braces in if/while/for statements.
This is a style guideline we have that was not enforced in CI. All
issues fixed here were detected by sonarqube SCA.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The CH32V006 and others in the CH32V00x series are an evolution of the
CH32V003 and use different remap offsets for the various peripherals.
In the same way as the CH32V20x, fork the CH32V003 driver and add
CH32V00x support.
Signed-off-by: Michael Hope <michaelh@juju.nz>
The Alternate Function IO (AFIO) block must have the clock enabled
before configuring. Some remappings seem to work without, but some
like EXTI do not. Fix.
Signed-off-by: Michael Hope <michaelh@juju.nz>
Intial support of pinctrl driver for Renesas RX MCU
family.
This support base on using Renesas RX driver package in
hal_renesas layer
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Signed-off-by: Phi Tran <phi.tran.jg@bp.renesas.com>
Use generic name for structure in driver instead of specific chip name
for better compatibility.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Add support for fixed GPIO routes that don't have a configurable
route register, but still require mode configuration and enabling.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Replace occurrences of "RaspberryPi" with "Raspberry Pi" in
documentation, comment blocks etc. Correct the name of "PicoW" to
"Pico W", matching Raspberry Pi's documentation at
https://www.raspberrypi.com/documentation/microcontrollers/pico-series.html .
Signed-off-by: Andrew Featherstone <andrew.featherstone@gmail.com>
This is the initial commit to support pinctrl driver for Renesas RZ/V2L
Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
This is the initial commit to support pinctrl driver for Renesas RZ/A3UL
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Signed-off-by: Phuc Pham <phuc.pham.xr@bp.renesas.com>
Due to historical reasons, there were two implementations of
R7FA4M1AB3CFM. However, the migration has been completed,
so the old one is now being removed.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
This is the initial commit to support PINCTRL driver for Renesas RZ/T2L
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com>
This is the initial commit to support pinctrl driver for Renesas RZ/N2L
Signed-off-by: Hoang Nguyen <hoang.nguyen.jx@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
This is a follow-up to commit 45d827a51a.
Although routing for those pins is configured via UICR, pinctrl still
needs to be involved so that it is possible to set desired drive mode
for them etc.
Add also the missing RWDS pin.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Fix the scenario where a pinctrl node intends to deallocate a pin
from a peripheral. If the GPIO mode is disabled the DBUS route
should be cleared, not set. This allows reuse of a pin for other
purposes when a driver is suspended and the pinctrl sleep state is
applied, as GPIOs are typically disabled in the sleep state.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
This device is included on Silabs SiWx91x series. The current driver is
able to manage "High Power" and "Ultra Low Power" pins.
Co-authored-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Add support for pinctrl to cc23x0 SoC. Like for other TI SoCs,
a node approach is implemented (no grouping approach).
Signed-off-by: Lars Thalian Morstad <l-morstad@ti.com>
Signed-off-by: Vebjorn Myklebust <v.myklebust@ti.com>
Signed-off-by: Stoyan Bogdanov <sbogdanov@baylibre.com>
Signed-off-by: Julien Panis <jpanis@baylibre.com>
Fixes a multitude of Kconfigs that wrongly appear on devices
where support is literally impossible
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
The GPIO peripheral on Silabs Series 2 devices is responsible for
allocating analog buses to analog peripherals. Enable support for
this in the pinctrl driver. Since these bus allocations are not
digital pins, introduce a new property silabs,analog-bus for this
purpose.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Some peripherals (e.g. ethernet) have remaps only on some of the pins.
Pins without remaps do not conflict and must be ignored to correctly
process the remaps.
Signed-off-by: Vegard Storheil Eriksen <zyp@jvnv.net>
Add the possibility to activate the XBARB driver
Update NXP HAL revision to include support for xbarb
Signed-off-by: Mathias Landolt <mathias.landolt@loepfe.com>
Signed-off-by: Adrian Bieri <adrian.bieri@loepfe.com>
