Adapt all Espressif SoC and driver code to the updated
hal_espressif module synced with IDF master branch.
Main changes:
- clock control: delegate peripheral clock gating to HAL
layer using new clock/reset APIs
- SPI/GDMA: adapt to restructured DMA HAL with new channel
allocation and configuration interfaces
- ethernet: add RMII clock configuration and PHY management
- GPIO: simplify using direct HAL function calls
- flash: adapt to updated SPI flash HAL interfaces
- linker scripts: update IRAM/DRAM mappings for new HAL
object files
- DTS: fix ESP32-S2 PSRAM dcache1 address to match actual
MMU mapping region (0x3f800000 DRAM1 instead of 0x3f500000
DPORT which lacks 8-bit access capability)
- west.yml: update hal_espressif revision
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Several NXP drivers require clock control subsystem name definition in
Devicetree. It prevents usage of clock control without subsystem such
as fixed-clock. fixed-clock can be used for early SoC enablement when
complete clock controller is not available or not required.
Allow optional usage of clock control without subsystem by using 0 as
subsystem name if the name is not defined in devicetree. Add the option
for port, i2c, spi and serial drivers.
Signed-off-by: Michal Smola <michal.smola@nxp.com>
A special SYS_INIT() callback with hardcoded PRE_KERNEL_1 level 0 priority
inside the STM32 pinctrl driver was configuring the SWD-JTAG ports on
STM32F1 series.
Since this is the only series which requires such configuration, move this
code to the SoC-specific init hook instead (which has almost the same
priority as PRE_KERNEL_1 level 0 - it runs just slightly earlier).
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Add pin control driver for Alif SoCs. The driver manages
pin muxing (alternate function selection) and pad configuration
for Alif SoCs.
Signed-off-by: Silesh C V <silesh@alifsemi.com>
Fix inconsistent macro name from IOMUX_GET_SCTIMER_IN_CLR_ENABLE
to IOMUX_GET_CTIMER_CLR_ENABLE to align with the actual CTimer
functionality and related macro naming convention.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
The BCM2711 GPIO controller provides 58 GPIO pins (0-57) that can be
configured for various functions including GPIO input/output and
alternate functions for peripherals like SPI, I2C, UART, PWM, etc.
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
GPIO hardware in Microchip MEC parts is the same except for the MUX
field (number of alternate functions). We modify the old XEC PINCTRL
driver to work on all MEC parts and also be independent of HAL and
CMSIS register structures. During development we found a DT issue
with DT_ENUM_IDX_OR always inserting the default value. Worked around
by converting slew rate and drive strength to YAML integer type and
created defines for the values in the dt-bindings header.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Drop cat1 from the binding files to enable reuse by other
category devices as well.
Fixes#99174
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
Only modify the definitions that need to be changed in the pinmux register;
SR/IS will retain their default values after reset.
Signed-off-by: Haoran Jiang <halfsweet@halfsweet.cn>
Use the "zephyr-keep-sorted-start/stop" comment to have CI check
the alphabetical order of includes, to help reducing the chance
of conflicts while contributing drivers.
Signed-off-by: Josuah Demangeon <me@josuah.net>
GPIO pad power domain management is not neccesary if the quirky
cross domain feature is handled at the application level. Replace it
with directly setting/clearing pin retention, as hardware will force
power domains on automatically.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Pinctrl needs to set the needed drive and direction of the pins. Also
this later allows automatically setting the clock bit for the traceclk
pin.
Signed-off-by: Karsten Koenig <karsten.koenig@nordicsemi.no>
Certain SPIM instances in nRF52/53/54L/54H Series provide hardware
control of the CSN (chip select) line. Although the standard SPI
drivers do not use this feature, it should be possible to configure
this line through pinctrl in case some special driver needs this.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
The SIUL2 pin control driver is a native implementation usable across
all NXP SoCs with SIUL2 IP. Remove the "S32" prefix to allow clean
reuse by other families.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
When PM or PM_DEVICE is enabled pinctrl sleep state is using for
device suspension. However, there are cases where power management is
not used but we still want to be able to put pins to sleep state, e.g.
device deinit.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
The STM32MP2 series needs gpioz pinctrl support to be able to use
the GPIOZ pins.
Signed-off-by: Tanguy Raufflet <tanguy.raufflet@savoirfairelinux.com>
The sleep output configuration should be skipped for pins
22 to 28.
This was causing incorrect GPIO wakeups when entering
standby mode on RW612.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
This property allows a user to specify the operation of a
pin in sleep mode.
By default, pins are configured to be output low in sleep mode.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Reorganize and update soc folder files for SDK-independance
Reorganize and update hal_bouffalolab files for SDK-independance
Reorganize and update soc dts files for SDK-independance
Update serial and pinctrl driver files for SDK-independance
Update ai_wb2_12f, bl604e_iot_dvk, and dt_bl10_dvk
to new bl60x support
and fixup openocd config of ai_wb2_12f
Signed-off-by: Camille BAUD <mail@massdriver.space>
Transition nrf54h away from the soc specific gpd
(global power domain) driver which mixed power domains, pinctrl
and gpio pin retention into a non scalable solution, forcing soc
specific logic to bleed into nrf drivers.
The new solution uses zephyrs PM_DEVICE based power domains to
properly model the hardware layout of device and pin power domains,
and moves pin retention logic out of drivers into pinctrl and
gpio, which are the components which manage pins (pads).
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Previously, FUNC_3 related setting were cleared unconditionally,
regardless of the selected alternate function. This could
unintentionally disable FUNC_3 settings when configuring other
alternate functions.
This change ensures that FUNC_3 gcr/ext bits are only cleared
when alt_func is IT8XXX2_ALT_FUNC_3.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
