GPIO pad power domain management is not neccesary if the quirky
cross domain feature is handled at the application level. Replace it
with directly setting/clearing pin retention, as hardware will force
power domains on automatically.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Pinctrl needs to set the needed drive and direction of the pins. Also
this later allows automatically setting the clock bit for the traceclk
pin.
Signed-off-by: Karsten Koenig <karsten.koenig@nordicsemi.no>
Certain SPIM instances in nRF52/53/54L/54H Series provide hardware
control of the CSN (chip select) line. Although the standard SPI
drivers do not use this feature, it should be possible to configure
this line through pinctrl in case some special driver needs this.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
The SIUL2 pin control driver is a native implementation usable across
all NXP SoCs with SIUL2 IP. Remove the "S32" prefix to allow clean
reuse by other families.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
When PM or PM_DEVICE is enabled pinctrl sleep state is using for
device suspension. However, there are cases where power management is
not used but we still want to be able to put pins to sleep state, e.g.
device deinit.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
The STM32MP2 series needs gpioz pinctrl support to be able to use
the GPIOZ pins.
Signed-off-by: Tanguy Raufflet <tanguy.raufflet@savoirfairelinux.com>
The sleep output configuration should be skipped for pins
22 to 28.
This was causing incorrect GPIO wakeups when entering
standby mode on RW612.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
This property allows a user to specify the operation of a
pin in sleep mode.
By default, pins are configured to be output low in sleep mode.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Reorganize and update soc folder files for SDK-independance
Reorganize and update hal_bouffalolab files for SDK-independance
Reorganize and update soc dts files for SDK-independance
Update serial and pinctrl driver files for SDK-independance
Update ai_wb2_12f, bl604e_iot_dvk, and dt_bl10_dvk
to new bl60x support
and fixup openocd config of ai_wb2_12f
Signed-off-by: Camille BAUD <mail@massdriver.space>
Transition nrf54h away from the soc specific gpd
(global power domain) driver which mixed power domains, pinctrl
and gpio pin retention into a non scalable solution, forcing soc
specific logic to bleed into nrf drivers.
The new solution uses zephyrs PM_DEVICE based power domains to
properly model the hardware layout of device and pin power domains,
and moves pin retention logic out of drivers into pinctrl and
gpio, which are the components which manage pins (pads).
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Previously, FUNC_3 related setting were cleared unconditionally,
regardless of the selected alternate function. This could
unintentionally disable FUNC_3 settings when configuring other
alternate functions.
This change ensures that FUNC_3 gcr/ext bits are only cleared
when alt_func is IT8XXX2_ALT_FUNC_3.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Pins can be configured to retain their config even when the power
domain they belong to is suspended. Update pinctrl_nrf to enable
retain only if the pin has been configured and is not in use
(pincnf is low-power/sleep), disable retain otherwise.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
The CH32V003 has a 8 channel, 10 bit onboard ADC. Add an immediate
mode driver and the appropriate pinctrl bindings. Note that the
CH32V003 GPIO pins have both a floating input and an analogue input
mode, and the pinctrl is needed to put the pin in analogue mode.
Signed-off-by: Michael Hope <michaelh@juju.nz>
- Add support for gpio interrupt on RX130.
- Add support for gpio-keys input subsys on RSK_RX130_512KB boards.
Signed-off-by: Phi Tran <phi.tran.jg@bp.renesas.com>
Fix ABUS allocation if both EVEN and ODD busses are used for the
same port. The initialisation loop would incorrectly overwrite
entire GPIO_nBUSALLOC when iterating the pinctrl array, must do
a read/mask/update/write sequence.
Signed-off-by: Jonny Gellhaar <jonny.gellhaar@prevas.se>
Remove redundant register updates in pinctrl_configure_pins, and replace
the improper (and inefficient) use of bitwise OR assignment (|=) with
direct assignments when writing to the write-only BSHR registers
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Modify the STM32 pinctrl driver and SoC-specific pinctrl macros
to introduce support of the st,stm32n6-pinctrl variant.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
The sleep-output property is no longer used. This results in the sleep
bit to be always cleared. Delete this code so we can retain any sleep
mode configuration done.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Some devices have multiple pinctrl regions; for instance, main pinctrl and
mcu pinctrl. Currently there can only be a single pinctrl instance picked
form a DT label. This patch makes the pinctrl driver initialise one
instance for each node with correct compatible string.
Signed-off-by: Amneesh Singh <a-singh7@ti.com>
Fix incorrect use of bitwise OR operator when checking pull-up and
pull-down resistor configuration.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Add MPS4 pinctrl support by referring to
`mps4/common/partition/platform_base_address.h`
from TF-M's main branch.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
Update hal_wch.
As the hal upstream changed name, there is now a name conflict.
Rename ch32fun.h to hal_ch32fun.h to fix this conflict.
Signed-off-by: Miguel Gazquez <miguel.gazquez@bootlin.com>
Added a pinctrl driver support for MSPM0 Family.
Signed-off-by: Saravanan Sekar <saravanan@linumiz.com>
Signed-off-by: Jackson Farley <j-farley@ti.com>
Add missing curly braces in if/while/for statements.
This is a style guideline we have that was not enforced in CI. All
issues fixed here were detected by sonarqube SCA.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The CH32V006 and others in the CH32V00x series are an evolution of the
CH32V003 and use different remap offsets for the various peripherals.
In the same way as the CH32V20x, fork the CH32V003 driver and add
CH32V00x support.
Signed-off-by: Michael Hope <michaelh@juju.nz>
