Add a generic NRF_FUN_VPR_VIO pinctrl function so that a pin can be
assigned to a VPR core and driven directly through its VIO interface.
Where the local core can select pin routing (NRF_GPIO_HAS_SEL) the pin is
routed to the VPR here; otherwise routing is controlled by the secure
domain via UICR and no action is needed at configure time.
Signed-off-by: Lucas van der Ploeg <lucas.vanderploeg@nordicsemi.no>
Add the NPCM pin controller driver. It selects a pin's function by
writing the SCFG bits listed in devicetree, and sets the pull and
voltage level when requested.
Also add the NPCM4 pin function and pin group tables.
Signed-off-by: Alan Yang <tyang1@nuvoton.com>
Rename the misspelled `offest` bit-field in `pinctrl_soc.h` together with
its user in the NPCX pinctrl driver, and fix the other spelling errors in
the same files. Both files change in one commit so the tree builds at
every commit.
Assisted-by: Claude:claude-sonnet-5-5 codespell
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
device_map() hands out a new virtual mapping on every call and nothing
unmaps it, so reconfiguring pins at runtime leaks virtual address space
until k_mem_map() fails and the kernel panics.
Signed-off-by: Jonathan Elliot Peace <jep@alphabetiq.com>
The PMOD_B UARTB case OR-ed PM_A_CFG0_UART1b, which shifts into the
PMOD A mux field, so PMOD B was left unprogrammed and PMOD A's
setting was corrupted. Use PM_B_CFG0_UART2b, the otherwise unused
constant defined for this case.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
RT266x uses a single combined IOMUXC PIO register per pad, with the
mux-mode and pad configuration in the same register. Add an
SOC_SERIES_IMXRT266X path that combines both into one write so the pad
config does not clobber the mux-mode, and translates the driver-private
input-enable flag to the hardware IBENA bit.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Add the pin controller for the MT8188, with the full pin table and the
devicetree macros that turn a pinmux property into a pin and function pair.
The register window is mapped with device_map() at PRE_KERNEL_1 priority 0
rather than reached through its physical address. There is no struct
device to hang DEVICE_MMIO off, because pinctrl_configure_pins() is called
from other drivers' init before any pin controller device would exist, but
the window still has to be mapped rather than assumed; a static
mmu_regions.c entry would do the same job less portably and only on arm64.
The cluster directory goes on the include path here because the pinctrl
framework includes pinctrl_soc.h, which this commit adds.
Co-authored-by: Felix Freimann <felix.freimann@mediatek.com>
Signed-off-by: Aary Patil <aary.patil@mediatek.com>
Create a dedicated Kconfig option which controls compilation of the
STM32 GPIO port manager module, and select this option explicitly in
the Kconfig for the STM32 GPIO and PINCTRL drivers which require this
module.
This replaces the previous approach where the SoC common CMakeLists
would add the GPIO port manage module to the build automatically if
either of the STM32 GPIO or PINCTRL module was enabled; an explicit
select at Kconfig level makes the dependency more visible.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
The PORT pin-mux registers only answer while the block is clocked, and a
power domain that goes down takes the clock gate with it: it comes back
closed. Every driver that re-applies its pinctrl state on the way back up
writes through those registers, so it faults on an unclocked block, and a
board whose pads are not restored has no console to report it with.
Give the driver a PM handler that re-opens the gate from TURN_ON. The pad
configuration itself is state and not activity -- it has to hold for as
long as the block is powered, whatever the rest of the SoC is doing -- so
SUSPEND, RESUME and TURN_OFF have nothing to do.
Init keeps enabling the clock itself rather than leaving it to TURN_ON.
Drivers apply their pin state from their own initialisation and none of
them claims this device first, so the gate has to be open before any of
them runs, while a device sitting in a power domain is only handed TURN_ON
once something resumes the domain -- which for a domain that only tracks
SoC power states may be much later, or never.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
The block's clock gate is opened from one place, initialisation, and is
about to be opened from a second. Lift it into a function of its own so
both callers share the error handling instead of repeating it.
No functional change.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
AM13 IOMUX has PINCM[0] at base+0 (no RESERVED0 word), unlike MSPM0/
MSPM33 where PINCM[0] is at base+4. Select the correct offset at
compile time using CONFIG_SOC_SERIES_AM13E.
Signed-off-by: Aman Lachhiramka <a-lachhiramka@ti.com>
Extend the gpio_ports[] table from prt21 up to prt30 for the wider
port range on newer CAT1C SoCs, and generate it with LISTIFY()
instead of a copy-pasted GPIO_PORT_OR_NULL() list. Absent ports
still resolve to NULL, so behaviour is unchanged.
Signed-off-by: Alexpandi Muniyandi <alexpandi@linumiz.com>
The MSPM0 pinctrl driver called DL_GPIO_initPeripheralFunction() and
DL_GPIO_initPeripheralAnalogFunction() from TI DriverLib to configure
IOMUX PINCM registers. These are single-register writes that can be
expressed directly using sys_write32(), removing the dependency on the
vendor HAL.
The IOMUX base address is obtained from the pinctrl node reg property
via DT_INST_REG_ADDR(0), which now returns the correct hardware address
after the DTS reorganization.
The pinctrl_soc_pin_t iomux field already encodes configuration bits at
positions that match the PINCM hardware register layout, so values can
be written directly without translation.
Signed-off-by: Aman Lachhiramka <a-lachhiramka@ti.com>
The RP1 register field macros were only used by the pinctrl driver, so
move them into pinctrl_rp1.c and drop the public header (the RP1 GPIO
driver already defines the few fields it needs itself).
Assisted-by: Claude:opus-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
The gpio and pinctrl drivers each open-coded the split of an
absolute pad number into a Zephyr gpio port and pin index. Move
it into one header in the common soc folder and use it from
both, so the next pad user cannot get the split wrong. The
pinctrl copy was a no-op because its pad numbers are already
absolute, so it is dropped.
Assisted-by: Claude:opus-5
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add support for the comparator peripheral found in WCH CH5xx SoCs.
This commit also extends the comparator API with a child API to allow
dynamic configuration of the negative reference voltage. This feature
is intended to enable software-based ADC implementations using the
comparator peripheral.
Signed-off-by: Elie Carrot <elie.carrot@smile.fr>
The pinmux controller provides the total number of muxable pins.
Read this number during initialization and check against it
during each pin configuration.
Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
Enabling the rp1 pinctrl also requires the bcm2712 pinctrl,
so add a minimal stub.
This does not perform any processing, but preserves the register
settings at reset.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
This commit moves pinctrl registers definition file to RTS5817
soc directory, because gpio driver will also include this file
Signed-off-by: Darcy Lu <darcy_lu@realsil.com.cn>
GPIO index 32 belongs to GPIO_GRP1 bit 0, but the split used '> 32',
sending index 32 into a 32-bit shift on GPIO_GRP0 instead. Use '>=',
consistent with the gpio_idx - 32 addressing used for the high group.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
This commit migrates the existing pinmux driver for the musca-b1
board to the newer pinctrl API. The new implementation also fixes
a bug in the original pinmux driver which would have selected
alternative function 2 instead of ALTF1 as desired.
The musca-s1 pinmux driver has been left as this board is
deprecated.
Signed-off-by: Laurie Fay <Laurie.Fay@arm.com>
Support Zephyr RTOS on Cortex A720 for R-Car X5H.
For more information and documentation, please visit the product page:
https://www.renesas.com/secure/gen5-r-car-x5h
Signed-off-by: Nam Nguyen <nam.nguyen.xn@renesas.com>
With PULLEN set, the PORT_OUT bit selects the pull direction. The
pull-down path never cleared a previously set OUT bit, so a requested
pull-down could configure a pull-up instead. Clear the latch in the
pull-down case, as the gpio_mchp_port_g1 driver does.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Add SoC and devicetree support for the R-Car Gen4 R8A779G0 A76.
Co-authored-by: Yuya Hamamachi <yuya.hamamachi.sx@renesas.com>
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Don't allow enabling the STM32 pinctrl driver if no GPIO port is enabled
as this would cause a build error in the GPIOport manager module.
If no GPIO port is enabled, the pinctrl driver is useless anyways.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
The DINOFF update read back SMTEN instead of DINOFF, so the write
seeded the input-disable register from Schmitt-trigger state and
destroyed the other pins' DINOFF bits. Read DINOFF, matching every
other read-modify-write in the function.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Add a pin controller driver for the WCH CH570 SoC.
Implements `pinctrl_configure_pins` to enable GPIO initialization and
alternate function configuration.
Update hal_wch revision in west.yml and hal_ch32fun.h to sync with
changes merged in zephyrproject-rtos/hal_wch#6
Signed-off-by: Elie Carrot <elie.carrot@smile.fr>
Add the initial pinctrl driver support for the ELAN EM32 SoC family.
This driver provides basic pin multiplexing and electrical configuration
support. Device tree bindings are included for pin function definitions.
Signed-off-by: Johnny Chuang <johnny.chuang@emc.com.tw>
Add a pinctrl driver for the CH32H41x AFIO block. Unlike the CH32V20x/30x
remap (PCFR) model, the CH32H41x selects pin alternate functions through
a per-pin 4-bit field in the AFIO GPIOx_AFLR/AFHR registers (STM32-style
mux), in addition to the usual GPIO CFGLR/CFGHR direction and bias
configuration.
The driver is gated by CONFIG_PINCTRL_WCH_H41X_AFIO (default y when the
wch,h41x-afio node is enabled) and is wired into the pinctrl CMakeLists
and Kconfig alongside the existing WCH AFIO drivers.
Signed-off-by: Liu Changjie <liucj1228@outlook.com>
AESC_PINCTRL_MAX_PINS is the pin count, so valid indices are
0 to MAX_PINS - 1, but the guard used '>', letting pin 128 write one
register past the pin mux range. Use '>='.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
The PIN_POSEL case AND-ed the two disjoint bit masks, producing 0, so
the old POC0/POCSEL0 values were never cleared and could not be set
back to zero. OR the masks, matching the POC2/POC3 cases.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Add a required ngpios property to the BCM2711 pinctrl binding
and set it in the SoC dtsi. Update the driver to read the number
of GPIOs from devicetree via DT_INST_PROP.
This makes the GPIO count explicit in devicetree and avoids
hardcoded assumptions in the driver.
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
The PMUX register was not being properly cleared before setting
the new mux value. This causes incorrect pin configuration when
the register contains non-zero initial values.
Signed-off-by: Fabin V Martin <Fabinv.Martin@microchip.com>
Register structs rely on the compiler emitting 32-bit volatile accesses
and on the struct layout staying in sync with the hardware. sys_read32
and sys_write32 make the access width explicit, work with DEVICE_MMIO
address mapping, and match the convention used by in-tree drivers.
Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
Use <> operator to include a Zephyr header file instead of "" that
is intended to local header files, not header files relative to
specifically defined search paths.
This change was made running the sed shell command below:
$ sed -i -E 's/#include "zephyr\/([^"]+)\.h"/#include <zephyr\/\1.h>/g' \
`grep -rsl "#include \"zephyr/" drivers/`
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
-Added pinctrl driver for the NXP LPC84x series.
-The driver manages pin configuration via the IOCON
peripheral and dynamic pin function assignment via
the Switch Matrix (SWM).
Signed-off-by: Surya Prakash T <suryat@aerlync.com>
Signed-off-by: Sayooj K Karun <sayooj@aerlync.com>
Co-authored-by: Dilip Raman <dilipr@aerlync.com>
Pins configured with SAM_PINMUX_FUNC_extra (e.g. ADC analog inputs)
fall through the pinctrl configuration with the function field
defaulting to 0, which maps to SOC_GPIO_FUNC_A (Peripheral A).
If Peripheral A for that pin is an active output (e.g. SSC_TD on
PA17/SAM4S), it drives the pin LOW and the ADC reads 0V despite a
valid analog signal on the input.
Configure extra-function pins as PIO input (high-impedance) so no
peripheral output driver interferes with the analog signal path.
The ADC reads via its own internal analog connection regardless of
PIO mode.
Tested on SAM4S where PA17 (ADC ch0) Peripheral A is SSC_TD — ADC
now reads correctly instead of returning 0.
Signed-off-by: Ričards Poriņš <ricards.porins@gmail.com>
The Alif pinctrl driver needs to be usable by MMU-enabled Cortex-A32
based board variants (in addition to the Cortex-M55 based boards), which
require MMIO regions to be mapped into the virtual address space at
runtime. Map the pinctrl and lpgpio pinctrl regions using device_map()
during boot.
The driver does not use the device model, and the two regions are named
reg entries on a single pinctrl node. As the DEVICE_MMIO_TOPLEVEL_*
macros do not support named reg entries, device_map() is called directly
to map each region.
No behavioral change for the existing non-MMU (Cortex-M55) targets, as
device_map() collapses to a simple address assignment in them, now done
once at boot instead of compile time.
Signed-off-by: Silesh C V <silesh@alifsemi.com>
Add CY_GPIO_DM_CFGOUT3_STRONG_PULLUP_HIGHZ support to pinctrl
driver for Infineon
Assisted-by: Claude:claude-opus-4.7
Signed-off-by: Zayne Stites <Zayne.Stites@infineon.com>
A pin requesting both input-enable and output-enable matched neither
switch case and left both disabled. Test the two bits independently
so a bidirectional pin keeps both directions enabled.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
