drivers: Add MAX32690 pinctrl driver
Pincontrol driver for MAX32690 Co-authored-by: Okan Sahin <okan.sahin@analog.com> Signed-off-by: Sadik Ozer <sadik.ozer@analog.com>
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7 changed files with 330 additions and 0 deletions
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@ -37,5 +37,6 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_QUICKLOGIC_EOS_S3 pinctrl_eos_s3.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_MCI_IO_MUX pinctrl_mci_io_mux.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_ENE_KB1200 pinctrl_ene_kb1200.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_IMX_SCU pinctrl_imx_scu.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_MAX32 pinctrl_max32.c)
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add_subdirectory(renesas)
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@ -65,6 +65,7 @@ source "drivers/pinctrl/Kconfig.eos_s3"
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source "drivers/pinctrl/Kconfig.mci_io_mux"
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source "drivers/pinctrl/Kconfig.ene"
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source "drivers/pinctrl/Kconfig.zynqmp"
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source "drivers/pinctrl/Kconfig.max32"
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rsource "renesas/Kconfig"
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9
drivers/pinctrl/Kconfig.max32
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9
drivers/pinctrl/Kconfig.max32
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@ -0,0 +1,9 @@
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# Copyright (c) 2023-2024 Analog Devices, Inc.
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# SPDX-License-Identifier: Apache-2.0
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config PINCTRL_MAX32
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bool "Analog Devices MAX32 MCUs pin controller driver"
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default y
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depends on DT_HAS_ADI_MAX32_PINCTRL_ENABLED
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help
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Pin controller driver support for max32 SoC series
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114
drivers/pinctrl/pinctrl_max32.c
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114
drivers/pinctrl/pinctrl_max32.c
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@ -0,0 +1,114 @@
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/*
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* Copyright (c) 2023-2024 Analog Devices, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/dt-bindings/pinctrl/max32-pinctrl.h>
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#include <zephyr/dt-bindings/gpio/adi-max32-gpio.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <gpio.h>
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#define ADI_MAX32_GET_PORT_ADDR_OR_NONE(nodelabel) \
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IF_ENABLED(DT_NODE_EXISTS(DT_NODELABEL(nodelabel)), \
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(DT_REG_ADDR(DT_NODELABEL(nodelabel)),))
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/** GPIO port addresses */
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static const uint32_t gpios[] = {
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ADI_MAX32_GET_PORT_ADDR_OR_NONE(gpio0)
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ADI_MAX32_GET_PORT_ADDR_OR_NONE(gpio1)
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ADI_MAX32_GET_PORT_ADDR_OR_NONE(gpio2)
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ADI_MAX32_GET_PORT_ADDR_OR_NONE(gpio3)
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ADI_MAX32_GET_PORT_ADDR_OR_NONE(gpio4)
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ADI_MAX32_GET_PORT_ADDR_OR_NONE(gpio5)
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};
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static int pinctrl_configure_pin(pinctrl_soc_pin_t soc_pin)
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{
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uint32_t port;
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uint32_t pin;
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uint32_t afx;
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int pincfg;
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mxc_gpio_cfg_t gpio_cfg;
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port = MAX32_PINMUX_PORT(soc_pin.pinmux);
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pin = MAX32_PINMUX_PIN(soc_pin.pinmux);
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afx = MAX32_PINMUX_MODE(soc_pin.pinmux);
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pincfg = soc_pin.pincfg;
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if (gpios[port] == 0) {
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return -EINVAL;
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}
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gpio_cfg.port = (mxc_gpio_regs_t *)gpios[port];
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gpio_cfg.mask = BIT(pin);
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if (pincfg & BIT(MAX32_BIAS_PULL_UP_SHIFT)) {
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gpio_cfg.pad = MXC_GPIO_PAD_PULL_UP;
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} else if (pincfg & BIT(MAX32_BIAS_PULL_DOWN_SHIFT)) {
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gpio_cfg.pad = MXC_GPIO_PAD_PULL_DOWN;
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} else {
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gpio_cfg.pad = MXC_GPIO_PAD_NONE;
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}
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if (pincfg & BIT(MAX32_INPUT_ENABLE_SHIFT)) {
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gpio_cfg.func = MXC_GPIO_FUNC_IN;
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} else if (pincfg & BIT(MAX32_OUTPUT_ENABLE_SHIFT)) {
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gpio_cfg.func = MXC_GPIO_FUNC_OUT;
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} else {
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/* Add +1 to index match */
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gpio_cfg.func = (mxc_gpio_func_t)(afx + 1);
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}
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if (pincfg & BIT(MAX32_POWER_SOURCE_SHIFT)) {
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gpio_cfg.vssel = MXC_GPIO_VSSEL_VDDIOH;
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} else {
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gpio_cfg.vssel = MXC_GPIO_VSSEL_VDDIO;
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}
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switch (pincfg & MAX32_GPIO_DRV_STRENGTH_MASK) {
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case MAX32_GPIO_DRV_STRENGTH_1:
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gpio_cfg.drvstr = MXC_GPIO_DRVSTR_1;
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break;
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case MAX32_GPIO_DRV_STRENGTH_2:
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gpio_cfg.drvstr = MXC_GPIO_DRVSTR_2;
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break;
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case MAX32_GPIO_DRV_STRENGTH_3:
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gpio_cfg.drvstr = MXC_GPIO_DRVSTR_3;
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break;
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default:
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gpio_cfg.drvstr = MXC_GPIO_DRVSTR_0;
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break;
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}
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if (MXC_GPIO_Config(&gpio_cfg) != 0) {
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return -ENOTSUP;
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}
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if (pincfg & BIT(MAX32_OUTPUT_ENABLE_SHIFT)) {
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if (pincfg & BIT(MAX32_OUTPUT_HIGH_SHIFT)) {
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MXC_GPIO_OutSet(gpio_cfg.port, BIT(pin));
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} else {
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MXC_GPIO_OutClr(gpio_cfg.port, BIT(pin));
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}
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}
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return 0;
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}
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int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
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{
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ARG_UNUSED(reg);
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int ret;
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for (uint8_t i = 0U; i < pin_cnt; i++) {
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ret = pinctrl_configure_pin(*pins++);
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if (ret) {
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return ret;
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}
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}
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return 0;
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}
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90
dts/bindings/pinctrl/adi,max32-pinctrl.yaml
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90
dts/bindings/pinctrl/adi,max32-pinctrl.yaml
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@ -0,0 +1,90 @@
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# Copyright (c) 2023-2024 Analog Devices, Inc.
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# SPDX-License-Identifier: Apache-2.0
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description: |
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MAX32 Pin controller Node
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Based on pincfg-node.yaml binding.
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Note: `bias-disable` are default pin configurations.
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compatible: "adi,max32-pinctrl"
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include: base.yaml
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properties:
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reg:
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required: true
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child-binding:
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description: |
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Base binding configuration for ADI MAX32xxx MCUs
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include:
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- name: pincfg-node.yaml
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property-allowlist:
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- bias-disable
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- bias-pull-down
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- bias-pull-up
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- output-low
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- output-high
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- input-enable
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- output-enable
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- power-source
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- drive-strength
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properties:
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pinmux:
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required: true
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type: int
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description: |
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Integer array, represents gpio pin number and mux setting.
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These defines are calculated as: (pin<<8 | port<<4 | function<<0)
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With:
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- port: The gpio port index (0, 1, ...)
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- pin: The pin offset within the port (0, 1, 2, ...)
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- function: The function number, can be:
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* 0 : GPIO
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* 1 : Alternate Function 1
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* 2 : Alternate Function 2
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* 3 : Alternate Function 3
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* 4 : Alternate Function 4
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In case selected pin function is GPIO, pin is statically configured as
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a plain input/output GPIO. Default configuration is input. Output value
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can be configured by adding 'ouptut-low' or 'output-high' properties
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to the pin configuration.
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To simplify the usage, macro is available to generate "pinmux" field.
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This macro is available here:
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-include/zephyr/dt-bindings/pinctrl/max32-pinctrl.h
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Some examples of macro usage:
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P0.9 set as alernate function 1
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{
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pinmux = <MAX32_PINMUX(0, 9, AF1)>;
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};
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P0.9 set as alernate function 2
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{
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pinmux = <MAX32_PINMUX(0, 9, AF2)>;
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};
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P0.9 set as GPIO output high
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{
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pinmux = <MAX32_PINMUX(0, 9, GPIO)>;
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output-high;
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};
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power-source:
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enum: [0, 1]
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description: |
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GPIO Supply Voltage Select, Selects the voltage rail used for the pin.
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0 or MAX32_VSEL_VDDIO
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1 or MAX32_VSEL_VDDIOH
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drive-strength:
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default: 0
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enum: [0, 1, 2, 3]
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description: |
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There are 4 drive strength mode.
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Mode 0: 1mA
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Mode 1: 2mA
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Mode 2: 4mA
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Mode 3: 8mA
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Default GPIO output drive strength is mode 0 for MAX32 MCUs.
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For more information please take a look device user guide, datasheet.
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67
include/zephyr/dt-bindings/pinctrl/max32-pinctrl.h
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67
include/zephyr/dt-bindings/pinctrl/max32-pinctrl.h
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/*
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* Copyright (c) 2023-2024 Analog Devices, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_MAX32_PINCTRL_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_MAX32_PINCTRL_H_
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/**
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* @brief Pin modes
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*/
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#define MAX32_MODE_GPIO 0x00
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#define MAX32_MODE_AF1 0x01
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#define MAX32_MODE_AF2 0x02
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#define MAX32_MODE_AF3 0x03
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#define MAX32_MODE_AF4 0x04
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#define MAX32_MODE_AF5 0x05
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/**
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* @brief Mode, port, pin shift number
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*/
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#define MAX32_MODE_SHIFT 0U
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#define MAX32_MODE_MASK 0x0FU
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#define MAX32_PORT_SHIFT 4U
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#define MAX32_PORT_MASK 0x0FU
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#define MAX32_PIN_SHIFT 8U
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#define MAX32_PIN_MASK 0xFFU
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/**
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* @brief Pin configuration bit field.
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*
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* Fields:
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*
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* - mode [ 0 : 3 ]
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* - port [ 4 : 7 ]
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* - pin [ 8 : 15 ]
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*
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* @param port Port (0 .. 15)
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* @param pin Pin (0..31)
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* @param mode Mode (GPIO, AF1, AF2...).
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*/
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#define MAX32_PINMUX(port, pin, mode) \
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((((port)&MAX32_PORT_MASK) << MAX32_PORT_SHIFT) | \
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(((pin)&MAX32_PIN_MASK) << MAX32_PIN_SHIFT) | \
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(((MAX32_MODE_##mode) & MAX32_MODE_MASK) << MAX32_MODE_SHIFT))
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#define MAX32_PINMUX_PORT(pinmux) (((pinmux) >> MAX32_PORT_SHIFT) & MAX32_PORT_MASK)
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#define MAX32_PINMUX_PIN(pinmux) (((pinmux) >> MAX32_PIN_SHIFT) & MAX32_PIN_MASK)
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#define MAX32_PINMUX_MODE(pinmux) (((pinmux) >> MAX32_MODE_SHIFT) & MAX32_MODE_MASK)
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/* Selects the voltage rail used for the pin */
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#define MAX32_VSEL_VDDIO 0
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#define MAX32_VSEL_VDDIOH 1
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/**
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* @brief Pin configuration
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*/
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#define MAX32_INPUT_ENABLE_SHIFT 0x00
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#define MAX32_BIAS_PULL_UP_SHIFT 0x01
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#define MAX32_BIAS_PULL_DOWN_SHIFT 0x02
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#define MAX32_OUTPUT_ENABLE_SHIFT 0x03
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#define MAX32_POWER_SOURCE_SHIFT 0x04
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#define MAX32_OUTPUT_HIGH_SHIFT 0x05
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#define MAX32_DRV_STRENGTH_SHIFT 0x06 /* 2 bits */
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#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_MAX32_PINCTRL_H_ */
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48
soc/adi/max32/common/pinctrl_soc.h
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48
soc/adi/max32/common/pinctrl_soc.h
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/*
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* Copyright (c) 2023-2024 Analog Devices, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_SOC_ARM_ADI_MAX32_COMMON_PINCTRL_SOC_H_
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#define ZEPHYR_SOC_ARM_ADI_MAX32_COMMON_PINCTRL_SOC_H_
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#include <zephyr/devicetree.h>
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#include <zephyr/types.h>
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#include <zephyr/dt-bindings/pinctrl/max32-pinctrl.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef struct pinctrl_soc_pin {
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uint32_t pinmux;
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uint32_t pincfg;
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} pinctrl_soc_pin_t;
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#define Z_PINCTRL_MAX32_PINMUX_INIT(node_id) DT_PROP(node_id, pinmux)
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#define Z_PINCTRL_MAX32_PINCFG_INIT(node) \
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((DT_PROP_OR(node, input_enable, 0) << MAX32_INPUT_ENABLE_SHIFT) | \
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(DT_PROP_OR(node, output_enable, 0) << MAX32_OUTPUT_ENABLE_SHIFT) | \
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(DT_PROP_OR(node, bias_pull_up, 0) << MAX32_BIAS_PULL_UP_SHIFT) | \
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(DT_PROP_OR(node, bias_pull_down, 0) << MAX32_BIAS_PULL_DOWN_SHIFT) | \
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(DT_PROP_OR(node, power_source, 0) << MAX32_POWER_SOURCE_SHIFT) | \
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(DT_PROP_OR(node, output_high, 0) << MAX32_OUTPUT_HIGH_SHIFT) | \
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(DT_PROP_OR(node, drive_strength, 0) << MAX32_DRV_STRENGTH_SHIFT))
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#define Z_PINCTRL_STATE_PIN_INIT(node_id, state_prop, idx) \
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{.pinmux = Z_PINCTRL_MAX32_PINMUX_INIT(DT_PROP_BY_IDX(node_id, state_prop, idx)), \
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.pincfg = Z_PINCTRL_MAX32_PINCFG_INIT(DT_PROP_BY_IDX(node_id, state_prop, idx))},
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#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
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{ \
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DT_FOREACH_PROP_ELEM(node_id, prop, Z_PINCTRL_STATE_PIN_INIT) \
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* ZEPHYR_SOC_ARM_ADI_MAX32_COMMON_PINCTRL_SOC_H_ */
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