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drivers: pinctrl: Add pinctrl driver for RA8 series

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This is the initial commit to support minimum pinctrl
driver for Renesas MCU RA8M1.

Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
This commit is contained in:
Duy Nguyen 2024-01-11 04:51:42 +00:00 • committed by Anas Nashif
commit 75f1f7e982
8 changed files with 274 additions and 0 deletions
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2
drivers/pinctrl/renesas/CMakeLists.txt
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@ -1,7 +1,9 @@
# Copyright (c) 2024 EPAM Systems
# Copyright (c) 2024 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
zephyr_library_sources_ifdef(CONFIG_PINCTRL_RENESAS_RA ra/pinctrl_renesas_ra.c)
zephyr_library_sources_ifdef(CONFIG_PINCTRL_RENESAS_RA8 ra/pinctrl_renesas_ra8.c)
zephyr_library_sources_ifdef(CONFIG_PINCTRL_RZT2M rz/pinctrl_rzt2m.c)
zephyr_library_sources_ifdef(CONFIG_PINCTRL_SMARTBOND smartbond/pinctrl_smartbond.c)

8
drivers/pinctrl/renesas/ra/Kconfig
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@ -1,4 +1,5 @@
# Copyright (c) 2023 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
# Copyright (c) 2024 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
config PINCTRL_RENESAS_RA
@ -7,3 +8,10 @@ config PINCTRL_RENESAS_RA
depends on DT_HAS_RENESAS_RA_PINCTRL_ENABLED
help
Enable Renesas RA series pin controller driver.
config PINCTRL_RENESAS_RA8
bool "Renesas RA8 pinctrl driver"
default y
depends on DT_HAS_RENESAS_RA8_PINCTRL_ENABLED
help
Enable the Renesas RA8 pinctrl driver.

28
drivers/pinctrl/renesas/ra/pinctrl_renesas_ra8.c Normal file
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@ -0,0 +1,28 @@
/*
* Copyright (c) 2024 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/drivers/pinctrl.h>
#include <soc.h>
#define PORT_POS (8)
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
{
bsp_io_port_pin_t port_pin;
R_BSP_PinAccessEnable();
for (uint8_t i = 0U; i < pin_cnt; i++) {
const pinctrl_soc_pin_t *pin = &pins[i];
port_pin = (pin->port_num << PORT_POS) | pin->pin_num;
R_BSP_PinCfg(port_pin, pin->cfg);
}
R_BSP_PinAccessDisable();
return 0;
}

7
dts/arm/renesas/ra/ra8/ra8x1.dtsi
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@ -7,6 +7,7 @@
#include <mem.h>
#include <arm/armv8.1-m.dtsi>
#include <freq.h>
#include <zephyr/dt-bindings/pinctrl/renesas/ra-pinctrl.h>
/ {
@ -61,6 +62,12 @@
status = "okay";
};
};
pinctrl: pin-controller@40400800 {
compatible = "renesas,ra8-pinctrl";
reg = <0x40400800 0x3c0>;
status = "okay";
};
};
&nvic {

105
dts/bindings/pinctrl/renesas,ra8-pinctrl.yaml Normal file
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@ -0,0 +1,105 @@
# Copyright (c) 2024 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0
description: |
The Renesas RA pin controller is a node responsible for controlling
pin function selection and pin properties, such as routing a SCI0 RXD
to P610.
The node has the 'pinctrl' node label set in your SoC's devicetree,
so you can modify it like this:
&pinctrl {
/* your modifications go here */
};
All device pin configurations should be placed in child nodes of the
'pinctrl' node, as shown in this example:
/* You can put this in places like a board-pinctrl.dtsi file in
* your board directory, or a devicetree overlay in your application.
*/
/* include pre-defined combinations for the SoC variant used by the board */
#include <dt-bindings/pinctrl/renesas/ra-pinctrl.h>
&pinctrl {
/* configuration for the sci0 "default" state */
sci0_default: sci0_default {
group1 {
/* tx */
psels = <RA_PSEL(RA_PSEL_SCI_0, 6, 9)>;
drive-strength = "medium";
};
group2 {
/* rx */
psels = <RA_PSEL(RA_PSEL_SCI_0, 6, 10)>;
};
};
};
The 'sci0_default' child node encodes the pin configurations for a
particular state of a device; in this case, the default (that is, active)
state.
As shown, pin configurations are organized in groups within each child node.
Each group can specify a list of pin function selections in the 'psels'
property.
A group can also specify shared pin properties common to all the specified
pins, such as the 'input-enable' property in group 2. Here is a list of
supported standard pin properties:
- bias-disable: Disable pull-up/down (default, not required).
- bias-pull-up: Enable pull-up resistor.
- input-enable: Enable input from the pin.
- drive-strength: Set the drive strength of the pin. Possible
values are: low, medium, highspeed-high, high.
To link pin configurations with a device, use a pinctrl-N property for some
number N, like this example you could place in your board's DTS file:
#include "board-pinctrl.dtsi"
&sci0 {
pinctrl-0 = <&uart0_default>;
pinctrl-1 = <&uart0_sleep>;
pinctrl-names = "default", "sleep";
};
compatible: "renesas,ra8-pinctrl"
include: base.yaml
child-binding:
description: |
Definitions for a pinctrl state.
child-binding:
include:
- name: pincfg-node.yaml
property-allowlist:
- bias-disable
- bias-pull-up
- input-enable
- drive-open-drain
properties:
psels:
required: true
type: array
description: |
An array of pins sharing the same group properties. Each
element of the array is an integer constructed from the
pin number and the alternative function of the pin.
drive-strength:
type: string
enum:
- "low"
- "medium"
- "highspeed-high"
- "high"
default: "low"
description: |
The drive strength of a pin. The default value is low, as this
is the power on reset value.

56
include/zephyr/dt-bindings/pinctrl/renesas/ra-pinctrl.h Normal file
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@ -0,0 +1,56 @@
/*
* Copyright (c) 2024 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_RA_PINCTRL_H__
#define __ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_RA_PINCTRL_H__
#define RA_PORT_NUM_POS 0
#define RA_PORT_NUM_MASK 0xf
#define RA_PIN_NUM_POS 4
#define RA_PIN_NUM_MASK 0xf
#define RA_PSEL_HIZ_JTAG_SWD 0x0
#define RA_PSEL_AGT 0x1
#define RA_PSEL_GPT0 0x2
#define RA_PSEL_GPT1 0x3
#define RA_PSEL_SCI_0 0x4
#define RA_PSEL_SCI_2 0x4
#define RA_PSEL_SCI_4 0x4
#define RA_PSEL_SCI_6 0x4
#define RA_PSEL_SCI_8 0x4
#define RA_PSEL_SCI_1 0x5
#define RA_PSEL_SCI_3 0x5
#define RA_PSEL_SCI_5 0x5
#define RA_PSEL_SCI_7 0x5
#define RA_PSEL_SCI_9 0x5
#define RA_PSEL_SPI 0x6
#define RA_PSEL_I2C 0x7
#define RA_PSEL_CLKOUT_RTC 0x9
#define RA_PSEL_CAC_ADC 0xa
#define RA_PSEL_BUS 0xb
#define RA_PSEL_CANFD 0x10
#define RA_PSEL_QSPI 0x11
#define RA_PSEL_SSIE 0x12
#define RA_PSEL_USBFS 0x13
#define RA_PSEL_USBHS 0x14
#define RA_PSEL_SDHI 0x15
#define RA_PSEL_ETH_MII 0x16
#define RA_PSEL_ETH_RMII 0x17
#define RA_PSEL_GLCDC 0x19
#define RA_PSEL_OSPI 0x1c
#define RA_PSEL_POS 8
#define RA_PSEL_MASK 0x1f
#define RA_MODE_POS 13
#define RA_MODE_MASK 0x1
#define RA_PSEL(psel, port_num, pin_num) \
(1 << RA_MODE_POS | psel << RA_PSEL_POS | port_num << RA_PORT_NUM_POS | \
pin_num << RA_PIN_NUM_POS)
#endif /* __ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_RA_PINCTRL_H__ */

65
soc/renesas/ra/common_fsp/pinctrl_soc.h Normal file
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@ -0,0 +1,65 @@
/*
* Copyright (c) 2024 Renesas Electronics Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_SOC_RENESAS_RA_COMMON_PINCTRL_SOC_H_
#define ZEPHYR_SOC_RENESAS_RA_COMMON_PINCTRL_SOC_H_
#include <zephyr/devicetree.h>
#include <zephyr/types.h>
#include <zephyr/dt-bindings/pinctrl/renesas/ra-pinctrl.h>
/**
* @brief Type to hold a renesas ra pin's pinctrl configuration.
*/
struct ra_pinctrl_soc_pin {
/** Port number 0..9, A, B */
uint32_t port_num: 4;
/** Pin number 0..15 */
uint32_t pin_num: 4;
/** Register PFS cfg */
uint32_t cfg;
};
typedef struct ra_pinctrl_soc_pin pinctrl_soc_pin_t;
/**
* @brief Utility macro to initialize each pin.
*
* @param node_id Node identifier.
* @param prop Property name.
* @param idx Property entry index.
*/
#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \
{ \
.port_num = RA_GET_PORT_NUM(DT_PROP_BY_IDX(node_id, prop, idx)), \
.pin_num = RA_GET_PIN_NUM(DT_PROP_BY_IDX(node_id, prop, idx)), \
.cfg = (DT_PROP(node_id, bias_pull_up) << 4) | \
(DT_PROP(node_id, drive_open_drain) << 6) | \
(DT_ENUM_IDX(node_id, drive_strength) << 10) | \
(RA_GET_MODE(DT_PROP_BY_IDX(node_id, prop, idx)) << 16) | \
(RA_GET_PSEL(DT_PROP_BY_IDX(node_id, prop, idx)) << 24), \
},
/**
* @brief Utility macro to initialize state pins contained in a given property.
*
* @param node_id Node identifier.
* @param prop Property name describing state pins.
*/
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
{ \
DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), DT_FOREACH_PROP_ELEM, psels, \
Z_PINCTRL_STATE_PIN_INIT) \
}
#define RA_GET_PORT_NUM(pinctrl) (((pinctrl) >> RA_PORT_NUM_POS) & RA_PORT_NUM_MASK)
#define RA_GET_PIN_NUM(pinctrl) (((pinctrl) >> RA_PIN_NUM_POS) & RA_PIN_NUM_MASK)
#define RA_GET_MODE(pinctrl) (((pinctrl) >> RA_MODE_POS) & RA_MODE_MASK)
#define RA_GET_PSEL(pinctrl) (((pinctrl) >> RA_PSEL_POS) & RA_PSEL_MASK)
#endif /* ZEPHYR_SOC_RENESAS_RA_COMMON_PINCTRL_SOC_H_ */

3
soc/renesas/ra/ra8m1/soc.c
View file

@ -23,6 +23,8 @@ LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
/**
* @brief Perform basic hardware initialization at boot.
*
@ -34,6 +36,7 @@ uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
static int renesas_ra8m1_init(void)
{
SystemCoreClock = BSP_MOCO_HZ;
g_protect_pfswe_counter = 0;
bsp_clock_init();
return 0;