drivers: pinctrl: Add pinctrl driver for RA8 series
This is the initial commit to support minimum pinctrl driver for Renesas MCU RA8M1. Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
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@ -1,7 +1,9 @@
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# Copyright (c) 2024 EPAM Systems
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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_RENESAS_RA ra/pinctrl_renesas_ra.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_RENESAS_RA8 ra/pinctrl_renesas_ra8.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_RZT2M rz/pinctrl_rzt2m.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_SMARTBOND smartbond/pinctrl_smartbond.c)
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@ -1,4 +1,5 @@
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# Copyright (c) 2023 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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config PINCTRL_RENESAS_RA
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@ -7,3 +8,10 @@ config PINCTRL_RENESAS_RA
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depends on DT_HAS_RENESAS_RA_PINCTRL_ENABLED
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help
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Enable Renesas RA series pin controller driver.
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config PINCTRL_RENESAS_RA8
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bool "Renesas RA8 pinctrl driver"
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default y
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depends on DT_HAS_RENESAS_RA8_PINCTRL_ENABLED
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help
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Enable the Renesas RA8 pinctrl driver.
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28
drivers/pinctrl/renesas/ra/pinctrl_renesas_ra8.c
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28
drivers/pinctrl/renesas/ra/pinctrl_renesas_ra8.c
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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/drivers/pinctrl.h>
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#include <soc.h>
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#define PORT_POS (8)
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int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
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{
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bsp_io_port_pin_t port_pin;
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R_BSP_PinAccessEnable();
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for (uint8_t i = 0U; i < pin_cnt; i++) {
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const pinctrl_soc_pin_t *pin = &pins[i];
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port_pin = (pin->port_num << PORT_POS) | pin->pin_num;
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R_BSP_PinCfg(port_pin, pin->cfg);
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}
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R_BSP_PinAccessDisable();
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return 0;
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}
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@ -7,6 +7,7 @@
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#include <mem.h>
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#include <arm/armv8.1-m.dtsi>
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#include <freq.h>
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#include <zephyr/dt-bindings/pinctrl/renesas/ra-pinctrl.h>
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/ {
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status = "okay";
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};
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};
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pinctrl: pin-controller@40400800 {
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compatible = "renesas,ra8-pinctrl";
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reg = <0x40400800 0x3c0>;
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status = "okay";
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};
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};
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&nvic {
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105
dts/bindings/pinctrl/renesas,ra8-pinctrl.yaml
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dts/bindings/pinctrl/renesas,ra8-pinctrl.yaml
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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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description: |
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The Renesas RA pin controller is a node responsible for controlling
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pin function selection and pin properties, such as routing a SCI0 RXD
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to P610.
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The node has the 'pinctrl' node label set in your SoC's devicetree,
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so you can modify it like this:
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&pinctrl {
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/* your modifications go here */
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};
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All device pin configurations should be placed in child nodes of the
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'pinctrl' node, as shown in this example:
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/* You can put this in places like a board-pinctrl.dtsi file in
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* your board directory, or a devicetree overlay in your application.
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*/
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/* include pre-defined combinations for the SoC variant used by the board */
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#include <dt-bindings/pinctrl/renesas/ra-pinctrl.h>
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&pinctrl {
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/* configuration for the sci0 "default" state */
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sci0_default: sci0_default {
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group1 {
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/* tx */
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psels = <RA_PSEL(RA_PSEL_SCI_0, 6, 9)>;
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drive-strength = "medium";
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};
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group2 {
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/* rx */
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psels = <RA_PSEL(RA_PSEL_SCI_0, 6, 10)>;
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};
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};
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};
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The 'sci0_default' child node encodes the pin configurations for a
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particular state of a device; in this case, the default (that is, active)
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state.
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As shown, pin configurations are organized in groups within each child node.
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Each group can specify a list of pin function selections in the 'psels'
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property.
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A group can also specify shared pin properties common to all the specified
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pins, such as the 'input-enable' property in group 2. Here is a list of
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supported standard pin properties:
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- bias-disable: Disable pull-up/down (default, not required).
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- bias-pull-up: Enable pull-up resistor.
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- input-enable: Enable input from the pin.
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- drive-strength: Set the drive strength of the pin. Possible
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values are: low, medium, highspeed-high, high.
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To link pin configurations with a device, use a pinctrl-N property for some
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number N, like this example you could place in your board's DTS file:
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#include "board-pinctrl.dtsi"
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&sci0 {
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pinctrl-0 = <&uart0_default>;
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pinctrl-1 = <&uart0_sleep>;
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pinctrl-names = "default", "sleep";
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};
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compatible: "renesas,ra8-pinctrl"
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include: base.yaml
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child-binding:
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description: |
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Definitions for a pinctrl state.
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child-binding:
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include:
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- name: pincfg-node.yaml
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property-allowlist:
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- bias-disable
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- bias-pull-up
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- input-enable
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- drive-open-drain
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properties:
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psels:
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required: true
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type: array
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description: |
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An array of pins sharing the same group properties. Each
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element of the array is an integer constructed from the
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pin number and the alternative function of the pin.
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drive-strength:
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type: string
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enum:
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- "low"
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- "medium"
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- "highspeed-high"
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- "high"
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default: "low"
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description: |
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The drive strength of a pin. The default value is low, as this
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is the power on reset value.
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56
include/zephyr/dt-bindings/pinctrl/renesas/ra-pinctrl.h
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56
include/zephyr/dt-bindings/pinctrl/renesas/ra-pinctrl.h
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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_RA_PINCTRL_H__
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#define __ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_RA_PINCTRL_H__
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#define RA_PORT_NUM_POS 0
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#define RA_PORT_NUM_MASK 0xf
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#define RA_PIN_NUM_POS 4
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#define RA_PIN_NUM_MASK 0xf
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#define RA_PSEL_HIZ_JTAG_SWD 0x0
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#define RA_PSEL_AGT 0x1
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#define RA_PSEL_GPT0 0x2
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#define RA_PSEL_GPT1 0x3
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#define RA_PSEL_SCI_0 0x4
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#define RA_PSEL_SCI_2 0x4
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#define RA_PSEL_SCI_4 0x4
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#define RA_PSEL_SCI_6 0x4
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#define RA_PSEL_SCI_8 0x4
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#define RA_PSEL_SCI_1 0x5
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#define RA_PSEL_SCI_3 0x5
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#define RA_PSEL_SCI_5 0x5
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#define RA_PSEL_SCI_7 0x5
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#define RA_PSEL_SCI_9 0x5
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#define RA_PSEL_SPI 0x6
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#define RA_PSEL_I2C 0x7
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#define RA_PSEL_CLKOUT_RTC 0x9
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#define RA_PSEL_CAC_ADC 0xa
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#define RA_PSEL_BUS 0xb
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#define RA_PSEL_CANFD 0x10
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#define RA_PSEL_QSPI 0x11
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#define RA_PSEL_SSIE 0x12
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#define RA_PSEL_USBFS 0x13
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#define RA_PSEL_USBHS 0x14
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#define RA_PSEL_SDHI 0x15
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#define RA_PSEL_ETH_MII 0x16
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#define RA_PSEL_ETH_RMII 0x17
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#define RA_PSEL_GLCDC 0x19
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#define RA_PSEL_OSPI 0x1c
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#define RA_PSEL_POS 8
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#define RA_PSEL_MASK 0x1f
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#define RA_MODE_POS 13
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#define RA_MODE_MASK 0x1
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#define RA_PSEL(psel, port_num, pin_num) \
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(1 << RA_MODE_POS | psel << RA_PSEL_POS | port_num << RA_PORT_NUM_POS | \
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pin_num << RA_PIN_NUM_POS)
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#endif /* __ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_RA_PINCTRL_H__ */
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soc/renesas/ra/common_fsp/pinctrl_soc.h
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soc/renesas/ra/common_fsp/pinctrl_soc.h
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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_SOC_RENESAS_RA_COMMON_PINCTRL_SOC_H_
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#define ZEPHYR_SOC_RENESAS_RA_COMMON_PINCTRL_SOC_H_
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#include <zephyr/devicetree.h>
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#include <zephyr/types.h>
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#include <zephyr/dt-bindings/pinctrl/renesas/ra-pinctrl.h>
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/**
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* @brief Type to hold a renesas ra pin's pinctrl configuration.
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*/
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struct ra_pinctrl_soc_pin {
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/** Port number 0..9, A, B */
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uint32_t port_num: 4;
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/** Pin number 0..15 */
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uint32_t pin_num: 4;
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/** Register PFS cfg */
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uint32_t cfg;
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};
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typedef struct ra_pinctrl_soc_pin pinctrl_soc_pin_t;
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/**
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* @brief Utility macro to initialize each pin.
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*
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* @param node_id Node identifier.
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* @param prop Property name.
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* @param idx Property entry index.
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*/
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#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \
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{ \
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.port_num = RA_GET_PORT_NUM(DT_PROP_BY_IDX(node_id, prop, idx)), \
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.pin_num = RA_GET_PIN_NUM(DT_PROP_BY_IDX(node_id, prop, idx)), \
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.cfg = (DT_PROP(node_id, bias_pull_up) << 4) | \
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(DT_PROP(node_id, drive_open_drain) << 6) | \
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(DT_ENUM_IDX(node_id, drive_strength) << 10) | \
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(RA_GET_MODE(DT_PROP_BY_IDX(node_id, prop, idx)) << 16) | \
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(RA_GET_PSEL(DT_PROP_BY_IDX(node_id, prop, idx)) << 24), \
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},
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/**
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* @brief Utility macro to initialize state pins contained in a given property.
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*
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* @param node_id Node identifier.
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* @param prop Property name describing state pins.
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*/
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#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
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{ \
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DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), DT_FOREACH_PROP_ELEM, psels, \
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Z_PINCTRL_STATE_PIN_INIT) \
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}
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#define RA_GET_PORT_NUM(pinctrl) (((pinctrl) >> RA_PORT_NUM_POS) & RA_PORT_NUM_MASK)
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#define RA_GET_PIN_NUM(pinctrl) (((pinctrl) >> RA_PIN_NUM_POS) & RA_PIN_NUM_MASK)
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#define RA_GET_MODE(pinctrl) (((pinctrl) >> RA_MODE_POS) & RA_MODE_MASK)
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#define RA_GET_PSEL(pinctrl) (((pinctrl) >> RA_PSEL_POS) & RA_PSEL_MASK)
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#endif /* ZEPHYR_SOC_RENESAS_RA_COMMON_PINCTRL_SOC_H_ */
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@ -23,6 +23,8 @@ LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
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uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
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volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
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/**
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* @brief Perform basic hardware initialization at boot.
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*
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static int renesas_ra8m1_init(void)
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{
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SystemCoreClock = BSP_MOCO_HZ;
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g_protect_pfswe_counter = 0;
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bsp_clock_init();
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return 0;
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