drivers: pinctrl: update pinctrl_lpc_iocon.c driver
Define iocon array to store iocon base address add index parameter support to support multi iocon instances Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
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1 changed files with 25 additions and 6 deletions
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@ -1,5 +1,5 @@
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/*
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* Copyright 2022, NXP
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* Copyright 2022,2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -11,22 +11,40 @@
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#include <fsl_clock.h>
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#endif
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/* IOCON register addresses. */
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static uint32_t volatile *iocon[] = {
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#if (DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(iocon)))
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(uint32_t *)DT_REG_ADDR(DT_NODELABEL(iocon)),
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#else
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NULL,
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#endif
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#if (DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(iocon1)))
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(uint32_t *)DT_REG_ADDR(DT_NODELABEL(iocon1)),
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#else
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NULL,
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#endif
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#if (DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(iocon2)))
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(uint32_t *)DT_REG_ADDR(DT_NODELABEL(iocon2)),
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#else
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NULL,
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#endif
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};
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#define OFFSET(mux) (((mux) & 0xFFF00000) >> 20)
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#define TYPE(mux) (((mux) & 0xC0000) >> 18)
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#define INDEX(mux) (((mux) & 0x38000) >> 15)
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#define IOCON_TYPE_D 0x0
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#define IOCON_TYPE_I 0x1
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#define IOCON_TYPE_A 0x2
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static volatile uint32_t *iocon =
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(volatile uint32_t *)DT_REG_ADDR(DT_NODELABEL(iocon));
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int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
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uintptr_t reg)
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int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
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{
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for (uint8_t i = 0; i < pin_cnt; i++) {
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uint32_t pin_mux = pins[i];
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uint32_t offset = OFFSET(pin_mux);
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uint8_t index = INDEX(pin_mux);
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/* Check if this is an analog or i2c type pin */
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switch (TYPE(pin_mux)) {
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@ -44,7 +62,8 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
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__ASSERT_NO_MSG(TYPE(pin_mux) <= IOCON_TYPE_A);
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}
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/* Set pinmux */
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*(iocon + offset) = pin_mux;
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*(iocon[index] + offset) = pin_mux;
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}
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return 0;
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}
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