The code was updating net_rx->seq to make sure sdu_recv() gets the
right sequence number (seq_auth for segmented messages), however later
net_rx->seq was also used for enqueuing to the Friend Queue, causing
the queued messages to have the wrong value.
To fix this, don't update net_rx->seq, rather pass an explicit
sequence number value to sdu_recv(), which is just net_rx->seq for
unsegmented messages, and seq_auth for segmented messages.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
The 'valid' member of struct bt_gatt_ccc_cfg was redundant, since
setting 'peer' to BT_ADDR_LE_ANY does the same job. What's worse, the
handling of 'valid' was also buggy in that some places looking for
valid CCC structs only matched the address, meaning it might yield a
positive match for invalid entries.
Fix these issues by removing the 'valid' struct member, and solely
using the 'peer' member to identify valid entries. Also simplify the
code by acknowledging that no CCC entry is essentially the same as the
value '0' written to CCC.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
The main stack size was too small for this sample application
when TLS was enabled. Increasing it to 1504 bytes.
Fixes#7269
Signed-off-by: Jukka Rissanen <jukka.rissanen@linux.intel.com>
Update Kconfiglib to upstream revision da40c014398f3 (+ local Zephyr
modifications) to get commit da40c014398f3 ("Force encoding to UTF-8 by
default on Python 3") in. It sets a (configurable) UTF-8 default for
Python 3, overriding the encoding specified in the current locale.
I've decided that this is a good idea after some problem reports
unrelated to Zephyr. Running with the C locale breaks things horribly
otherwise, and the fix isn't obvious.
Plain strings aren't decoded on Python 2, so no changes are needed
there.
Related PEP: https://www.python.org/dev/peps/pep-0538/
Signed-off-by: Ulf Magnusson <ulfalizer@gmail.com>
Adds a shim layer around the imx gpio driver to adapt it to the Zephyr
gpio interface.
For now only the port 4 was tested.
Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
This was wrong in two ways, one subtle and one awful.
The subtle problem was that the IRQ lock isn't actually globally
recursive, it gets reset when you context switch (i.e. a _Swap()
implicitly releases and reacquires it). So the recursive count I was
keeping needs to be per-thread or else we risk deadlock any time we
swap away from a thread holding the lock.
And because part of my brain apparently knew this, there was an
"optimization" in the code that tested the current count vs. zero
outside the lock, on the argument that if it was non-zero we must
already hold the lock. Which would be true of a per-thread counter,
but NOT a global one: the other CPU may be holding that lock, and this
test will tell you *you* do. The upshot is that a recursive
irq_lock() would almost always SUCCEED INCORRECTLY when there was lock
contention. That this didn't break more things is amazing to me.
The rework is actually simpler than the original, thankfully. Though
there are some further subtleties:
* The lock state implied by irq_lock() allows the lock to be
implicitly released on context switch (i.e. you can _Swap() with the
lock held at a recursion level higher than 1, which needs to allow
other processes to run). So return paths into threads from _Swap()
and interrupt/exception exit need to check and restore the global
lock state, spinning as needed.
* The idle loop design specifies a k_cpu_idle() function that is on
common architectures expected to enable interrupts (for obvious
reasons), but there is no place to put non-arch code to wire it into
the global lock accounting. So on SMP, even CPU0 needs to use the
"dumb" spinning idle loop.
Finally this patch contains a simple bugfix too, found by inspection:
the interrupt return code used when CONFIG_SWITCH is enabled wasn't
correctly setting the active flag on the threads, opening up the
potential for a race that might result in a thread being scheduled on
two CPUs simultaneously.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
The smp_init() call was too early. Device and subsystem
initialization doesn't happen until after the main thread starts
running. Starting extra CPUs and allowing them to schedule threads
before their drivers are alive is a bad idea, even if it works in a
unit test.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
With fragmentation disabled echo server responds to packet fragment with
ICMPv6 message Type: "Parameter Problem (4)", Code: "unrecognized Next
Header type encountered (1)". If a fragment with payload length 15 is
received in response sent by echo server IPv6 payload length and ICMPv6
checksum are wrong. This patch solves the issue by correcting payload
length.
Signed-off-by: Ruslan Mstoi <ruslan.mstoi@intel.com>
This patch fixes the dependency chain for priviliged stack
generation. This fixes a problem when compiling after making
significant changes that would shift the privileged stack area.
Signed-off-by: Andy Gross <andy.gross@linaro.org>
The mcux dspi driver was incorrectly using the macro SPI_MODE_GET() to
parse the operation for SPI_TRANSFER_LSB. The effect of this bug was
that the driver would quietly always operate in SPI_TRANSFER_MSB mode.
Coverity-CID: 185401
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
The bt_mesh_provision() call results in the provisioning link state
being cleared, so link.conn will become NULL. Add code to store the
information of whether PB-GATT was used and use this information after
the call instead of relying on link.conn anymore at this point.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
The #ifdef protections are not needed, and in fact prevent helpers
such as IS_ENABLED() from being used when calling APIs which are
optional.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
After removing the -T linker warning for the POSIX arch
we can, and should, also treat its linker warnings as errors
Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
Modify the linker script with the command INSERT.
It instructs the linker to augment the default linker script
SECTIONS with the ones provided with the one provided in
this script.
It also modified the meaning of the -T switch, so it no longer
replaces the default linker script
Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
When a bug in the caching mechanism is detected the cache format must
be bumped to ensure that we no longer get a cache hit on old corrupted
keys.
This fixes#7246 when the cache is corrupted.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
Messages about compiler checks are very verbose so we disable them by
default. They have always been undesirably verbose, but introducing
CMAKE_REQUIRED_FLAGS into the 'check' string made them unacceptably
so.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
Fix a bug where different compiler checks were aliased and therefore
the test results were incorrectly re-used.
The 'check' string is used by CMake internally to cache test results,
but when testing linker flags the check string has been aliased
between the different linker checks. To fix the aliasing issue we add
the CMAKE_REQUIRED_FLAGS variable to the 'check' string. The aliasing
issue disappears because the linker flag-under-test is in
'CMAKE_REQUIRED_FLAGS'.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
Fix issue with Coverity using if / else instead of switch, though it
does not affect code.
Fixes: #7257
CID: 185399
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
According to IEEE 802.1Q the VLAN priority (PCP) is not directly mapped
to the network packet priority. The Best Effort priority has a PCP value
of 0. The lowest priority (Background) has a PCP value of 1.
All the values are mapped according to the following table:
+-----+-----+---------+
| PCP | PRI | Acronym |
+-----+-----+---------+
| 1 | 0 | BK |
| 0 | 1 | BE |
| 2 | 2 | EE |
| 3 | 3 | CA |
| 4 | 4 | VI |
| 5 | 5 | VO |
| 6 | 6 | IC |
| 7 | 7 | NC |
+-----+-----+---------+
Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com>
Add hardware dependencies and filters to make sure we do not explode if
for example we try to build a sample/test using rtc when the platform
does not support that.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add support to enable test application selectively based
on defconfig
Change-Id: I8111750ff099edd95ffa22c6e312999c801678ea
Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
A brief description about intel_s1000 and ways to connect,
flash, debug etc.
Change-Id: I459c64d8d9574bc3511da7f983d68e044cacc1d0
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
patch add a hid test application which sends continues
reports to the host
Change-Id: I3a638caded629b502b4cfc6c7bdcba0b67428350
Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Enable the CAVS I2S on intel_s1000. Also, introduce a test to
validate I2S in ping-pong and normal modes.
Change-Id: Iea78e22cedc7724c1c2e821c68d7030cc0a65047
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Implements the driver for Intel CAVS I2S. Only Playback
is currently supported.
Change-Id: I7b816f9736dc35e79a81d3664d6405dc0aac15b4
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Enable the CAVS DMA on intel_s1000. Also, introduce a test to
validate the DMA.
Change-Id: I2ff233c45cfd8aea55e254d905350a666aa649a0
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Introduce the Intel CAVS DMA. This is based out of the DesignWare
DMA IP but the register offset and bits have been changed in some
cases. However, the fundamental definition for the register field
has not been changed. Hence the registers begin with "DW_" to
indicate the Designware origin.
This driver currently supports the single block mode and linked list
multi-block mode. Scatter-Gather is not supported.
Change-Id: I33a8ed5141d9236167de50e14d3d407e95d6f553
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This patchset provides Xtensa's xcc compiler support for Xtensa
projects in Cmake. This requires the below environment variables
to be defined aptly. The appropriate xcc license information also
need to be supplied.
ZEPHYR_GCC_VARIANT=xcc
TOOLCHAIN_VER=RF-2015.3-linux
XTENSA_CORE=cavs21_LX6HiFi3_RF3_WB16
XTENSA_SYSTEM=/opt/xtensa/XtDevTools/install/tools/
RF-2015.3-linux/XtensaTools/config/
XTENSA_BUILD_PATHS=/opt/xtensa/XtDevTools/install/builds/
Change-Id: Ib3c10e8095439b0e32276ff37c00eca8420773ec
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This patchset creates Debug, Debugserver and Flash scripts
ensuring support in the ZephyrBinaryRunner mode.
Change-Id: Ib4f7820b1c6a045bd67cf4a031be99cf61e65eca
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This patchset carries out basic tests on the features supported
on intel_s1000. Currently, Interrupt mechanism, GPIO handling, I2C
communication and UART prints are illustrated.
Change-Id: I7ea03b5085b7fa8d29635c294038536465a70660
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
intel_s1000 has multiple levels of interrupts consisting of core, CAVS
Logic and designware interrupt controller. This patchset modifies
the regular gen_isr mechanism to support these multiple levels.
Change-Id: I0450666d4e601dfbc8cadc9c9d8100afb61a214c
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This interrupt controller is a designware IP that combines several
sources of interrupt into one line that is then routed to the parent
controller.
This implementation supports only the regular irqs with no support
for priority filtering and vectored interrupts. Firqs are also not
supported.
Change-Id: I8bdf6f8df4632b6d7e8a3ba9a77116771d034a48
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
CAVS interrupt logic is an intel IP that combines several sources of
interrupt into one line that is then routed to the parent controller.
CAVS stands for "connected Audio, Voice and Speech". This IP supports
4 lines which can have a max of 32 interrupts each.
Change-Id: Ia6be51428bedf1011d148ae1fc5d4c34252c05da
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
intel_s1000 makes use of DesignWare IP for I2C.
Change-Id: Ie091318c5959b95e1febeb5cefa440f35a6d144b
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Enable GPIO handling for intel_s1000. It uses a DesignWare IP.
Change-Id: I522534935e4ef3a56d93aca669f6de961d927481
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
__start is deemed the entry point for all architectures in Zephyr.
Accordingly, Xtensa code had to be modified a bit to fall in line
with this convention.
Change-Id: If3ed344721c9f2735378b866662a68d8d5795324
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
intel_s1000 uses DesignWare IP for UART. National Semiconductor
16550 (UART) component specification is followed in this IP.
Change-Id: Ied7df1dc178d55b6dbe71d729d6383ba07274ea4
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Setting CACHEATTR from _memmap_cacheattr_reset is making
the intel_s1000 SoC get into some unknown state. Removing
it for intel_s1000_crb for now.
Change-Id: Ib44638ef75de6200ef5c2aad55f093a633da864a
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
intel_s1000_crb board makes use of the intel_s1000 SoC. It has
a built-in ROM which gets executed upon applying power. It then
executes the secondary bootloader followed by the FW (like zephyr).
Change-Id: If334c359b4372a56997c3b2e1eb9250e80847f07
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Define memctl_default.S and memerror-vector.S files. A reference
could be found in the Xtensa toolchain directories. These are
required for using cavs21_LX6HiFi3_RF3_WB16 Xtensa CPU mainly in
simulator. On boards which have ROM, these would have been already
defined in the ROM. Hence, the contents of these files will be
developed at a later time if required.
Change-Id: Idf52397bb6880c136525e69f47e09defcba7f036
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
