drivers: interrupts: introduce CAVS interrupt logic
CAVS interrupt logic is an intel IP that combines several sources of interrupt into one line that is then routed to the parent controller. CAVS stands for "connected Audio, Voice and Speech". This IP supports 4 lines which can have a max of 32 interrupts each. Change-Id: Ia6be51428bedf1011d148ae1fc5d4c34252c05da Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Rajavardhan Gundi
Anas Nashif
parent
9cc381c07a
commit
74016bb64c
6 changed files with 399 additions and 0 deletions
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@ -7,3 +7,4 @@ zephyr_sources_ifdef(CONFIG_PIC_DISABLE i8259.c)
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zephyr_sources_ifdef(CONFIG_PLIC_FE310 plic_fe310.c)
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zephyr_sources_ifdef(CONFIG_SHARED_IRQ shared_irq.c)
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zephyr_sources_ifdef(CONFIG_SOC_FAMILY_STM32 exti_stm32.c)
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zephyr_sources_ifdef(CONFIG_CAVS_ICTL cavs_ictl.c)
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@ -130,4 +130,6 @@ source "drivers/interrupt_controller/Kconfig.stm32"
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source "drivers/interrupt_controller/Kconfig.multilevel"
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source "drivers/interrupt_controller/Kconfig.s1000"
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endmenu
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68
drivers/interrupt_controller/Kconfig.s1000
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68
drivers/interrupt_controller/Kconfig.s1000
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@ -0,0 +1,68 @@
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# Kconfig - Intel_S1000 configuration
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#
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# Copyright (c) 2017 Intel Corporation
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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config CAVS_ICTL
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bool "CAVS Interrupt Logic"
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default n
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depends on MULTI_LEVEL_INTERRUPTS
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help
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These are 4 in number supporting a max of 32 interrupts each.
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config CAVS_ISR_TBL_OFFSET
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int "Offset in the SW ISR Table"
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default 0
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depends on CAVS_ICTL
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help
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This indicates the offset in the SW_ISR_TABLE beginning from where
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the ISRs for CAVS Interrupt Controller are assigned.
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config CAVS_ICTL_0_NAME
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string "CAVS 0 Driver name"
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depends on CAVS_ICTL
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default "CAVS_0"
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config CAVS_ICTL_0_OFFSET
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hex "Parent interrupt number to which CAVS_0 maps"
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default 0x00
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depends on CAVS_ICTL
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config CAVS_ICTL_1_NAME
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string "CAVS 1 Driver name"
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depends on CAVS_ICTL
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default "CAVS_1"
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config CAVS_ICTL_1_OFFSET
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hex "Parent interrupt number to which CAVS_1 maps"
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default 0x00
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depends on CAVS_ICTL
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config CAVS_ICTL_2_NAME
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string "CAVS 2 Driver name"
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depends on CAVS_ICTL
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default "CAVS_2"
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config CAVS_ICTL_2_OFFSET
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hex "Parent interrupt number to which CAVS_2 maps"
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default 0x00
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depends on CAVS_ICTL
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config CAVS_ICTL_3_NAME
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string "CAVS 3 Driver name"
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depends on CAVS_ICTL
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default "CAVS_3"
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config CAVS_ICTL_3_OFFSET
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hex "Parent interrupt number to which CAVS_3 maps"
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default 0x00
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depends on CAVS_ICTL
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config CAVS_ICTL_INIT_PRIORITY
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int "CAVS ICTL Init priority"
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default 60
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depends on CAVS_ICTL
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help
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Cavs Interrupt Logic initialization priority.
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194
drivers/interrupt_controller/cavs_ictl.c
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194
drivers/interrupt_controller/cavs_ictl.c
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@ -0,0 +1,194 @@
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/*
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* Copyright (c) 2017 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <device.h>
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#include <board.h>
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#include <irq_nextlevel.h>
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#include "cavs_ictl.h"
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static ALWAYS_INLINE void cavs_ictl_dispatch_child_isrs(u32_t intr_status,
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u32_t isr_base_offset)
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{
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u32_t intr_bitpos, intr_offset;
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/* Dispatch lower level ISRs depending upon the bit set */
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while (intr_status) {
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intr_bitpos = find_lsb_set(intr_status) - 1;
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intr_status &= ~(1 << intr_bitpos);
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intr_offset = isr_base_offset + intr_bitpos;
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_sw_isr_table[intr_offset].isr(
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_sw_isr_table[intr_offset].arg);
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}
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}
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static void cavs_ictl_isr(void *arg)
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{
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struct device *port = (struct device *)arg;
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struct cavs_ictl_runtime *context = port->driver_data;
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const struct cavs_ictl_config *config = port->config->config_info;
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volatile struct cavs_registers * const regs =
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(struct cavs_registers *)context->base_addr;
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cavs_ictl_dispatch_child_isrs(regs->status_il,
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config->isr_table_offset);
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}
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static inline void cavs_ictl_irq_enable(struct device *dev, unsigned int irq)
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{
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struct cavs_ictl_runtime *context = dev->driver_data;
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volatile struct cavs_registers * const regs =
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(struct cavs_registers *)context->base_addr;
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regs->enable_il = (1 << irq);
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}
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static inline void cavs_ictl_irq_disable(struct device *dev, unsigned int irq)
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{
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struct cavs_ictl_runtime *context = dev->driver_data;
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volatile struct cavs_registers * const regs =
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(struct cavs_registers *)context->base_addr;
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regs->disable_il = (1 << irq);
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}
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static inline unsigned int cavs_ictl_irq_get_state(struct device *dev)
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{
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struct cavs_ictl_runtime *context = dev->driver_data;
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volatile struct cavs_registers * const regs =
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(struct cavs_registers *)context->base_addr;
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/* When the bits of this register are set, it means the
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* corresponding interrupts are disabled. This function
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* returns 0 only if ALL the interrupts are disabled.
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*/
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if (regs->disable_state_il == 0xFFFFFFFF) {
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return 0;
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}
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return 1;
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}
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static const struct irq_next_level_api cavs_apis = {
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.intr_enable = cavs_ictl_irq_enable,
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.intr_disable = cavs_ictl_irq_disable,
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.intr_get_state = cavs_ictl_irq_get_state,
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};
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static int cavs_ictl_0_initialize(struct device *port)
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{
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return 0;
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}
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static void cavs_config_0_irq(struct device *port);
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static const struct cavs_ictl_config cavs_config_0 = {
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.irq_num = CAVS_ICTL_0_IRQ,
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.isr_table_offset = CONFIG_CAVS_ISR_TBL_OFFSET,
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.config_func = cavs_config_0_irq,
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};
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static struct cavs_ictl_runtime cavs_0_runtime = {
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.base_addr = CAVS_ICTL_BASE_ADDR,
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};
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DEVICE_AND_API_INIT(cavs_ictl_0, CONFIG_CAVS_ICTL_0_NAME,
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cavs_ictl_0_initialize, &cavs_0_runtime, &cavs_config_0,
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POST_KERNEL, CONFIG_CAVS_ICTL_INIT_PRIORITY, &cavs_apis);
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static void cavs_config_0_irq(struct device *port)
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{
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IRQ_CONNECT(CAVS_ICTL_0_IRQ, CONFIG_CAVS_ICTL_0_IRQ_PRI, cavs_ictl_isr,
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DEVICE_GET(cavs_ictl_0), CAVS_ICTL_0_IRQ_FLAGS);
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}
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static int cavs_ictl_1_initialize(struct device *port)
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{
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return 0;
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}
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static void cavs_config_1_irq(struct device *port);
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static const struct cavs_ictl_config cavs_config_1 = {
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.irq_num = CAVS_ICTL_1_IRQ,
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.isr_table_offset = CONFIG_CAVS_ISR_TBL_OFFSET +
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CONFIG_MAX_IRQ_PER_AGGREGATOR,
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.config_func = cavs_config_1_irq,
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};
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static struct cavs_ictl_runtime cavs_1_runtime = {
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.base_addr = CAVS_ICTL_BASE_ADDR + sizeof(struct cavs_registers),
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};
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DEVICE_AND_API_INIT(cavs_ictl_1, CONFIG_CAVS_ICTL_1_NAME,
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cavs_ictl_1_initialize, &cavs_1_runtime, &cavs_config_1,
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POST_KERNEL, CONFIG_CAVS_ICTL_INIT_PRIORITY, &cavs_apis);
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static void cavs_config_1_irq(struct device *port)
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{
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IRQ_CONNECT(CAVS_ICTL_1_IRQ, CONFIG_CAVS_ICTL_1_IRQ_PRI, cavs_ictl_isr,
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DEVICE_GET(cavs_ictl_1), CAVS_ICTL_1_IRQ_FLAGS);
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}
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static int cavs_ictl_2_initialize(struct device *port)
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{
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return 0;
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}
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static void cavs_config_2_irq(struct device *port);
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static const struct cavs_ictl_config cavs_config_2 = {
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.irq_num = CAVS_ICTL_2_IRQ,
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.isr_table_offset = CONFIG_CAVS_ISR_TBL_OFFSET +
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CONFIG_MAX_IRQ_PER_AGGREGATOR * 2,
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.config_func = cavs_config_2_irq,
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};
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static struct cavs_ictl_runtime cavs_2_runtime = {
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.base_addr = CAVS_ICTL_BASE_ADDR + sizeof(struct cavs_registers) * 2,
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};
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DEVICE_AND_API_INIT(cavs_ictl_2, CONFIG_CAVS_ICTL_2_NAME,
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cavs_ictl_2_initialize, &cavs_2_runtime, &cavs_config_2,
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POST_KERNEL, CONFIG_CAVS_ICTL_INIT_PRIORITY, &cavs_apis);
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static void cavs_config_2_irq(struct device *port)
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{
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IRQ_CONNECT(CAVS_ICTL_2_IRQ, CONFIG_CAVS_ICTL_2_IRQ_PRI, cavs_ictl_isr,
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DEVICE_GET(cavs_ictl_2), CAVS_ICTL_2_IRQ_FLAGS);
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}
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static int cavs_ictl_3_initialize(struct device *port)
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{
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return 0;
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}
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static void cavs_config_3_irq(struct device *port);
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static const struct cavs_ictl_config cavs_config_3 = {
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.irq_num = CAVS_ICTL_3_IRQ,
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.isr_table_offset = CONFIG_CAVS_ISR_TBL_OFFSET +
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CONFIG_MAX_IRQ_PER_AGGREGATOR*3,
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.config_func = cavs_config_3_irq,
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};
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static struct cavs_ictl_runtime cavs_3_runtime = {
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.base_addr = CAVS_ICTL_BASE_ADDR + sizeof(struct cavs_registers) * 3,
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};
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DEVICE_AND_API_INIT(cavs_ictl_3, CONFIG_CAVS_ICTL_3_NAME,
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cavs_ictl_3_initialize, &cavs_3_runtime, &cavs_config_3,
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POST_KERNEL, CONFIG_CAVS_ICTL_INIT_PRIORITY, &cavs_apis);
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static void cavs_config_3_irq(struct device *port)
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{
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IRQ_CONNECT(CAVS_ICTL_3_IRQ, CONFIG_CAVS_ICTL_3_IRQ_PRI, cavs_ictl_isr,
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DEVICE_GET(cavs_ictl_3), CAVS_ICTL_3_IRQ_FLAGS);
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}
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39
drivers/interrupt_controller/cavs_ictl.h
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39
drivers/interrupt_controller/cavs_ictl.h
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@ -0,0 +1,39 @@
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/*
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* Copyright (c) 2017 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _CAVS_ICTL_H_
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#define _CAVS_ICTL_H_
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#include <zephyr/types.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef void (*cavs_ictl_config_irq_t)(struct device *port);
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struct cavs_ictl_config {
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u32_t irq_num;
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u32_t isr_table_offset;
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cavs_ictl_config_irq_t config_func;
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};
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struct cavs_ictl_runtime {
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u32_t base_addr;
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};
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struct cavs_registers {
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u32_t disable_il; /* il_msd - offset 0x00 */
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u32_t enable_il; /* il_mcd - offset 0x04 */
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u32_t disable_state_il; /* il_md - offset 0x08 */
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u32_t status_il; /* il_sd - offset 0x0C */
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};
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#ifdef __cplusplus
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}
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#endif
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#endif /* _CAVS_ICTL_H_ */
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95
include/irq_nextlevel.h
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95
include/irq_nextlevel.h
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@ -0,0 +1,95 @@
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/*
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* Copyright (c) 2017 Intel corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Public interface for configuring interrupts
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*/
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#ifndef _IRQ_NEXTLEVEL_H_
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#define _IRQ_NEXTLEVEL_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @cond INTERNAL_HIDDEN
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*
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* These are for internal use only, so skip these in
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* public documentation.
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*/
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typedef void (*irq_next_level_func_t)(struct device *dev, unsigned int irq);
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typedef unsigned int (*irq_next_level_get_state_t)(struct device *dev);
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struct irq_next_level_api {
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irq_next_level_func_t intr_enable;
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irq_next_level_func_t intr_disable;
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irq_next_level_get_state_t intr_get_state;
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};
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/**
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* @endcond
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*/
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/**
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* @brief Enable an IRQ in the next level.
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*
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* This routine enables interrupts present in the interrupt controller.
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*
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* @param dev Pointer to the device structure for the driver instance.
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* @param irq IRQ to be enabled.
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*
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* @return N/A
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*/
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static inline void irq_enable_next_level(struct device *dev, u32_t irq)
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{
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const struct irq_next_level_api *api = dev->driver_api;
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api->intr_enable(dev, irq);
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}
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/**
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* @brief Disable an IRQ in the next level.
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*
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* This routine disables interrupts present in the interrupt controller.
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*
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* @param dev Pointer to the device structure for the driver instance.
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* @param irq IRQ to be disabled.
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*
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* @return N/A
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*/
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static inline void irq_disable_next_level(struct device *dev, u32_t irq)
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{
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const struct irq_next_level_api *api = dev->driver_api;
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api->intr_disable(dev, irq);
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}
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/**
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* @brief Get IRQ enable state.
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*
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* This routine indicates if any interrupts are enabled in the interrupt
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* controller.
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*
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* @param dev Pointer to the device structure for the driver instance.
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*
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* @return interrupt enable state, true or false
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*/
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static inline unsigned int irq_is_enabled_next_level(struct device *dev)
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{
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const struct irq_next_level_api *api = dev->driver_api;
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return api->intr_get_state(dev);
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}
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* _IRQ_NEXTLEVEL_H_ */
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