This initial support of L2C driver only contains cache enable and HW
capability checking. Cache management operation isn't supported yet
in this driver.
Signed-off-by: Jim Shu <cwshu@andestech.com>
Andes V5 PMA can let SW programmably configure memory attribute of
physical memory region. This commit enable CONFIG_NOCACHE_MEMORY of
Andes V5 CPUs based on the PMA. Use PMA region 0 to set whole nocache
section as uncached memory.
Signed-off-by: Jim Shu <cwshu@andestech.com>
Support custom RISC-V CSR context switch for Andes V5 CPUs.
Both AndeStar V5 DSP and PowerBrake features have it's own CSR to be
saved for thread and ISR context, so adding these CSRs into the RISC-V
SOC context management framework (CONFIG_RISCV_SOC_CONTEXT_SAVE).
Signed-off-by: Jim Shu <cwshu@andestech.com>
Add andes_v5 SoC series and andes_ae350 SoC. It includes
soc initialization code, linker script, and custom CSR encoding.
Signed-off-by: Jim Shu <cwshu@andestech.com>
This is the initial version of a Zephyr CMake linker file for the arm
architecture.
This file defines memory regions, groups, linker sections and symbols
for the arm architecture.
It also sources the common common-ram.cmake, common-rom.cmake,
debug-sections,cmake, and thread-local-storage.cmake.
It configure sections for SoC families using zephyr_linker_sources()
functions:
- nxp_imx
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
For IMX, for timer interrupt, the interrupt handler
was not the correct one executed and that’s because
the handlers were not at the expected address.
For IMX the size constraint of the interrupt vector
table entry is 0x1C bytes of code, less than usual.
I've added a small indirection to bypass this size
constraint and moved the default handlers to the end
of vector table, renaming them to
_Level\LVL\()VectorHelper.
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Add a common part for all i.MX boards.
Add support for i.MX8, which represents i.MX8QM.
This has a 1 Xtensa HiFi4 core, with 64 KB TCM,
448 KB OCRAM, 8MB SDRAM and 1 ESAI, 1 SAI as
audio interfaces.
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Cleanup and preparation commit for linker script generator.
Zephyr linker scripts provides start and end symbols for each larger
areas in the linker script.
The symbols _image_text_start and _image_text_end sometimes includes
linker/kobject-text.ld. This mean there must be both the regular
__text_start and __text_end symbols for the pure text section, as well
as <group>_start and <group>_end symbols.
The symbols describing the text region which covers more than just the
text section itself will thus be changed to:
_image_text_start -> __text_region_start
_image_text_end -> __text_region_end
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Cleanup and preparation commit for linker script generator.
Zephyr linker scripts provides start and end symbols for each larger
areas in the linker script.
The symbols _image_rom_start and _image_rom_end corresponds to the group
ROMABLE_REGION defined in the ld linker scripts.
The symbols _image_rodata_start and _image_rodata_end is not placed as
independent group but covers common-rom.ld, thread-local-storage.ld,
kobject-rom.ld and snippets-rodata.ld.
This commit align those names and prepares for generation of groups in
linker scripts.
The symbols describing the ROMABLE_REGION will be renamed to:
_image_rom_start -> __rom_region_start
_image_rom_end -> __rom_region_end
The rodata will also use the group symbol notation as:
_image_rodata_start -> __rodata_region_start
_image_rodata_end -> __rodata_region_end
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Cleanup and preparation commit for linker script generator.
Zephyr linker scripts provides start and end symbols for each section,
and sometimes even size and LMA start symbols.
Generally, start and end symbols uses the following pattern, as:
Section name: foo
Section start symbol: __foo_start
Section end symbol: __foo_end
However, this pattern is not followed consistently.
To allow for linker script generation and ensure consistent naming of
symbols then the following pattern is introduced consistently to allow
for cleaner linker script generation.
Section name: foo
Section start symbol: __foo_start
Section end symbol: __foo_end
Section size symbol: __foo_size
Section LMA start symbol: __foo_load_start
This commit aligns the symbols for _data_ram/rom to other symbols and in
such a way they follow consistent pattern which allows for linker script
and scatter file generation.
The symbols are named according to the section name they describe.
Section name is `data`
A new group named data_region is introduced which instead spans all the
input and output sections that was previously covered by
__data_ram_start, __data_ram_end, and __data_rom_start.
The following symbols are aligned in this commit:
- __data_ram_start -> __data_region_start
- __data_ram_end -> __data_region_end
- __data_rom_start -> __data_region_load_start
The following new symbols are introduced so that the data section is
aligned with other sections:
- __data_end
- __data_start
value identical to __data_region_start but describes start of
the section.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
We add support of mpu v6 therefore it is needed to have a board to
validate that feature. This commit add a new HS nsim simulator
which supports mpu v6.
Signed-off-by: Yuguo Zou <yuguo.zou@synopsys.com>
Move the IDT_LIST memory region to the location recommended by
`intlist.ld`. The documentation specifies that this region should not
overlap other regions, and there is no guarantee that the area after the
`SRAM` region is not used. The end of the address space is much less
likely to be a valid RAM address.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Define soc_interrupt_init as a weak symbol in the common RISC-V
privileged instruction set SoC support.
This allows overriding soc_interrupt_init for SoCs which are not fully
compliant with the RISC-V privileged specification.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Define __soc_handle_irq as a weak symbol in the common RISC-V privileged
instruction set SoC support.
This allows overriding __soc_handle_irq for SoCs which are not fully
compliant with the RISC-V privileged specification.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Follow up on commit bfd45e5b8c
("drivers: remove Kconfig option CONFIG_UART_CONSOLE_ON_DEV_NAME")
Remove Kconfig options
CONFIG_BT_UART_ON_DEV_NAME and CONFIG_BT_MONITOR_ON_DEV_NAME
since all UART drivers are converted to devicetree and we can just use
DEVICE_DT_GET(DT_CHOSEN(zephyr_bt_uart)) and
DEVICE_DT_GET(DT_CHOSEN(zephyr_bt_mon_uart)).
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Microchip MEC172x series I2C driver implementing controller
and target modes. The driver implemenents its own I2C port
pin control functions and does not depended upon pinmux. Future
updates will make use of PINCTRL when that subystem is finalized.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Add Kconfig options that allow users to select the way the APPROTECT
mechanism is handled in the SystemInit() function.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
esp32c3 has already supported RISC-V GP, just apply new kconfig option
to it. Forcely select CONFIG_RISCV_GP in esp32c3 at first because it
seems to be necessary in the esp32c3 SoC.
Signed-off-by: Jim Shu <cwshu@andestech.com>
Add norelax option before initializing GP at common entry point.
Remove __global_pointer$ symbol in the SoC linker script because it's
in the arch one. Remove -mno-relax when GP support is enabled.
Signed-off-by: Jim Shu <cwshu@andestech.com>
Initialize GP at common entry point of riscv-privilege SoCs so that
this commit add GP support of these SoCs at once.
As some privilege SoCs want to customize the entry point, they should
disable linker relaxation by `.norelax option` before entrying the
common entry point `__start`.
Signed-off-by: Jim Shu <cwshu@andestech.com>
Creating static libraries for drivers moves some symbols out of IRAM.
This change fixes it.
Signed-off-by: Shubham Kulkarni <shubham.kulkarni@espressif.com>
Creating static libraries for drivers moves some symbols out of IRAM.
This change fixes it.
Signed-off-by: Shubham Kulkarni <shubham.kulkarni@espressif.com>
Creating static libraries for drivers moves some symbols out of IRAM.
This change fixes it.
Signed-off-by: Shubham Kulkarni <shubham.kulkarni@espressif.com>
1. Update soc.c file to add USB clock setup
2. Add a linker script file to move USB transfer
buffer and controller buffers to USB RAM
3. Update Kconfig's to add USB support
4. Add zephyr_udc0 nodelabel
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
1. Update soc.c file to add USB clock setup
2. Add a linker script file to move USB transfer
buffer and controller buffers to USB RAM
3. Update Kconfig's to add USB support
4. Add zephyr_udc0 nodelabel
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
The USB config name has changed to USB_MCUX and the
device tree node name has changed from nxp_kinetis_usbd
to nxp_mcux_usbd
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
The delay will ensure last byte has been latched in before
This also change the method of reading status register from re-send
read status command on each read to read status register continuously.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
log and libc optimization default config are soc related
and should be moved out from board context.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This reverts commit 7b09d031fa. Because
context save of GP register is removed, we don't need to initialize GP
at thread init. GP will be a constant value so that it could only be
initialized at program start.
Signed-off-by: Jim Shu <cwshu@andestech.com>
The way we currently handle direction finding extension (DFE) support
on Nordic nRF5 controllers relies on required devicetree properties
related to DFE in the "nordic,nrf-radio" node.
That doesn't make sense on radios without DFE support, though.
Any .dtsi for an SoC without DFE support which has such a node would
require extraneous DFE related properties like dfe-antenna-num.
Instead of making the properties required, mark them optional. We
indicate the presence of DFE support via a new 'dfe-supported' boolean
property which the SoC .dtsi files can set (or not) depending on
support.
This gives us the opportunity to do some cleanup in the Kconfig,
removing CONFIG_HAS_HW_NRF_RADIO_BLE_DF since we know from the
devicetree whether DFE support is available.
Handle that change appropriately in radio_df.c. This gives us an
opportunity to improve readability in the devicetree-related macro
magic in that file.
Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
This commit enables the ARM DSP extension on the MPS2 AN521 SoC CPU1
(the CPU1 supports both FPU and DSP).
With this change, the CMSIS-DSP tests running on the
`mps2_an521_remote` board will use the DSP instructions.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
