Timer "drivers" do not use the device model infrastructure, they are
singletons with a SYS_INIT call. This means they do not have to include
device.h but init.h. Things worked because device.h includes init.h.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Now that everything is in place, the prescaler value picked from dts is
used to properly configure the clock.
The code is moved into its own function.
There are four main cases:
- F1 and F37x don't have prescaler (in ADC register) so nothing is done.
- F0 only has individual registers.
- C0, G0, L0, WB1x and WL have both invidual and common registers. The
individual one is used to define either synchronous mode with its
prescaler, or asynchronous mode. The common one is only used to store
the value of the asynchronous prescaler.
- All others only have a common register where both the mode and the
prescaler is stored.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Get the STM32 ADC prescaler data from dts to create the appropriate LL
macro to use for the ADC clock.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Current setup tries to initialize the bank driver before the parent one,
which is the inverse of what the devicetree hierarchy implies and
causes a bunch of:
ERROR: /soc/gpio@e000a000/psgpio_bank@3 PRE_KERNEL_1 40 32 <
/soc/gpio@e000a000 PRE_KERNEL_2 40 10
Change the bank driver to initialize at PRE_KERNEL_1 as the parent
drivers so that ordinals take care of priority between these two.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Fix a build error:
crypto_it8xxx2_sha.c:99:26: warning: declaration of 'i' shadows a
previous local [-Wshadow]
99 | for (int i = 0; i < ARRAY_SIZE(sha256_k); i++) {
| ^ crypto_it8xxx2_sha.c:88:13: note:
shadowed declaration is here
88 | int i;
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Fix a few issues with the reset-gpio functionality in spi_nor, missing
header, missing semicolon, unnecessary and not working condition on a
struct field that is not a pointer.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The previous implementation called k_usleep to wait if the fifo was not
empty. This leads to an exception if called from an ISR (e.g. for
for logging).
In addition to that, the k_usleep leads to noticeable interruptions
when printing strings longer than the 64 bytes of the fifo.
With this commit, the function will busy-wait until all characters are
sent or if the timeout is reached. The timeout will only be reached if
no USB host is connected to the port. After the timeout is reached
once, the function will return immediately for subsequent calls
(dropping the characters to be sent) until the USB host is connected
again.
Fixes#60825
Signed-off-by: Martin Jäger <martin@libre.solar>
Fix a shadow variable build error:
wdt_andes_atcwdt200.c:112:49: warning: declaration of 'counter_dev'
shadows a global declaration [-Wshadow]
112 | static void wdt_counter_cb(const struct device *counter_dev,
uint8_t chan_id, |
~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~ wdt_andes_atcwdt200.c:95:35: note:
shadowed declaration is here
95 | static const struct device *const counter_dev = |
^~~~~~~~~~~
Make the outer variable more specific rather than the local one.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Change the power_domain_intel_adsp initialization priority so that it
initializes after the DMA driver that it depends on.
Fixes a few:
ERROR: /soc/dma@72c00 POST_KERNEL 40 69 <
/soc/dfpmccu@71b00/hst_domain POST_KERNEL 75 65
ERROR: /soc/dma@72400 POST_KERNEL 40 66 <
/soc/dfpmccu@71b00/hst_domain POST_KERNEL 75 65
...
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Fix CONTAINER_OF usage in gpio_keys_interrupt, this should go first to
struct gpio_keys_callback and then to struct gpio_keys_pin_data. It
happens to work right now because cb_data is the first field.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Fix few instances of delayable work handlers using the k_work pointer
directly in a CONTAINER_OF pointing to a k_work_delayable.
This is harmless since the k_work is the first element in
k_work_delayable, but using k_work_delayable_from_work is the right way
of handling it.
Change a couple of explicit CONTAINER_OF doing the same work as the
macro in the process.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
"callback != NULL" is used to determine if the callback is in use.
The TX complete semaphone should only be given back after setting the
callback to NULL.
This would likely only be a race condition if the ISR is processed on a
different core to the TX call.
Signed-off-by: Grant Ramsay <gramsay@enphaseenergy.com>
The MCAN driver operates in TX queue mode (TXBC.TFQM = 1). In this mode
TXFQS.TFQPI returns the first available buffer (usually buffer zero).
Hardware is free to re-use a buffer as soon as TX completes, it does not
have to wait for the matching TX event to be processed.
If a TX completes and that TX buffer is re-used before processing the TX
event, two TX events for the same buffer occur. The first event calls the
second events TX callback, and the second event results in a NULL pointer
exception.
In a "normal" configuration, the TX event ISR will always preempt the
queuing of a TX frame to the same TX buffer.
However, this issue could occur if:
* Sending a message with ISRs temporarily disabled.
* The ISR is processed on a different core to the TX call.
The fix is to manually track which TX buffers are available, only freeing
a buffer after the TX event has been processed.
The MCAN user manual states that this is allowed:
"The application may use register TXBRP instead of the Put Index and may
place messages to any Tx Buffer without pending transmission request"
Signed-off-by: Grant Ramsay <gramsay@enphaseenergy.com>
Move workaround methods for npcx series to soc init functions. If
there's no workaround for this series, drop its soc.c file directly.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
The full scale prop was incorrectly using the enum idx which was then
to be used with a look up table which used the actual range number.
This changes it to use the int directly from the dts.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
This gpio data register and keyboard scan out register are shared
register. To prevent race condition caused by access from different
thread, add critical section.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Added configuration of termination current and trickle voltage
Added option to bypass low voltage charge inhibit
Added option to disable automatic recharge
Signed-off-by: Andy Sinclair <andy.sinclair@nordicsemi.no>
Some log messages could be too noisy, especially if the sensor shell was
used which would call all attr and samples even though just a few are
supported.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
For now clock can be read and written.
Clock can be set in full iso8601 time format, like 2023-12-24T12:45:56
or by just providing either data or time
Alarms not accessible
Signed-off-by: Kim Bøndergaard <kim.bondergaard@prevas.dk>
It mirrors the functionality of the vl53l0x driver.
Also removes an assert not needed, as the channel is checked.
Signed-off-by: Daniel Stuart <daniel.stuart14@gmail.com>
CONFIG_COVERAGE has been incorrectly used to
change other kconfig options (stack sizes, etc)
code defaults, as well as some samples behaviour,
which should not have dependend on it.
Instead those should have depended on COVERAGE_GCOV,
which, being the one which adds special code and
temporary RAM storage for embedded targets,
require changes to many features.
When building for the native targets, all this was
unnecessary.
=> Fix the dependency.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
CONFIG_NOCACHE_MEMORY is a valid way of declaring buffers in
nocache regions. Consider them valid in the stm32 SPI driver
nocache check. Also, don't check NULL buffers as the SPI
interface states that such buffers will result in sending
zeroes.
Signed-off-by: Daniel Gaston Ochoa <dgastonochoa@gmail.com>
Increase the default init priority of nct38xx so that they work well
with the default I2C init priority (50).
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The CMSIS module glue code was part of arch/ directory. Move it to
modules/cmsis, and provide a single entry point for it: cmsis_core.h.
This entry header will include the right CMSIS header (M or A/R).
To make this change possible, CMSIS module Kconfig/CMake are declared as
external, allowing us to add a new Zephyr include directory.
All files including CMSIS have been updated.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
This CL introduces new Flash Interface Unit (FIU) hardware in npcx4
series. The different operations of npcx9 and npcx4 FIU include:
1. 4-byte mode support for DRA mode move to SPI_DEV reg
2. To access the second flash in DRA mode, we need to configure
SPI_DEV_SEL field in BURST_CFG additionally.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
This CL introduces new clock architectures in npcx4 series and wraps
clock configurations of different series by device tree files.
For example, the PWDWN_CTLx reg initialization relies on `pwdwn-ctl-val`
prop of pcc DT node now.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
The return variable rc in sbs_gauge_do_battery_cutoff() needs to
be initialized, or else it would return random value if the for
loop is never entered.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
channel_get was doing using floating point constants with it's calculation.
The result is changed to be a float as this was generating a double
promotion warning.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
