Change format in various shell_error calls from int to long unsigned
int.
Warning:
warning: format '%d' expects argument of type 'int', but argument
6 has type 'long unsigned int'
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
When user only use pb-gatt provisioning, which unable to
send out connectable advertising, due to adv thread not started.
Signed-off-by: Lingao Meng <menglingao@xiaomi.com>
After commit eeb15aa393 ("timer: hpet: enable 64 bit mode for
better usages") was applied, main thread stack usage on qemu_x86
platform increased from 984 to 1040 bytes.
Default stack size, which is 1024, is no longer enough. Change that to
1536 to make sure this sample runs correctly on qemu_x86.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
When QEMU is running in icount mode, the behaviour regarding
the CPU being in sleep mode is configurable, with the default
value being set to 'off'. In this case, instruction counting
continues even when the CPU is sleeping or no target time is
set in the system timer. If the sleep parameter is set to
'on', instruction counting stops if the CPU is sleeping, and
the instruction count will fast-forward directly to the next
target time once it is being set.
In the Xilinx derivative of QEMU (which simulates ZynqMP and
Zynq-7000 SoCs), the default configuration causes QEMU to no
longer accept control commands via the console or remotely
whenever Zephyr enters and remains in idle mode.
Therefore, this commit makes the value of the sleep para-
meter of the icount functionality configurable, with the
default value remaining 'off'. The value can be changed at
board level alongside with the specification of the icount
shift value.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@Weidmueller.com>
Enable the existing aarch32 Cortex-R implementation of
timestamp_serialize() for aarch32 Cortex-A CPUs as well.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@Weidmueller.com>
Add consideration of aarch32 Cortex-A CPUs to a test case in which
architecture-specific assembly instructions are used in order to
explicitly trigger an exception. This test case already considers
aarch32 Cortex-R CPUs, the same instruction will be used by
Cortex-A CPUs.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@Weidmueller.com>
Add the inclusion of the Common Peripheral Access Layer for aarch32
Cortex-A SoCs in combination with the respective SoC's header file,
in which the feature flags evaluated in core_ca.h must be provided.
The corresponding CMSIS include path is added to the build by setting
the HAS_CMSIS_CORE_A Kconfig item for all aarch32 Cortex-A CPUs.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@Weidmueller.com>
Fixes interrupt-driven operation. With the previous way of
handling the TX FIFO and the interrupt flags, the operation
of the UART was prone to stalling when using it as the
console I/O device.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
The qemu_cortex_a9 target simulates the Xilinx Zynq-7000
in a single core configuration with 512 MB of RAM. Supported
peripherals are the Zynq's two UARTs, of which one is activated
for console use, and the two Ethernet controllers, of which
GEM0 can be linked to the local zeth interface.
This target uses Xilinx' fork of QEMU, which is already being
used by the qemu_cortex_r5 target. Although being labelled
'arm64', this version of QEMU is also capable of emulating the
Zynq-7000 based on a binary device tree file. While regular
QEMU provides a Zynq-based machine, this implementation is
buggy and/or incomplete.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
Introduce support for On-Chip Memory (OCM) areas in aarch32 Cortex-A
SoCs. This memory area is suitable for, amongst other things, un-
cached device DMA. The OCM memory can reside either at address zero
or at a high memory address, with configuration of the memory's lo-
cation similar to the configuration of the location of the exception
vectors. In both cases, it must be assured that the low/high OCM
area declaration doesn't overlap with the exception vectors memory
page at either the low/high address. Therefore, all possible OCM
location options shall be described in the SoC's device tree, the
current location shall be indicated via a "chosen" entry in the
target board's device tree.
This commit contains the necessary changes to the linker-related
files as well as the static region declaration for the MMU in-
itialization in the Zynq-7000 SoC-specific init code.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
Add support for the Xilinx Zynq-7000 SoC family to this driver. This
includes some SoC-specific register accesses when setting an updated
TX clock divider, also, the device tree binding now supports higher
MDC clock divisor values when the current target SoC is a Zynq rather
than a ZynqMP.
With regards to the use of this driver in a QEMU simulation of the
Zynq-7000, the Kconfig file is modified so that the driver is not
enabled unless QEMU networking is set to Ethernet mode.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
Add SoC-specific code, the basic device tree and Kconfig data as well
as the corresponding linker command file for the Xilinx Zynq-7000
family of SoCs. This SoC - either as a QEMU simulation or on actual
hardware such as the Avnet/Digilent ZedBoard - is suitable as an ini-
tial target for the ARMv7 Cortex-A support.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
Modification of the ARM architected timer driver and its configuration
data in order to address an erratum which exists at least in the Cor-
tex-A9 CPU, and which can also be observed in the QEMU implementation
of the Cortex-A9.
Comp.: ARM Cortex-A9 processors Software Developer Errata Notice
ARM document ID032315
Erratum 740657
This erratum causes a spurious interrupt pending indication with the
interrupt controller if no new compare value is written within the
timer ISR before the interrupt is cleared. This is usually the case
in tickless mode. If the spurious interrupt is not prevented, the
timer ISR will be called twice, but on second execution, the pending
flag is not set within the timer's register space. Not handling this
issue will lead to erratic tick announcements to the kernel.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
Modify #ifdefs so that any code that is compiled if CONFIG_ARMV7_R is
set is also compiled if CONFIG_ARMV7_A is set.
Modify #ifdefs so that any code that is compiled if CONFIG_CPU_CORTEX_R
is set is also compiled if CONFIG_CPU_AARCH32_CORTEX_A is set.
Modify source dir inclusion in CMakeLists.txt accordingly.
Brief file descriptions have been updated to include Cortex-A whereever
only Cortex-M and Cortex-R were mentioned so far.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
An initial implementation for memory management using the ARMv7 MMU.
A single L1 translation table for the whole 4 GB address space is al-
ways present, a configurable number of L2 page tables are linked to
the L1 table based on the static memory area configuration at boot
time, or whenever arch_mem_map/arch_mem_unmap are called at run-time.
Currently, a CPU with the Multiprocessor Extensions and execution at
PL1 are always assumed. Userspace-related features or thread stack
guard pages are not yet supported. Neither are LPAE, PXN or TEX re-
mapping. All mappings are currently assigned to the same domain. Re-
garding the permissions model, access permissions are specified using
the AP[2:1] model rather than the older AP[2:0] model, which, accor-
ding to ARM's documentation, is deprecated and should no longer be
used. The newer model adds some complexity when it comes to mapping
pages as unaccessible (the AP[2:1] model doesn't support explicit
specification of "no R, no W" permissions, it's always at least "RO"),
this is accomplished by invalidating the ID bits of the respective
page's PTE.
Includes sources, Kconfig integration, adjusted CMakeLists and the
modified linker command file (proper section alignment!).
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
The configuration bits ATCMPCEN, B0TCMPCEN and B1TCMPCEN in the ACTLR
register referenced in the function z_arm_tcm_disable_ecc are only de-
fined for Cortex-R CPUs. For Cortex-A CPUs, those bits are declared
as reserved.
Comp.: https://arm-software.github.io/CMSIS_5/Core_A/html/group__CMSIS__ACTLR.html
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
List of improvements:
- The PM logging module was only available if CONFIG_PM=y, however, it
was also used by Device PM (which can be selected without PM). A new
logging module has been created for Device PM.
- Log level is passed to LOG_MODULE_(DECLARE|REGISTER)
- Logger name has been adjusted to `pm` (was `power`)
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
POLL is not a dependency of runtime device PM since it now uses
conditional variables to notify waiting threads.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
SYS_POWER_MANAGEMENT and DEVICE_POWER_MANAGEMENT were deprecated in
2.5.0, remove them now.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Enables ADC1 on the RT1020 evaluation board. Channels 10 and 11 of this
ADC are exposed as pins 1 and 2 of J18 on the evk.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Enables ADC on RT1015 evaluation board. Channels 1 and 13 are exposed as
pins 2 and 1 of J18 on the EVK.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Added ADC support to RT1010 evaluation board. ADC channels 1 and 2 are
exposed as pins 10 and 12 of J26.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Adds ADC support to RT1024 EVK. ADC channels 10 and 11 are enabled as
pins 2 and 4 on J18 of the evaluation board
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Enables the ADC on the RT1060 evaluation board. Channels 0 and 15 of
ADC1 are available on pins 1 and 0 of J23, respectively.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Fix compilation error for devices where ssize_t can not
be formatted with %d, due to ssize_t not being equal int.
Fixes#39629
Signed-off-by: Dominik Ermel <dominik.ermel@nordicsemi.no>
Previously the host would handle disconnecting associated CISes and
invoking callbacks when a host ACL conn was disconnected.
This responsibility has now been moved to the controller, which needs to
send a NODE_RX_TYPE_TERMINATE with the CIS handle for proper
disconnection in the host. This is in accordance with the spec.
As disconnect reason, the CIS uses the ACL reason, which is passed to
the host along with the handle.
Signed-off-by: Morten Priess <mtpr@oticon.com>
This add access to modules/hal/gigadevice with three firmware
libraries by updating west.yaml file:
- GD32E10X ARM (Cortex-M4F)
- GD32F403 ARM (Cortex-M4F)
- GD32VF103 RISC-V (Nucleisys Bumblebee core)
It introduce module/hal_gigadevice, which contains all Cmake
and Kconfig rules to build GigaDevice SoCs into zephyr main
tree.
Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
