arch: arm: core: aarch32: enable ARMv7-R/Cortex-R code for ARMv7-A/Cortex-A
Modify #ifdefs so that any code that is compiled if CONFIG_ARMV7_R is set is also compiled if CONFIG_ARMV7_A is set. Modify #ifdefs so that any code that is compiled if CONFIG_CPU_CORTEX_R is set is also compiled if CONFIG_CPU_AARCH32_CORTEX_A is set. Modify source dir inclusion in CMakeLists.txt accordingly. Brief file descriptions have been updated to include Cortex-A whereever only Cortex-M and Cortex-R were mentioned so far. Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
This commit is contained in:
parent
70c403c215
commit
c6141c49c1
13 changed files with 42 additions and 34 deletions
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@ -30,5 +30,6 @@ add_subdirectory_ifdef(CONFIG_ARM_MPU mpu)
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add_subdirectory_ifdef(CONFIG_ARM_AARCH32_MMU mmu)
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add_subdirectory_ifdef(CONFIG_CPU_CORTEX_R cortex_a_r)
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add_subdirectory_ifdef(CONFIG_CPU_AARCH32_CORTEX_A cortex_a_r)
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zephyr_linker_sources(ROM_START SORT_KEY 0x0vectors vector_table.ld)
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@ -6,7 +6,7 @@
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/**
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* @file
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* @brief ARM Cortex-M and Cortex-R power management
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* @brief ARM Cortex-A, Cortex-M and Cortex-R power management
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*
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*/
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@ -135,7 +135,8 @@ SECTION_FUNC(TEXT, arch_cpu_atomic_idle)
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/* r0: interrupt mask from caller */
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#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) \
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|| defined(CONFIG_ARMV7_R)
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|| defined(CONFIG_ARMV7_R) \
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|| defined(CONFIG_ARMV7_A)
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/* No BASEPRI, call wfe directly
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* (SEVONPEND is set in z_arm_cpu_idle_init())
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*/
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@ -6,7 +6,7 @@
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/**
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* @file
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* @brief ARM Cortex-M and Cortex-R interrupt management
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* @brief ARM Cortex-A, Cortex-M and Cortex-R interrupt management
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*
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*
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* Interrupt management: enabling/disabling and dynamic ISR
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@ -18,7 +18,8 @@
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#include <arch/cpu.h>
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#if defined(CONFIG_CPU_CORTEX_M)
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#include <arch/arm/aarch32/cortex_m/cmsis.h>
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#elif defined(CONFIG_CPU_CORTEX_A) || defined(CONFIG_CPU_CORTEX_R)
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#elif defined(CONFIG_CPU_AARCH32_CORTEX_A) \
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|| defined(CONFIG_CPU_CORTEX_R)
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#include <drivers/interrupt_controller/gic.h>
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#endif
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#include <sys/__assert.h>
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@ -92,7 +93,8 @@ void z_arm_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags)
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NVIC_SetPriority((IRQn_Type)irq, prio);
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}
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#elif defined(CONFIG_CPU_CORTEX_A) || defined(CONFIG_CPU_CORTEX_R)
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#elif defined(CONFIG_CPU_AARCH32_CORTEX_A) \
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|| defined(CONFIG_CPU_CORTEX_R)
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/*
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* For Cortex-A and Cortex-R cores, the default interrupt controller is the ARM
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* Generic Interrupt Controller (GIC) and therefore the architecture interrupt
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@ -162,7 +164,8 @@ void z_irq_spurious(const void *unused)
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void _arch_isr_direct_pm(void)
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{
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#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) \
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|| defined(CONFIG_ARMV7_R)
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|| defined(CONFIG_ARMV7_R) \
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|| defined(CONFIG_ARMV7_A)
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unsigned int key;
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/* irq_lock() does what we wan for this CPU */
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@ -185,7 +188,8 @@ void _arch_isr_direct_pm(void)
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}
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#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) \
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|| defined(CONFIG_ARMV7_R)
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|| defined(CONFIG_ARMV7_R) \
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|| defined(CONFIG_ARMV7_A)
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irq_unlock(key);
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#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
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__asm__ volatile("cpsie i" : : : "memory");
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@ -7,7 +7,7 @@
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/**
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* @file
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* @brief ARM Cortex-M and Cortex-R wrapper for ISRs with parameter
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* @brief ARM Cortex-A, Cortex-M and Cortex-R wrapper for ISRs with parameter
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*
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* Wrapper installed in vector table for handling dynamic interrupts that accept
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* a parameter.
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@ -48,7 +48,7 @@ SECTION_FUNC(TEXT, _isr_wrapper)
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#if defined(CONFIG_CPU_CORTEX_M)
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push {r0,lr} /* r0, lr are now the first items on the stack */
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#elif defined(CONFIG_CPU_CORTEX_R)
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#elif defined(CONFIG_CPU_CORTEX_R) || defined(CONFIG_CPU_AARCH32_CORTEX_A)
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#if defined(CONFIG_USERSPACE)
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/* See comment below about svc stack usage */
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@ -164,7 +164,7 @@ _idle_state_cleared:
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/* clear kernel idle state */
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strne r1, [r2, #_kernel_offset_to_idle]
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blne z_pm_save_idle_exit
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#elif defined(CONFIG_ARMV7_R)
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#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A)
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beq _idle_state_cleared
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movs r1, #0
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/* clear kernel idle state */
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@ -191,7 +191,7 @@ _idle_state_cleared:
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sub r0, r0, #16 /* get IRQ number */
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lsl r0, r0, #3 /* table is 8-byte wide */
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#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
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#elif defined(CONFIG_CPU_CORTEX_R)
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#elif defined(CONFIG_CPU_CORTEX_R) || defined(CONFIG_CPU_AARCH32_CORTEX_A)
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/* Get active IRQ number from the interrupt controller */
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#if !defined(CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER)
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bl arm_gic_get_active
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@ -233,7 +233,7 @@ _idle_state_cleared:
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ldm r1!,{r0,r3} /* arg in r0, ISR in r3 */
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blx r3 /* call ISR */
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#if defined(CONFIG_CPU_CORTEX_R)
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#if defined(CONFIG_CPU_CORTEX_R) || defined(CONFIG_CPU_AARCH32_CORTEX_A)
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spurious_continue:
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/* Signal end-of-interrupt */
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pop {r0, r1}
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@ -242,7 +242,7 @@ spurious_continue:
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#else
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bl z_soc_irq_eoi
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#endif /* !CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER */
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#endif /* CONFIG_CPU_CORTEX_R */
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#endif /* CONFIG_CPU_CORTEX_R || CONFIG_CPU_AARCH32_CORTEX_A */
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#ifdef CONFIG_TRACING_ISR
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bl sys_trace_isr_exit
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@ -253,7 +253,7 @@ spurious_continue:
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mov lr, r3
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#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
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pop {r0, lr}
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#elif defined(CONFIG_ARMV7_R)
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#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A)
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/*
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* r0 and lr_irq were saved on the process stack since a swap could
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* happen. exc_exit will handle getting those values back
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@ -20,7 +20,7 @@
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#include <kernel_internal.h>
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#include <linker/linker-defs.h>
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#if defined(CONFIG_ARMV7_R)
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#if defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A)
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#include <aarch32/cortex_a_r/stack.h>
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#endif
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@ -166,6 +166,7 @@ static inline void z_arm_floating_point_init(void)
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#endif /* CONFIG_CPU_HAS_FPU */
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extern FUNC_NORETURN void z_cstart(void);
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/**
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*
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* @brief Prepare to and run C code
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@ -182,7 +183,7 @@ void z_arm_prep_c(void)
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#endif
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z_bss_zero();
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z_data_copy();
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#if defined(CONFIG_ARMV7_R) && defined(CONFIG_INIT_STACKS)
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#if ((defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A)) && defined(CONFIG_INIT_STACKS))
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z_arm_init_stacks();
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#endif
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z_arm_interrupt_init();
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@ -42,7 +42,7 @@ int arch_swap(unsigned int key)
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/* clear mask or enable all irqs to take a pendsv */
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irq_unlock(0);
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#elif defined(CONFIG_CPU_CORTEX_R)
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#elif defined(CONFIG_CPU_CORTEX_R) || defined(CONFIG_CPU_AARCH32_CORTEX_A)
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z_arm_cortex_r_svc();
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irq_unlock(key);
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#endif
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@ -11,7 +11,7 @@
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* @brief Thread context switching for ARM Cortex-M and Cortex-R
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*
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* This module implements the routines necessary for thread context switching
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* on ARM Cortex-M and Cortex-R CPUs.
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* on ARM Cortex-A, Cortex-M and Cortex-R CPUs.
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*/
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#include <toolchain.h>
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@ -120,7 +120,7 @@ out_fp_endif:
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* regardless of whether the thread has an active FP context.
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*/
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#endif /* CONFIG_FPU_SHARING */
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#elif defined(CONFIG_ARMV7_R)
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#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A)
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/* Store rest of process context */
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cps #MODE_SYS
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stm r0, {r4-r11, sp}
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movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
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msr BASEPRI_MAX, r0
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isb /* Make the effect of disabling interrupts be realized immediately */
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#elif defined(CONFIG_ARMV7_R)
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#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A)
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/*
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* Interrupts are still disabled from arch_swap so empty clause
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* here to avoid the preprocessor error below
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/* load callee-saved + psp from thread */
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add r0, r2, #_thread_offset_to_callee_saved
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ldmia r0, {v1-v8, ip}
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#elif defined(CONFIG_ARMV7_R)
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#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A)
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_thread_irq_disabled:
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/* load _kernel into r1 and current k_thread into r2 */
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ldr r1, =_kernel
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bx lr
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#endif /* CONFIG_USERSPACE */
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#elif defined(CONFIG_ARMV7_R)
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#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A)
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/**
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*
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@ -6,10 +6,10 @@
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/**
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* @file
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* @brief New thread creation for ARM Cortex-M and Cortex-R
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* @brief New thread creation for ARM Cortex-A, Cortex-M and Cortex-R
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*
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* Core thread related primitives for the ARM Cortex-M and Cortex-R
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* processor architecture.
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* Core thread related primitives for the ARM Cortex-A, Cortex-M and
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* Cortex-R processor architecture.
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*/
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#include <kernel.h>
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"movs r1, #0\n\t"
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#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) \
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|| defined(CONFIG_ARMV7_R)
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|| defined(CONFIG_ARMV7_R) \
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|| defined(CONFIG_ARMV7_A)
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"cpsie i\n\t" /* __enable_irq() */
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#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
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"cpsie if\n\t" /* __enable_irq(); __enable_fault_irq() */
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*
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* @brief Setup interrupt stack
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*
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* On Cortex-R, the interrupt stack is set up by reset.S
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* On Cortex-A and Cortex-R, the interrupt stack is set up by reset.S
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*
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* @return N/A
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*/
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@ -27,7 +27,7 @@
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#if defined(CONFIG_CPU_CORTEX_M)
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#include <aarch32/cortex_m/stack.h>
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#include <aarch32/cortex_m/exc.h>
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#elif defined(CONFIG_CPU_CORTEX_R)
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#elif defined(CONFIG_CPU_CORTEX_R) || defined(CONFIG_CPU_AARCH32_CORTEX_A)
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#include <aarch32/cortex_a_r/stack.h>
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#include <aarch32/cortex_a_r/exc.h>
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#endif
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@ -37,7 +37,7 @@
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#include <arch/arm/aarch32/cortex_m/cpu.h>
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#include <arch/arm/aarch32/cortex_m/memory_map.h>
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#include <arch/common/sys_io.h>
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#elif defined(CONFIG_CPU_CORTEX_R)
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#elif defined(CONFIG_CPU_CORTEX_R) || defined(CONFIG_CPU_AARCH32_CORTEX_A)
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#include <arch/arm/aarch32/cortex_a_r/cpu.h>
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#include <arch/arm/aarch32/cortex_a_r/sys_io.h>
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#include <arch/arm/aarch32/cortex_a_r/timer.h>
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*/
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#if defined(CONFIG_USERSPACE)
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#define Z_THREAD_MIN_STACK_ALIGN CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE
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#elif defined(CONFIG_ARM_MMU)
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#elif defined(CONFIG_ARM_AARCH32_MMU)
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#define Z_THREAD_MIN_STACK_ALIGN CONFIG_ARM_MMU_REGION_MIN_ALIGN_AND_SIZE
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#else
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#define Z_THREAD_MIN_STACK_ALIGN ARCH_STACK_PTR_ALIGN
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@ -22,7 +22,7 @@
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#include <arch/arm/aarch32/exc.h>
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#include <irq.h>
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#if defined(CONFIG_CPU_CORTEX_R)
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#if defined(CONFIG_CPU_CORTEX_R) || defined(CONFIG_CPU_AARCH32_CORTEX_A)
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#include <arch/arm/aarch32/cortex_a_r/cpu.h>
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#endif
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: "=r"(key), "=r"(tmp)
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: "i"(_EXC_IRQ_DEFAULT_PRIO)
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: "memory");
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#elif defined(CONFIG_ARMV7_R)
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#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A)
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__asm__ volatile(
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"mrs %0, cpsr;"
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"and %0, #" TOSTR(I_BIT) ";"
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"msr BASEPRI, %0;"
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"isb;"
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: : "r"(key) : "memory");
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#elif defined(CONFIG_ARMV7_R)
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#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A)
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if (key != 0U) {
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return;
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}
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@ -53,7 +53,7 @@ do { \
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: [reason] "i" (reason_p), [id] "i" (_SVC_CALL_RUNTIME_EXCEPT) \
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: "memory"); \
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} while (false)
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#elif defined(CONFIG_ARMV7_R)
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#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A)
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/*
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* In order to support using svc for an exception while running in an
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* isr, stack $lr_svc before calling svc. While exiting the isr,
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