Add an entry for the RAM region assigned to soft peripherals that will
disable caching for that region. Without this, communication with the
FLPR coprocessor cannot be performed correctly.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Use generic name for structure in driver instead of specific chip name
for better compatibility.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Some files should be separated from the common folder to
each soc folder for future expansion of the chip.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Add support for fixed GPIO routes that don't have a configurable
route register, but still require mode configuration and enabling.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
This commit refactors the NPCX SoC hierarchy to improve maintainability and
enable future support for upcoming chips.
Key changes include:
1. Introduced a new `npcxn` subdirectory under `common/` to consolidate
shared components across the npcxn series.
2. Renamed and reorganized register access files for improved consistency.
3. Updated relevant Kconfig files, header files, and CMakeLists
for the new structure.
Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
Due to a change in linker script cortex_a_r/scripts/linker.ld
, the _image_ram_start has been changed so the Zephyr image
cannot be copied from flash to ram as expected
and cannot run properly.
It is replaced by CONFIG_SRAM_BASE_ADDRESS, the _image_ram_size is also
replaced by _flash_used as a preventive measure.
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Use esp_restart call to guarantee and registered
shutdown handlers will be triggered before rebooting.
This guarantees that subsystems like Wi-Fi and BLE
will deinit correctly.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This patch will set MMU permissions for rom_ext sections
It is possible to call the rom_ext code located in IMR
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
This patch will extend MMU mapping range for hwreg1 entry
because it is required to access lower register addresses
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
nrf54h20 device requires device runtime PM to be enabled when
device PM is in use.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Current code configures the higher bits ahead of drive strength
to be "1", this patch fix this issue.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Signed-off-by: Lei Xu <lei.xu@nxp.com>
Updated `CMakeLists.txt` and `Kconfig` to integrate power management
for RA8D1, RA8M1, and RA8T1.
Modified `Kconfig.defconfig` to configure ULPT timer as the system timer
when power management is enabled:
- Adjusted `SYS_CLOCK_HW_CYCLES_PER_SEC` and `SYS_CLOCK_TICKS_PER_SEC`
for ULPT timer.
- Disabled `CORTEX_M_SYSTICK` when ULPT timer is used as the system timer.
Implemented power management logic in the new `power.c` file for:
- RA8D1 (`soc/renesas/ra/ra8d1/power.c`)
- RA8M1 (`soc/renesas/ra/ra8m1/power.c`)
- RA8T1 (`soc/renesas/ra/ra8t1/power.c`)
Signed-off-by: Khanh Nguyen <khanh.nguyen.wz@bp.renesas.com>
This is the initial commit to support pinctrl driver for Renesas RZ/T2M
Corrected space in the comment.
Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Signed-off-by: Binh Nguyen <binh.nguyen.xw@renesas.com>
Renesas takes over the maintainer of SoC Renesas RZ/T2M to unify with
other RZ devices
- Move soc/renesas/rzt2m to soc/renesas/rz
- Support xSPI boot mode to boot code from flash
- Change to use HAL Renesas
Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Signed-off-by: Binh Nguyen <binh.nguyen.xw@renesas.com>
RAM power configuration is preserved through soft reset,
meaning that there is a risk of accessing powered off RAM blocks
when booting in different application (i.e. bootloader).
Add option to force all RAM blocks to be powered on
before triggering soft reset to prevent this from happening.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
The chip requires a successful sleep entry to change the PLL sequence.
By default, the IT8XXX2 chip enables the I2C0 alternate function, which
can cause the clock/data lines to meet the start condition, preventing
EC from entering sleep mode.
This commit disables the I2C0 alternate function before executing the
PLL sequence change to ensure that the EC can enter sleep mode
successfully.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
STM32F439 SoC is an STM32F429 with an integrated crypto/hash processor
providing hardware acceleration for encryption (AES and TDES) and hash
(MD5, SHA-1 and SHA-2).
Signed-off-by: Mathieu Anquetin <mathieu.anquetin@groupe-cahors.com>
Convert z_clock_hw_cycles_per_sec to unsigned int to increase
supported frequency range.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
This is the initial commit to support pinctrl driver for Renesas RZ/V2L
Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Add support for the RPU, real-time processing unit on Versal NET SoC.
It is based on Cortext-R52 processor.
The patch contains initial wiring and configuration for generic board
with OCM(1MB) and DDR(2G) memories, cpu, interrupt controller, global
timer and UART.
versalnet.dtsi contains common peripherals integrated into Versal NET
SoC, and versalnet_r52.dtsi has peripherals which are private to
Cortex-R52 processor.
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
Signed-off-by: Mubin Sayyed <mubin.sayyed@amd.com>
