This adds a new driver for Renesas RZ/T2M.
The driver allows configuration of pin direction,
pull up/down resistors, drive strength and slew rate,
and selection of function for a pin.
Signed-off-by: Wojciech Sipak <wsipak@antmicro.com>
To avoid complicating the initial code for supporting the SoC,
I have implemented only the bare minimum for now.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
This commit addst pinctrl support for Apollo4 SoCs.
Co-authored-by: Mateusz Sierszulski <msierszulski@antmicro.com>
Signed-off-by: Maciej Sobkowski <msobkowski@antmicro.com>
Add a new pinctrl driver for TI CC32XX SoC. The driver has not been
tested, just implemented following datasheet specs and checked that it
compiles. Consider this as a best-effort driver to remove custom pinmux
code in board files.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Added initial version of Infineon CAT1 Pin controller driver.
Added initial version of binding file for Infineon CAT1 Pinctrl driver.
Added initial version of dt header for Infineon CAT1 pinctrl driver.
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
Following updates previously done for other drivers, rename all
occurrences of S32 to NXP S32 to avoid ambiguity.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
This commit adds initial support for gecko pinctrl driver
Co-authored-by: Mateusz Sierszulski <msierszulski@antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Introduce Pinctrl driver for SIUL2 module present on NXP S32 devices,
which provides control over all pins, such as function selection and
electrical characteristics that appear on external chip pins.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
Refactor iMX RT pin control support to use more generic names, as the
IOMUXC peripheral is present on non RT iMX application cores.
Additionally, make selection of the pin control driver occur at the SOC
level.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This CL is the initial version for npcx pinctrl driver and introduces
pinctrl nodes for both IO-pads and peripheral devices for each npcx
series. Users can set pin configuration via these nodes in the board
layout DT file. It also wraps all configurations related to pin-muxing
in pinctrl_soc.h. Regarding the other pin properties, we will implement
them later.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Add pinctrl driver for CC13XX/CC26XX family of SoCs
to facilitate transition from pinmux to pinctrl.
`IOCPortConfigureSet()` from TI hal driverlib used to
implement the generic pinctrl driver.
Signed-off-by: Vaishnav Achath <vaishnav@beagleboard.org>
Add lpc iocon pinctrl driver. Driver handles IOCON clock initialization as
well as IOCON pin configuration
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This update current Atmel sam0 pinctrl initiative to current Zephyr
pinctrl API. It update current devicetree bindings and add the sam0
pinctrl driver.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This update current Atmel sam pinctrl initiative to current Zephyr
pinctrl API. It update current devicetree bindings and add the sam
pinctrl driver.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Add kinetis pinctrl driver. Driver initializes clocks for each port, and
exposes the pinctrl_configure_pins function required for pinctrl
support.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Introduce Pin Function Controller for Renesas R-Car family.
This first implementation support to set a given pin as gpio
or peripheral (GPSR), to set a peripheral function to a
pin (IPSR), to set pull-up, pull-down (PUEN, PUD).
In addition this driver allows to set driving capabilies(DRVCTRL).
Pins are identified thanks to the per SoC binding for
pin definition which also contains pin alternate function
parameters.
Some pins can also have driving capabilities, some have bias
capabilities.
In order to find the correct bias and drive registers pfc_r8a77951.c
describes the different registers.
Each SoCs or package will need to define getters
for these registers: pfc_rcar_get_bias_regs() and
pfc_rcar_get_drive_regs().
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Add initial support for nRF pin controller driver. The implementation in
this patch does not yet support any peripheral. Only states
representation and basic driver functionality is introduced.
Note:
The nrf_pin_configure function has been marked as __unused since it may
not be used in certain scenarios until all peripherals are supported by
the pinctrl driver. For example, if only UART/E is supported but the
board does not enable UART, the function will never get called. However,
that board will likely have other peripherals that will gain support in
the future.
Thanks to Marti Bolivar for bindings documentation.
Co-authored-by: Marti Bolivar <marti.bolivar@nordicsemi.no>
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add initial version for STM32 pinctrl driver. Driver has been written
re-using many of the already existing parts in
drivers/pinmux/pinmux_stm32.c.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add a pin control driver for GD32 SoCs using the AFIO model.
Thanks to Gerson Fernando Budke for testing and implementation
suggestions.
Co-authored-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Initial skeleton for pinctrl drivers. This patch includes common
infrastructure and API definitions for pinctrl drivers.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
